LXR uboot/arch/arm/include/asm/arch-ls102xa/ns

   1/* SPDX-License-Identifier: GPL-2.0+ */
   2/*
   3 * Copyright 2014 Freescale Semiconductor, Inc.
   4 */
   5
   6#ifndef __FSL_NS_ACCESS_H_
   7#define __FSL_NS_ACCESS_H_
   8
   9enum csu_cslx_ind {
  10        CSU_CSLX_PCIE2_IO = 0,
  11        CSU_CSLX_PCIE1_IO,
  12        CSU_CSLX_MG2TPR_IP,
  13        CSU_CSLX_IFC_MEM,
  14        CSU_CSLX_OCRAM,
  15        CSU_CSLX_GIC,
  16        CSU_CSLX_PCIE1,
  17        CSU_CSLX_OCRAM2,
  18        CSU_CSLX_QSPI_MEM,
  19        CSU_CSLX_PCIE2,
  20        CSU_CSLX_SATA,
  21        CSU_CSLX_USB3,
  22        CSU_CSLX_SERDES = 32,
  23        CSU_CSLX_QDMA,
  24        CSU_CSLX_LPUART2,
  25        CSU_CSLX_LPUART1,
  26        CSU_CSLX_LPUART4,
  27        CSU_CSLX_LPUART3,
  28        CSU_CSLX_LPUART6,
  29        CSU_CSLX_LPUART5,
  30        CSU_CSLX_DSPI2 = 40,
  31        CSU_CSLX_DSPI1,
  32        CSU_CSLX_QSPI,
  33        CSU_CSLX_ESDHC,
  34        CSU_CSLX_2D_ACE,
  35        CSU_CSLX_IFC,
  36        CSU_CSLX_I2C1,
  37        CSU_CSLX_USB2,
  38        CSU_CSLX_I2C3,
  39        CSU_CSLX_I2C2,
  40        CSU_CSLX_DUART2 = 50,
  41        CSU_CSLX_DUART1,
  42        CSU_CSLX_WDT2,
  43        CSU_CSLX_WDT1,
  44        CSU_CSLX_EDMA,
  45        CSU_CSLX_SYS_CNT,
  46        CSU_CSLX_DMA_MUX2,
  47        CSU_CSLX_DMA_MUX1,
  48        CSU_CSLX_DDR,
  49        CSU_CSLX_QUICC,
  50        CSU_CSLX_DCFG_CCU_RCPM = 60,
  51        CSU_CSLX_SECURE_BOOTROM,
  52        CSU_CSLX_SFP,
  53        CSU_CSLX_TMU,
  54        CSU_CSLX_SECURE_MONITOR,
  55        CSU_CSLX_RESERVED0,
  56        CSU_CSLX_ETSEC1,
  57        CSU_CSLX_SEC5_5,
  58        CSU_CSLX_ETSEC3,
  59        CSU_CSLX_ETSEC2,
  60        CSU_CSLX_GPIO2 = 70,
  61        CSU_CSLX_GPIO1,
  62        CSU_CSLX_GPIO4,
  63        CSU_CSLX_GPIO3,
  64        CSU_CSLX_PLATFORM_CONT,
  65        CSU_CSLX_CSU,
  66        CSU_CSLX_ASRC,
  67        CSU_CSLX_SPDIF,
  68        CSU_CSLX_FLEXCAN2,
  69        CSU_CSLX_FLEXCAN1,
  70        CSU_CSLX_FLEXCAN4 = 80,
  71        CSU_CSLX_FLEXCAN3,
  72        CSU_CSLX_SAI2,
  73        CSU_CSLX_SAI1,
  74        CSU_CSLX_SAI4,
  75        CSU_CSLX_SAI3,
  76        CSU_CSLX_FTM2,
  77        CSU_CSLX_FTM1,
  78        CSU_CSLX_FTM4,
  79        CSU_CSLX_FTM3,
  80        CSU_CSLX_FTM6 = 90,
  81        CSU_CSLX_FTM5,
  82        CSU_CSLX_FTM8,
  83        CSU_CSLX_FTM7,
  84        CSU_CSLX_EPU,
  85        CSU_CSLX_COP_DCSR,
  86        CSU_CSLX_DDI,
  87        CSU_CSLX_GDI,
  88        CSU_CSLX_RESERVED1,
  89        CSU_CSLX_USB3_PHY = 116,
  90        CSU_CSLX_RESERVED2,
  91        CSU_CSLX_MAX,
  92};
  93
  94#endif
  95