1/* SPDX-License-Identifier: GPL-2.0+ */ 2/* 3 * Copyright (C) 2011 Freescale Semiconductor, Inc. All Rights Reserved. 4 */ 5 6#ifndef __ASM_ARCH_MX6_IMX_REGS_H__ 7#define __ASM_ARCH_MX6_IMX_REGS_H__ 8 9#define ARCH_MXC 10 11#define ROMCP_ARB_BASE_ADDR 0x00000000 12#define ROMCP_ARB_END_ADDR 0x000FFFFF 13 14#ifdef CONFIG_MX6SL 15#define GPU_2D_ARB_BASE_ADDR 0x02200000 16#define GPU_2D_ARB_END_ADDR 0x02203FFF 17#define OPENVG_ARB_BASE_ADDR 0x02204000 18#define OPENVG_ARB_END_ADDR 0x02207FFF 19#elif (defined(CONFIG_MX6SX) || defined(CONFIG_MX6UL) || defined(CONFIG_MX6ULL)) 20#define CAAM_ARB_BASE_ADDR 0x00100000 21#define CAAM_ARB_END_ADDR 0x00107FFF 22#define GPU_ARB_BASE_ADDR 0x01800000 23#define GPU_ARB_END_ADDR 0x01803FFF 24#define APBH_DMA_ARB_BASE_ADDR 0x01804000 25#define APBH_DMA_ARB_END_ADDR 0x0180BFFF 26#define M4_BOOTROM_BASE_ADDR 0x007F8000 27 28#elif !defined(CONFIG_MX6SLL) 29#define CAAM_ARB_BASE_ADDR 0x00100000 30#define CAAM_ARB_END_ADDR 0x00103FFF 31#define APBH_DMA_ARB_BASE_ADDR 0x00110000 32#define APBH_DMA_ARB_END_ADDR 0x00117FFF 33#define HDMI_ARB_BASE_ADDR 0x00120000 34#define HDMI_ARB_END_ADDR 0x00128FFF 35#define GPU_3D_ARB_BASE_ADDR 0x00130000 36#define GPU_3D_ARB_END_ADDR 0x00133FFF 37#define GPU_2D_ARB_BASE_ADDR 0x00134000 38#define GPU_2D_ARB_END_ADDR 0x00137FFF 39#define DTCP_ARB_BASE_ADDR 0x00138000 40#define DTCP_ARB_END_ADDR 0x0013BFFF 41#endif /* CONFIG_MX6SL */ 42 43#define MXS_APBH_BASE APBH_DMA_ARB_BASE_ADDR 44#define MXS_GPMI_BASE (APBH_DMA_ARB_BASE_ADDR + 0x02000) 45#define MXS_BCH_BASE (APBH_DMA_ARB_BASE_ADDR + 0x04000) 46 47/* GPV - PL301 configuration ports */ 48#if (defined(CONFIG_MX6SX) || \ 49 defined(CONFIG_MX6UL) || defined(CONFIG_MX6ULL) || \ 50 defined(CONFIG_MX6SL) || defined(CONFIG_MX6SLL)) 51#define GPV2_BASE_ADDR 0x00D00000 52#define GPV3_BASE_ADDR 0x00E00000 53#define GPV4_BASE_ADDR 0x00F00000 54#define GPV5_BASE_ADDR 0x01000000 55#define GPV6_BASE_ADDR 0x01100000 56#define PCIE_ARB_BASE_ADDR 0x08000000 57#define PCIE_ARB_END_ADDR 0x08FFFFFF 58 59#else 60#define GPV2_BASE_ADDR 0x00200000 61#define GPV3_BASE_ADDR 0x00300000 62#define GPV4_BASE_ADDR 0x00800000 63#define PCIE_ARB_BASE_ADDR 0x01000000 64#define PCIE_ARB_END_ADDR 0x01FFFFFF 65#endif 66 67#define IRAM_BASE_ADDR 0x00900000 68#define SCU_BASE_ADDR 0x00A00000 69#define IC_INTERFACES_BASE_ADDR 0x00A00100 70#define GLOBAL_TIMER_BASE_ADDR 0x00A00200 71#define PRIVATE_TIMERS_WD_BASE_ADDR 0x00A00600 72#define IC_DISTRIBUTOR_BASE_ADDR 0x00A01000 73#define L2_PL310_BASE 0x00A02000 74#define GPV0_BASE_ADDR 0x00B00000 75#define GPV1_BASE_ADDR 0x00C00000 76 77#define AIPS1_ARB_BASE_ADDR 0x02000000 78#define AIPS1_ARB_END_ADDR 0x020FFFFF 79#define AIPS2_ARB_BASE_ADDR 0x02100000 80#define AIPS2_ARB_END_ADDR 0x021FFFFF 81/* AIPS3 only on i.MX6SX */ 82#define AIPS3_ARB_BASE_ADDR 0x02200000 83#define AIPS3_ARB_END_ADDR 0x022FFFFF 84#ifdef CONFIG_MX6SX 85#define WEIM_ARB_BASE_ADDR 0x50000000 86#define WEIM_ARB_END_ADDR 0x57FFFFFF 87#define QSPI0_AMBA_BASE 0x60000000 88#define QSPI0_AMBA_END 0x6FFFFFFF 89#define QSPI1_AMBA_BASE 0x70000000 90#define QSPI1_AMBA_END 0x7FFFFFFF 91#elif (defined(CONFIG_MX6UL) || defined(CONFIG_MX6ULL)) 92#define WEIM_ARB_BASE_ADDR 0x50000000 93#define WEIM_ARB_END_ADDR 0x57FFFFFF 94#define QSPI0_AMBA_BASE 0x60000000 95#define QSPI0_AMBA_END 0x6FFFFFFF 96#elif !defined(CONFIG_MX6SLL) 97#define SATA_ARB_BASE_ADDR 0x02200000 98#define SATA_ARB_END_ADDR 0x02203FFF 99#define OPENVG_ARB_BASE_ADDR 0x02204000 100#define OPENVG_ARB_END_ADDR 0x02207FFF 101#define HSI_ARB_BASE_ADDR 0x02208000 102#define HSI_ARB_END_ADDR 0x0220BFFF 103#define IPU1_ARB_BASE_ADDR 0x02400000 104#define IPU1_ARB_END_ADDR 0x027FFFFF 105#define IPU2_ARB_BASE_ADDR 0x02800000 106#define IPU2_ARB_END_ADDR 0x02BFFFFF 107#define WEIM_ARB_BASE_ADDR 0x08000000 108#define WEIM_ARB_END_ADDR 0x0FFFFFFF 109#endif 110 111#if (defined(CONFIG_MX6SLL) || defined(CONFIG_MX6SL) || \ 112 defined(CONFIG_MX6SX) || \ 113 defined(CONFIG_MX6UL) || defined(CONFIG_MX6ULL)) 114#define MMDC0_ARB_BASE_ADDR 0x80000000 115#define MMDC0_ARB_END_ADDR 0xFFFFFFFF 116#define MMDC1_ARB_BASE_ADDR 0xC0000000 117#define MMDC1_ARB_END_ADDR 0xFFFFFFFF 118#else 119#define MMDC0_ARB_BASE_ADDR 0x10000000 120#define MMDC0_ARB_END_ADDR 0x7FFFFFFF 121#define MMDC1_ARB_BASE_ADDR 0x80000000 122#define MMDC1_ARB_END_ADDR 0xFFFFFFFF 123#endif 124 125#ifndef CONFIG_MX6SX 126#define IPU_SOC_BASE_ADDR IPU1_ARB_BASE_ADDR 127#define IPU_SOC_OFFSET 0x00200000 128#endif 129 130/* Defines for Blocks connected via AIPS (SkyBlue) */ 131#define ATZ1_BASE_ADDR AIPS1_ARB_BASE_ADDR 132#define ATZ2_BASE_ADDR AIPS2_ARB_BASE_ADDR 133#define ATZ3_BASE_ADDR AIPS3_ARB_BASE_ADDR 134#define AIPS1_BASE_ADDR AIPS1_ON_BASE_ADDR 135#define AIPS2_BASE_ADDR AIPS2_ON_BASE_ADDR 136#define AIPS3_BASE_ADDR AIPS3_ON_BASE_ADDR 137 138#define SPDIF_BASE_ADDR (ATZ1_BASE_ADDR + 0x04000) 139#define ECSPI1_BASE_ADDR (ATZ1_BASE_ADDR + 0x08000) 140#define ECSPI2_BASE_ADDR (ATZ1_BASE_ADDR + 0x0C000) 141#define ECSPI3_BASE_ADDR (ATZ1_BASE_ADDR + 0x10000) 142#define ECSPI4_BASE_ADDR (ATZ1_BASE_ADDR + 0x14000) 143 144#define MX6SL_UART5_BASE_ADDR (ATZ1_BASE_ADDR + 0x18000) 145#define MX6SLL_UART4_BASE_ADDR (ATZ1_BASE_ADDR + 0x18000) 146#define MX6UL_UART7_BASE_ADDR (ATZ1_BASE_ADDR + 0x18000) 147#define MX6SL_UART2_BASE_ADDR (ATZ1_BASE_ADDR + 0x24000) 148#define MX6SLL_UART2_BASE_ADDR (ATZ1_BASE_ADDR + 0x24000) 149#define MX6UL_UART8_BASE_ADDR (ATZ1_BASE_ADDR + 0x24000) 150#define MX6SL_UART3_BASE_ADDR (ATZ1_BASE_ADDR + 0x34000) 151#define MX6SLL_UART3_BASE_ADDR (ATZ1_BASE_ADDR + 0x34000) 152#define MX6SL_UART4_BASE_ADDR (ATZ1_BASE_ADDR + 0x38000) 153 154#ifndef CONFIG_MX6SX 155#define ECSPI5_BASE_ADDR (ATZ1_BASE_ADDR + 0x18000) 156#endif 157#define UART1_IPS_BASE_ADDR (ATZ1_BASE_ADDR + 0x20000) 158#define UART1_BASE (ATZ1_BASE_ADDR + 0x20000) 159#define ESAI1_BASE_ADDR (ATZ1_BASE_ADDR + 0x24000) 160#define UART8_BASE (ATZ1_BASE_ADDR + 0x24000) 161#define SSI1_BASE_ADDR (ATZ1_BASE_ADDR + 0x28000) 162#define SSI2_BASE_ADDR (ATZ1_BASE_ADDR + 0x2C000) 163#define SSI3_BASE_ADDR (ATZ1_BASE_ADDR + 0x30000) 164#define ASRC_BASE_ADDR (ATZ1_BASE_ADDR + 0x34000) 165 166#ifndef CONFIG_MX6SX 167#define SPBA_BASE_ADDR (ATZ1_BASE_ADDR + 0x3C000) 168#define VPU_BASE_ADDR (ATZ1_BASE_ADDR + 0x40000) 169#endif 170#define AIPS1_ON_BASE_ADDR (ATZ1_BASE_ADDR + 0x7C000) 171 172#define AIPS1_OFF_BASE_ADDR (ATZ1_BASE_ADDR + 0x80000) 173#define PWM1_BASE_ADDR (AIPS1_OFF_BASE_ADDR + 0x0000) 174#define PWM2_BASE_ADDR (AIPS1_OFF_BASE_ADDR + 0x4000) 175#define PWM3_BASE_ADDR (AIPS1_OFF_BASE_ADDR + 0x8000) 176#define PWM4_BASE_ADDR (AIPS1_OFF_BASE_ADDR + 0xC000) 177#define CAN1_BASE_ADDR (AIPS1_OFF_BASE_ADDR + 0x10000) 178#define CAN2_BASE_ADDR (AIPS1_OFF_BASE_ADDR + 0x14000) 179/* QOSC on i.MX6SLL */ 180#define QOSC_BASE_ADDR (AIPS1_OFF_BASE_ADDR + 0x14000) 181#define GPT1_BASE_ADDR (AIPS1_OFF_BASE_ADDR + 0x18000) 182#define GPIO1_BASE_ADDR (AIPS1_OFF_BASE_ADDR + 0x1C000) 183#define GPIO2_BASE_ADDR (AIPS1_OFF_BASE_ADDR + 0x20000) 184#define GPIO3_BASE_ADDR (AIPS1_OFF_BASE_ADDR + 0x24000) 185#define GPIO4_BASE_ADDR (AIPS1_OFF_BASE_ADDR + 0x28000) 186#define GPIO5_BASE_ADDR (AIPS1_OFF_BASE_ADDR + 0x2C000) 187#define MX6UL_SNVS_LP_BASE_ADDR (AIPS1_OFF_BASE_ADDR + 0x30000) 188#define GPIO6_BASE_ADDR (AIPS1_OFF_BASE_ADDR + 0x30000) 189#define GPIO7_BASE_ADDR (AIPS1_OFF_BASE_ADDR + 0x34000) 190#define KPP_BASE_ADDR (AIPS1_OFF_BASE_ADDR + 0x38000) 191#define WDOG1_BASE_ADDR (AIPS1_OFF_BASE_ADDR + 0x3C000) 192#define WDOG2_BASE_ADDR (AIPS1_OFF_BASE_ADDR + 0x40000) 193#define ANATOP_BASE_ADDR (AIPS1_OFF_BASE_ADDR + 0x48000) 194#define USB_PHY0_BASE_ADDR (AIPS1_OFF_BASE_ADDR + 0x49000) 195#define USB_PHY1_BASE_ADDR (AIPS1_OFF_BASE_ADDR + 0x4a000) 196#define CCM_BASE_ADDR (AIPS1_OFF_BASE_ADDR + 0x44000) 197#define SNVS_BASE_ADDR (AIPS1_OFF_BASE_ADDR + 0x4C000) 198#define EPIT1_BASE_ADDR (AIPS1_OFF_BASE_ADDR + 0x50000) 199#define EPIT2_BASE_ADDR (AIPS1_OFF_BASE_ADDR + 0x54000) 200#define SRC_BASE_ADDR (AIPS1_OFF_BASE_ADDR + 0x58000) 201#define GPC_BASE_ADDR (AIPS1_OFF_BASE_ADDR + 0x5C000) 202#define IOMUXC_BASE_ADDR (AIPS1_OFF_BASE_ADDR + 0x60000) 203#define IOMUXC_GPR_BASE_ADDR (AIPS1_OFF_BASE_ADDR + 0x64000) 204#ifdef CONFIG_MX6SLL 205#define CSI_BASE_ADDR (AIPS1_OFF_BASE_ADDR + 0x68000) 206#define SDMA_PORT_HOST_BASE_ADDR (AIPS1_OFF_BASE_ADDR + 0x6C000) 207#define PXP_BASE_ADDR (AIPS1_OFF_BASE_ADDR + 0x70000) 208#define EPDC_BASE_ADDR (AIPS1_OFF_BASE_ADDR + 0x74000) 209#define DCP_BASE_ADDR (AIPS1_OFF_BASE_ADDR + 0x7C000) 210#elif defined(CONFIG_MX6SL) 211#define CSI_BASE_ADDR (AIPS1_OFF_BASE_ADDR + 0x64000) 212#define SIPIX_BASE_ADDR (AIPS1_OFF_BASE_ADDR + 0x68000) 213#define SDMA_PORT_HOST_BASE_ADDR (AIPS1_OFF_BASE_ADDR + 0x6C000) 214#elif defined(CONFIG_MX6SX) 215#define CANFD1_BASE_ADDR (AIPS1_OFF_BASE_ADDR + 0x68000) 216#define SDMA_BASE_ADDR (AIPS1_OFF_BASE_ADDR + 0x6C000) 217#define CANFD2_BASE_ADDR (AIPS1_OFF_BASE_ADDR + 0x70000) 218#define SEMAPHORE1_BASE_ADDR (AIPS1_OFF_BASE_ADDR + 0x74000) 219#define SEMAPHORE2_BASE_ADDR (AIPS1_OFF_BASE_ADDR + 0x78000) 220#define RDC_BASE_ADDR (AIPS1_OFF_BASE_ADDR + 0x7C000) 221#else 222#define DCIC1_BASE_ADDR (AIPS1_OFF_BASE_ADDR + 0x64000) 223#define DCIC2_BASE_ADDR (AIPS1_OFF_BASE_ADDR + 0x68000) 224#define DMA_REQ_PORT_HOST_BASE_ADDR (AIPS1_OFF_BASE_ADDR + 0x6C000) 225#endif 226 227#define MX6SL_LCDIF_BASE_ADDR (AIPS1_OFF_BASE_ADDR + 0x78000) 228#define MX6SLL_LCDIF_BASE_ADDR (AIPS1_OFF_BASE_ADDR + 0x78000) 229 230#define AIPS2_ON_BASE_ADDR (ATZ2_BASE_ADDR + 0x7C000) 231#define AIPS2_OFF_BASE_ADDR (ATZ2_BASE_ADDR + 0x80000) 232#define AIPS3_ON_BASE_ADDR (ATZ3_BASE_ADDR + 0x7C000) 233#define AIPS3_OFF_BASE_ADDR (ATZ3_BASE_ADDR + 0x80000) 234#if defined(CONFIG_MX6UL) 235#define CAAM_BASE_ADDR (ATZ2_BASE_ADDR + 0x40000) 236#else 237#define CAAM_BASE_ADDR (ATZ2_BASE_ADDR) 238#endif 239#define ARM_BASE_ADDR (ATZ2_BASE_ADDR + 0x40000) 240 241#define CONFIG_SYS_FSL_SEC_OFFSET 0 242#define CONFIG_SYS_FSL_SEC_ADDR (CAAM_BASE_ADDR + \ 243 CONFIG_SYS_FSL_SEC_OFFSET) 244#define CONFIG_SYS_FSL_JR0_OFFSET 0x1000 245#define CONFIG_SYS_FSL_JR0_ADDR (CAAM_BASE_ADDR + \ 246 CONFIG_SYS_FSL_JR0_OFFSET) 247#define CONFIG_SYS_FSL_MAX_NUM_OF_SEC 1 248 249#define USB_PL301_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0x0000) 250#define USB_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0x4000) 251 252#define ENET_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0x8000) 253#ifdef CONFIG_MX6SL 254#define MSHC_IPS_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0xC000) 255#else 256#define MLB_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0xC000) 257#endif 258 259#define USDHC1_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0x10000) 260#define USDHC2_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0x14000) 261#define USDHC3_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0x18000) 262#define USDHC4_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0x1C000) 263#define I2C1_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0x20000) 264#define I2C2_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0x24000) 265#define I2C3_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0x28000) 266#define ROMCP_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0x2C000) 267#define MMDC_P0_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0x30000) 268/* i.MX6SL/SLL */ 269#define RNGB_IPS_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0x34000) 270#if (defined(CONFIG_MX6UL) || defined(CONFIG_MX6ULL)) 271#define ENET2_BASE_ADDR (AIPS1_OFF_BASE_ADDR + 0x34000) 272#else 273/* i.MX6SX */ 274#define ENET2_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0x34000) 275#endif 276/* i.MX6DQ/SDL */ 277#define MMDC_P1_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0x34000) 278 279#define WEIM_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0x38000) 280#define OCOTP_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0x3C000) 281#define CSU_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0x40000) 282#ifdef CONFIG_MX6SLL 283#define IOMUXC_GPR_SNVS_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0x44000) 284#define IOMUXC_SNVS_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0x48000) 285#endif 286#define IP2APB_PERFMON1_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0x44000) 287#define IP2APB_PERFMON2_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0x48000) 288#define MX6UL_LCDIF1_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0x48000) 289#define MX6ULL_LCDIF1_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0x48000) 290#ifdef CONFIG_MX6SX 291#define DEBUG_MONITOR_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0x4C000) 292#else 293#define IP2APB_PERFMON3_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0x4C000) 294#endif 295#define IP2APB_TZASC1_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0x50000) 296#if (defined(CONFIG_MX6UL) || defined(CONFIG_MX6ULL)) 297#define SCTR_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0x5C000) 298#define QSPI0_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0x60000) 299#define UART6_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0x7C000) 300#elif defined(CONFIG_MX6SX) 301#define SAI1_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0x54000) 302#define AUDMUX_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0x58000) 303#define SAI2_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0x5C000) 304#define QSPI0_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0x60000) 305#define QSPI1_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0x64000) 306#else 307#define IP2APB_TZASC2_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0x54000) 308#define MIPI_CSI2_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0x5C000) 309#define MIPI_DSI_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0x60000) 310#define VDOA_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0x64000) 311#endif 312#define MX6UL_WDOG3_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0x64000) 313#define UART2_BASE (AIPS2_OFF_BASE_ADDR + 0x68000) 314#define UART3_BASE (AIPS2_OFF_BASE_ADDR + 0x6C000) 315#define UART4_BASE (AIPS2_OFF_BASE_ADDR + 0x70000) 316#define UART5_BASE (AIPS2_OFF_BASE_ADDR + 0x74000) 317#define I2C4_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0x78000) 318#define IP2APB_USBPHY1_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0x78000) 319#define IP2APB_USBPHY2_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0x7C000) 320/* i.MX6SLL */ 321#define MTR_MASTER_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0x7C000) 322 323#ifdef CONFIG_MX6SX 324#define GIS_BASE_ADDR (AIPS3_ARB_BASE_ADDR + 0x04000) 325#define DCIC1_BASE_ADDR (AIPS3_ARB_BASE_ADDR + 0x0C000) 326#define DCIC2_BASE_ADDR (AIPS3_ARB_BASE_ADDR + 0x10000) 327#define CSI1_BASE_ADDR (AIPS3_ARB_BASE_ADDR + 0x14000) 328#define PXP_BASE_ADDR (AIPS3_ARB_BASE_ADDR + 0x18000) 329#define CSI2_BASE_ADDR (AIPS3_ARB_BASE_ADDR + 0x1C000) 330#define VADC_BASE_ADDR (AIPS3_ARB_BASE_ADDR + 0x28000) 331#define VDEC_BASE_ADDR (AIPS3_ARB_BASE_ADDR + 0x2C000) 332#define SPBA_BASE_ADDR (AIPS3_ARB_BASE_ADDR + 0x3C000) 333#define AIPS3_CONFIG_BASE_ADDR (AIPS3_ARB_BASE_ADDR + 0x7C000) 334#define ADC1_BASE_ADDR (AIPS3_ARB_BASE_ADDR + 0x80000) 335#define ADC2_BASE_ADDR (AIPS3_ARB_BASE_ADDR + 0x84000) 336#define ECSPI5_BASE_ADDR (AIPS3_ARB_BASE_ADDR + 0x8C000) 337#define HS_BASE_ADDR (AIPS3_ARB_BASE_ADDR + 0x90000) 338#define MU_MCU_BASE_ADDR (AIPS3_ARB_BASE_ADDR + 0x94000) 339#define CANFD_BASE_ADDR (AIPS3_ARB_BASE_ADDR + 0x98000) 340#define MU_DSP_BASE_ADDR (AIPS3_ARB_BASE_ADDR + 0x9C000) 341#define UART6_BASE_ADDR (AIPS3_ARB_BASE_ADDR + 0xA0000) 342#define PWM5_BASE_ADDR (AIPS3_ARB_BASE_ADDR + 0xA4000) 343#define PWM6_BASE_ADDR (AIPS3_ARB_BASE_ADDR + 0xA8000) 344#define PWM7_BASE_ADDR (AIPS3_ARB_BASE_ADDR + 0xAC000) 345#define PWM8_BASE_ADDR (AIPS3_ARB_BASE_ADDR + 0xB0000) 346#elif (defined(CONFIG_MX6UL) || defined(CONFIG_MX6ULL)) 347#define AIPS3_CONFIG_BASE_ADDR (AIPS3_ARB_BASE_ADDR + 0x7C000) 348#define DCP_BASE_ADDR (AIPS3_ARB_BASE_ADDR + 0x80000) 349#define RNGB_BASE_ADDR (AIPS3_ARB_BASE_ADDR + 0x84000) 350#define UART8_IPS_BASE_ADDR (AIPS3_ARB_BASE_ADDR + 0x88000) 351#define EPDC_BASE_ADDR (AIPS3_ARB_BASE_ADDR + 0x8C000) 352#define IOMUXC_SNVS_BASE_ADDR (AIPS3_ARB_BASE_ADDR + 0x90000) 353#define SNVS_GPR_BASE_ADDR (AIPS3_ARB_BASE_ADDR + 0x94000) 354#endif 355 356#define NOC_DDR_BASE_ADDR (GPV0_BASE_ADDR + 0xB0000) 357 358/* Only for i.MX6SX */ 359#define LCDIF2_BASE_ADDR (AIPS3_ARB_BASE_ADDR + 0x24000) 360#define MX6SX_LCDIF1_BASE_ADDR (AIPS3_ARB_BASE_ADDR + 0x20000) 361#define MX6SX_WDOG3_BASE_ADDR (AIPS3_ARB_BASE_ADDR + 0x88000) 362 363#if !(defined(CONFIG_MX6SX) || \ 364 defined(CONFIG_MX6UL) || defined(CONFIG_MX6ULL) || \ 365 defined(CONFIG_MX6SLL) || defined(CONFIG_MX6SL)) 366#define IRAM_SIZE 0x00040000 367#else 368#define IRAM_SIZE 0x00020000 369#endif 370#define FEC_QUIRK_ENET_MAC 371 372#include <asm/mach-imx/regs-lcdif.h> 373#if !(defined(__KERNEL_STRICT_NAMES) || defined(__ASSEMBLY__)) 374#include <asm/types.h> 375 376/* only for i.MX6SX/UL */ 377#define WDOG3_BASE_ADDR (((is_mx6ul() || is_mx6ull()) ? \ 378 MX6UL_WDOG3_BASE_ADDR : MX6SX_WDOG3_BASE_ADDR)) 379#define LCDIF1_BASE_ADDR ((is_cpu_type(MXC_CPU_MX6SLL)) ? \ 380 MX6SLL_LCDIF_BASE_ADDR : \ 381 (is_cpu_type(MXC_CPU_MX6SL)) ? \ 382 MX6SL_LCDIF_BASE_ADDR : \ 383 ((is_cpu_type(MXC_CPU_MX6UL)) ? \ 384 MX6UL_LCDIF1_BASE_ADDR : \ 385 ((is_mx6ull()) ? \ 386 MX6ULL_LCDIF1_BASE_ADDR : MX6SX_LCDIF1_BASE_ADDR))) 387 388 389extern void imx_get_mac_from_fuse(int dev_id, unsigned char *mac); 390 391#define SRC_SCR_CORE_1_RESET_OFFSET 14 392#define SRC_SCR_CORE_1_RESET_MASK (1<<SRC_SCR_CORE_1_RESET_OFFSET) 393#define SRC_SCR_CORE_2_RESET_OFFSET 15 394#define SRC_SCR_CORE_2_RESET_MASK (1<<SRC_SCR_CORE_2_RESET_OFFSET) 395#define SRC_SCR_CORE_3_RESET_OFFSET 16 396#define SRC_SCR_CORE_3_RESET_MASK (1<<SRC_SCR_CORE_3_RESET_OFFSET) 397#define SRC_SCR_CORE_1_ENABLE_OFFSET 22 398#define SRC_SCR_CORE_1_ENABLE_MASK (1<<SRC_SCR_CORE_1_ENABLE_OFFSET) 399#define SRC_SCR_CORE_2_ENABLE_OFFSET 23 400#define SRC_SCR_CORE_2_ENABLE_MASK (1<<SRC_SCR_CORE_2_ENABLE_OFFSET) 401#define SRC_SCR_CORE_3_ENABLE_OFFSET 24 402#define SRC_SCR_CORE_3_ENABLE_MASK (1<<SRC_SCR_CORE_3_ENABLE_OFFSET) 403 404struct rdc_regs { 405 u32 vir; /* Version information */ 406 u32 reserved1[8]; 407 u32 stat; /* Status */ 408 u32 intctrl; /* Interrupt and Control */ 409 u32 intstat; /* Interrupt Status */ 410 u32 reserved2[116]; 411 u32 mda[32]; /* Master Domain Assignment */ 412 u32 reserved3[96]; 413 u32 pdap[104]; /* Peripheral Domain Access Permissions */ 414 u32 reserved4[88]; 415 struct { 416 u32 mrsa; /* Memory Region Start Address */ 417 u32 mrea; /* Memory Region End Address */ 418 u32 mrc; /* Memory Region Control */ 419 u32 mrvs; /* Memory Region Violation Status */ 420 } mem_region[55]; 421}; 422 423struct rdc_sema_regs { 424 u8 gate[64]; /* Gate */ 425 u16 rstgt; /* Reset Gate */ 426}; 427 428/* WEIM registers */ 429struct weim { 430 u32 cs0gcr1; 431 u32 cs0gcr2; 432 u32 cs0rcr1; 433 u32 cs0rcr2; 434 u32 cs0wcr1; 435 u32 cs0wcr2; 436 437 u32 cs1gcr1; 438 u32 cs1gcr2; 439 u32 cs1rcr1; 440 u32 cs1rcr2; 441 u32 cs1wcr1; 442 u32 cs1wcr2; 443 444 u32 cs2gcr1; 445 u32 cs2gcr2; 446 u32 cs2rcr1; 447 u32 cs2rcr2; 448 u32 cs2wcr1; 449 u32 cs2wcr2; 450 451 u32 cs3gcr1; 452 u32 cs3gcr2; 453 u32 cs3rcr1; 454 u32 cs3rcr2; 455 u32 cs3wcr1; 456 u32 cs3wcr2; 457 458 u32 unused[12]; 459 460 u32 wcr; 461 u32 wiar; 462 u32 ear; 463}; 464 465/* System Reset Controller (SRC) */ 466struct src { 467 u32 scr; 468 u32 sbmr1; 469 u32 srsr; 470 u32 reserved1[2]; 471 u32 sisr; 472 u32 simr; 473 u32 sbmr2; 474 u32 gpr1; 475 u32 gpr2; 476 u32 gpr3; 477 u32 gpr4; 478 u32 gpr5; 479 u32 gpr6; 480 u32 gpr7; 481 u32 gpr8; 482 u32 gpr9; 483 u32 gpr10; 484}; 485 486#define src_base ((struct src *)SRC_BASE_ADDR) 487 488#define SRC_M4_REG_OFFSET 0 489#define SRC_M4_ENABLE_OFFSET 22 490#define SRC_M4_ENABLE_MASK BIT(22) 491#define SRC_M4C_NON_SCLR_RST_OFFSET 4 492#define SRC_M4C_NON_SCLR_RST_MASK BIT(4) 493 494/* GPR1 bitfields */ 495#define IOMUXC_GPR1_APP_CLK_REQ_N BIT(30) 496#define IOMUXC_GPR1_PCIE_EXIT_L1 BIT(28) 497#define IOMUXC_GPR1_PCIE_RDY_L23 BIT(27) 498#define IOMUXC_GPR1_PCIE_ENTER_L1 BIT(26) 499#define IOMUXC_GPR1_MIPI_COLOR_SW BIT(25) 500#define IOMUXC_GPR1_DPI_OFF BIT(24) 501#define IOMUXC_GPR1_EXC_MON_SLVE BIT(22) 502#define IOMUXC_GPR1_ENET_CLK_SEL_OFFSET 21 503#define IOMUXC_GPR1_ENET_CLK_SEL_MASK (1 << IOMUXC_GPR1_ENET_CLK_SEL_OFFSET) 504#define IOMUXC_GPR1_MIPI_IPU2_MUX_IOMUX BIT(20) 505#define IOMUXC_GPR1_MIPI_IPU1_MUX_IOMUX BIT(19) 506#define IOMUXC_GPR1_PCIE_TEST_PD BIT(18) 507#define IOMUXC_GPR1_IPU_VPU_MUX_IPU2 BIT(17) 508#define IOMUXC_GPR1_PCIE_REF_CLK_EN BIT(16) 509#define IOMUXC_GPR1_USB_EXP_MODE BIT(15) 510#define IOMUXC_GPR1_PCIE_INT BIT(14) 511#define IOMUXC_GPR1_USB_OTG_ID_OFFSET 13 512#define IOMUXC_GPR1_USB_OTG_ID_SEL_MASK (1 << IOMUXC_GPR1_USB_OTG_ID_OFFSET) 513#define IOMUXC_GPR1_GINT BIT(12) 514#define IOMUXC_GPR1_ADDRS3_MASK (0x3 << 10) 515#define IOMUXC_GPR1_ADDRS3_32MB (0x0 << 10) 516#define IOMUXC_GPR1_ADDRS3_64MB (0x1 << 10) 517#define IOMUXC_GPR1_ADDRS3_128MB (0x2 << 10) 518#define IOMUXC_GPR1_ACT_CS3 BIT(9) 519#define IOMUXC_GPR1_ADDRS2_MASK (0x3 << 7) 520#define IOMUXC_GPR1_ACT_CS2 BIT(6) 521#define IOMUXC_GPR1_ADDRS1_MASK (0x3 << 4) 522#define IOMUXC_GPR1_ACT_CS1 BIT(3) 523#define IOMUXC_GPR1_ADDRS0_OFFSET (1) 524#define IOMUXC_GPR1_ADDRS0_MASK (0x3 << 1) 525#define IOMUXC_GPR1_ACT_CS0 BIT(0) 526 527/* GPR3 bitfields */ 528#define IOMUXC_GPR3_GPU_DBG_OFFSET 29 529#define IOMUXC_GPR3_GPU_DBG_MASK (3<<IOMUXC_GPR3_GPU_DBG_OFFSET) 530#define IOMUXC_GPR3_BCH_WR_CACHE_CTL_OFFSET 28 531#define IOMUXC_GPR3_BCH_WR_CACHE_CTL_MASK (1<<IOMUXC_GPR3_BCH_WR_CACHE_CTL_OFFSET) 532#define IOMUXC_GPR3_BCH_RD_CACHE_CTL_OFFSET 27 533#define IOMUXC_GPR3_BCH_RD_CACHE_CTL_MASK (1<<IOMUXC_GPR3_BCH_RD_CACHE_CTL_OFFSET) 534#define IOMUXC_GPR3_uSDHCx_WR_CACHE_CTL_OFFSET 26 535#define IOMUXC_GPR3_uSDHCx_WR_CACHE_CTL_MASK (1<<IOMUXC_GPR3_uSDHCx_WR_CACHE_CTL_OFFSET) 536#define IOMUXC_GPR3_uSDHCx_RD_CACHE_CTL_OFFSET 25 537#define IOMUXC_GPR3_uSDHCx_RD_CACHE_CTL_MASK (1<<IOMUXC_GPR3_uSDHCx_RD_CACHE_CTL_OFFSET) 538#define IOMUXC_GPR3_OCRAM_CTL_OFFSET 21 539#define IOMUXC_GPR3_OCRAM_CTL_MASK (0xf<<IOMUXC_GPR3_OCRAM_CTL_OFFSET) 540#define IOMUXC_GPR3_OCRAM_STATUS_OFFSET 17 541#define IOMUXC_GPR3_OCRAM_STATUS_MASK (0xf<<IOMUXC_GPR3_OCRAM_STATUS_OFFSET) 542#define IOMUXC_GPR3_CORE3_DBG_ACK_EN_OFFSET 16 543#define IOMUXC_GPR3_CORE3_DBG_ACK_EN_MASK (1<<IOMUXC_GPR3_CORE3_DBG_ACK_EN_OFFSET) 544#define IOMUXC_GPR3_CORE2_DBG_ACK_EN_OFFSET 15 545#define IOMUXC_GPR3_CORE2_DBG_ACK_EN_MASK (1<<IOMUXC_GPR3_CORE2_DBG_ACK_EN_OFFSET) 546#define IOMUXC_GPR3_CORE1_DBG_ACK_EN_OFFSET 14 547#define IOMUXC_GPR3_CORE1_DBG_ACK_EN_MASK (1<<IOMUXC_GPR3_CORE1_DBG_ACK_EN_OFFSET) 548#define IOMUXC_GPR3_CORE0_DBG_ACK_EN_OFFSET 13 549#define IOMUXC_GPR3_CORE0_DBG_ACK_EN_MASK (1<<IOMUXC_GPR3_CORE0_DBG_ACK_EN_OFFSET) 550#define IOMUXC_GPR3_TZASC2_BOOT_LOCK_OFFSET 12 551#define IOMUXC_GPR3_TZASC2_BOOT_LOCK_MASK (1<<IOMUXC_GPR3_TZASC2_BOOT_LOCK_OFFSET) 552#define IOMUXC_GPR3_TZASC1_BOOT_LOCK_OFFSET 11 553#define IOMUXC_GPR3_TZASC1_BOOT_LOCK_MASK (1<<IOMUXC_GPR3_TZASC1_BOOT_LOCK_OFFSET) 554#define IOMUXC_GPR3_IPU_DIAG_OFFSET 10 555#define IOMUXC_GPR3_IPU_DIAG_MASK (1<<IOMUXC_GPR3_IPU_DIAG_OFFSET) 556 557#define IOMUXC_GPR3_MUX_SRC_IPU1_DI0 0 558#define IOMUXC_GPR3_MUX_SRC_IPU1_DI1 1 559#define IOMUXC_GPR3_MUX_SRC_IPU2_DI0 2 560#define IOMUXC_GPR3_MUX_SRC_IPU2_DI1 3 561 562#define IOMUXC_GPR3_LVDS1_MUX_CTL_OFFSET 8 563#define IOMUXC_GPR3_LVDS1_MUX_CTL_MASK (3<<IOMUXC_GPR3_LVDS1_MUX_CTL_OFFSET) 564 565#define IOMUXC_GPR3_LVDS0_MUX_CTL_OFFSET 6 566#define IOMUXC_GPR3_LVDS0_MUX_CTL_MASK (3<<IOMUXC_GPR3_LVDS0_MUX_CTL_OFFSET) 567 568#define IOMUXC_GPR3_MIPI_MUX_CTL_OFFSET 4 569#define IOMUXC_GPR3_MIPI_MUX_CTL_MASK (3<<IOMUXC_GPR3_MIPI_MUX_CTL_OFFSET) 570 571#define IOMUXC_GPR3_HDMI_MUX_CTL_OFFSET 2 572#define IOMUXC_GPR3_HDMI_MUX_CTL_MASK (3<<IOMUXC_GPR3_HDMI_MUX_CTL_OFFSET) 573 574/* gpr12 bitfields */ 575#define IOMUXC_GPR12_ARMP_IPG_CLK_EN BIT(27) 576#define IOMUXC_GPR12_ARMP_AHB_CLK_EN BIT(26) 577#define IOMUXC_GPR12_ARMP_ATB_CLK_EN BIT(25) 578#define IOMUXC_GPR12_ARMP_APB_CLK_EN BIT(24) 579#define IOMUXC_GPR12_DEVICE_TYPE (0xf << 12) 580#define IOMUXC_GPR12_PCIE_CTL_2 BIT(10) 581#define IOMUXC_GPR12_LOS_LEVEL (0x1f << 4) 582 583struct iomuxc { 584#if (defined(CONFIG_MX6SX) || defined(CONFIG_MX6UL) || defined(CONFIG_MX6ULL)) 585 u8 reserved[0x4000]; 586#endif 587 u32 gpr[14]; 588}; 589 590struct gpc { 591 u32 cntr; 592 u32 pgr; 593 u32 imr1; 594 u32 imr2; 595 u32 imr3; 596 u32 imr4; 597 u32 isr1; 598 u32 isr2; 599 u32 isr3; 600 u32 isr4; 601}; 602 603#define IOMUXC_GPR2_COUNTER_RESET_VAL_OFFSET 20 604#define IOMUXC_GPR2_COUNTER_RESET_VAL_MASK (3<<IOMUXC_GPR2_COUNTER_RESET_VAL_OFFSET) 605#define IOMUXC_GPR2_LVDS_CLK_SHIFT_OFFSET 16 606#define IOMUXC_GPR2_LVDS_CLK_SHIFT_MASK (7<<IOMUXC_GPR2_LVDS_CLK_SHIFT_OFFSET) 607 608#define IOMUXC_GPR2_BGREF_RRMODE_OFFSET 15 609#define IOMUXC_GPR2_BGREF_RRMODE_MASK (1<<IOMUXC_GPR2_BGREF_RRMODE_OFFSET) 610#define IOMUXC_GPR2_BGREF_RRMODE_INTERNAL_RES (1<<IOMUXC_GPR2_BGREF_RRMODE_OFFSET) 611#define IOMUXC_GPR2_BGREF_RRMODE_EXTERNAL_RES (0<<IOMUXC_GPR2_BGREF_RRMODE_OFFSET) 612#define IOMUXC_GPR2_VSYNC_ACTIVE_HIGH 0 613#define IOMUXC_GPR2_VSYNC_ACTIVE_LOW 1 614 615#define IOMUXC_GPR2_DI1_VS_POLARITY_OFFSET 10 616#define IOMUXC_GPR2_DI1_VS_POLARITY_MASK (1<<IOMUXC_GPR2_DI1_VS_POLARITY_OFFSET) 617#define IOMUXC_GPR2_DI1_VS_POLARITY_ACTIVE_HIGH (IOMUXC_GPR2_VSYNC_ACTIVE_HIGH<<IOMUXC_GPR2_DI1_VS_POLARITY_OFFSET) 618#define IOMUXC_GPR2_DI1_VS_POLARITY_ACTIVE_LOW (IOMUXC_GPR2_VSYNC_ACTIVE_LOW<<IOMUXC_GPR2_DI1_VS_POLARITY_OFFSET) 619 620#define IOMUXC_GPR2_DI0_VS_POLARITY_OFFSET 9 621#define IOMUXC_GPR2_DI0_VS_POLARITY_MASK (1<<IOMUXC_GPR2_DI0_VS_POLARITY_OFFSET) 622#define IOMUXC_GPR2_DI0_VS_POLARITY_ACTIVE_HIGH (IOMUXC_GPR2_VSYNC_ACTIVE_HIGH<<IOMUXC_GPR2_DI0_VS_POLARITY_OFFSET) 623#define IOMUXC_GPR2_DI0_VS_POLARITY_ACTIVE_LOW (IOMUXC_GPR2_VSYNC_ACTIVE_LOW<<IOMUXC_GPR2_DI0_VS_POLARITY_OFFSET) 624 625#define IOMUXC_GPR2_BITMAP_SPWG 0 626#define IOMUXC_GPR2_BITMAP_JEIDA 1 627 628#define IOMUXC_GPR2_BIT_MAPPING_CH1_OFFSET 8 629#define IOMUXC_GPR2_BIT_MAPPING_CH1_MASK (1<<IOMUXC_GPR2_BIT_MAPPING_CH1_OFFSET) 630#define IOMUXC_GPR2_BIT_MAPPING_CH1_JEIDA (IOMUXC_GPR2_BITMAP_JEIDA<<IOMUXC_GPR2_BIT_MAPPING_CH1_OFFSET) 631#define IOMUXC_GPR2_BIT_MAPPING_CH1_SPWG (IOMUXC_GPR2_BITMAP_SPWG<<IOMUXC_GPR2_BIT_MAPPING_CH1_OFFSET) 632 633#define IOMUXC_GPR2_DATA_WIDTH_18 0 634#define IOMUXC_GPR2_DATA_WIDTH_24 1 635 636#define IOMUXC_GPR2_DATA_WIDTH_CH1_OFFSET 7 637#define IOMUXC_GPR2_DATA_WIDTH_CH1_MASK (1<<IOMUXC_GPR2_DATA_WIDTH_CH1_OFFSET) 638#define IOMUXC_GPR2_DATA_WIDTH_CH1_18BIT (IOMUXC_GPR2_DATA_WIDTH_18<<IOMUXC_GPR2_DATA_WIDTH_CH1_OFFSET) 639#define IOMUXC_GPR2_DATA_WIDTH_CH1_24BIT (IOMUXC_GPR2_DATA_WIDTH_24<<IOMUXC_GPR2_DATA_WIDTH_CH1_OFFSET) 640 641#define IOMUXC_GPR2_BIT_MAPPING_CH0_OFFSET 6 642#define IOMUXC_GPR2_BIT_MAPPING_CH0_MASK (1<<IOMUXC_GPR2_BIT_MAPPING_CH0_OFFSET) 643#define IOMUXC_GPR2_BIT_MAPPING_CH0_JEIDA (IOMUXC_GPR2_BITMAP_JEIDA<<IOMUXC_GPR2_BIT_MAPPING_CH0_OFFSET) 644#define IOMUXC_GPR2_BIT_MAPPING_CH0_SPWG (IOMUXC_GPR2_BITMAP_SPWG<<IOMUXC_GPR2_BIT_MAPPING_CH0_OFFSET) 645 646#define IOMUXC_GPR2_DATA_WIDTH_CH0_OFFSET 5 647#define IOMUXC_GPR2_DATA_WIDTH_CH0_MASK (1<<IOMUXC_GPR2_DATA_WIDTH_CH0_OFFSET) 648#define IOMUXC_GPR2_DATA_WIDTH_CH0_18BIT (IOMUXC_GPR2_DATA_WIDTH_18<<IOMUXC_GPR2_DATA_WIDTH_CH0_OFFSET) 649#define IOMUXC_GPR2_DATA_WIDTH_CH0_24BIT (IOMUXC_GPR2_DATA_WIDTH_24<<IOMUXC_GPR2_DATA_WIDTH_CH0_OFFSET) 650 651#define IOMUXC_GPR2_SPLIT_MODE_EN_OFFSET 4 652#define IOMUXC_GPR2_SPLIT_MODE_EN_MASK (1<<IOMUXC_GPR2_SPLIT_MODE_EN_OFFSET) 653 654#define IOMUXC_GPR2_MODE_DISABLED 0 655#define IOMUXC_GPR2_MODE_ENABLED_DI0 1 656#define IOMUXC_GPR2_MODE_ENABLED_DI1 3 657 658#define IOMUXC_GPR2_LVDS_CH1_MODE_OFFSET 2 659#define IOMUXC_GPR2_LVDS_CH1_MODE_MASK (3<<IOMUXC_GPR2_LVDS_CH1_MODE_OFFSET) 660#define IOMUXC_GPR2_LVDS_CH1_MODE_DISABLED (IOMUXC_GPR2_MODE_DISABLED<<IOMUXC_GPR2_LVDS_CH1_MODE_OFFSET) 661#define IOMUXC_GPR2_LVDS_CH1_MODE_ENABLED_DI0 (IOMUXC_GPR2_MODE_ENABLED_DI0<<IOMUXC_GPR2_LVDS_CH1_MODE_OFFSET) 662#define IOMUXC_GPR2_LVDS_CH1_MODE_ENABLED_DI1 (IOMUXC_GPR2_MODE_ENABLED_DI1<<IOMUXC_GPR2_LVDS_CH1_MODE_OFFSET) 663 664#define IOMUXC_GPR2_LVDS_CH0_MODE_OFFSET 0 665#define IOMUXC_GPR2_LVDS_CH0_MODE_MASK (3<<IOMUXC_GPR2_LVDS_CH0_MODE_OFFSET) 666#define IOMUXC_GPR2_LVDS_CH0_MODE_DISABLED (IOMUXC_GPR2_MODE_DISABLED<<IOMUXC_GPR2_LVDS_CH0_MODE_OFFSET) 667#define IOMUXC_GPR2_LVDS_CH0_MODE_ENABLED_DI0 (IOMUXC_GPR2_MODE_ENABLED_DI0<<IOMUXC_GPR2_LVDS_CH0_MODE_OFFSET) 668#define IOMUXC_GPR2_LVDS_CH0_MODE_ENABLED_DI1 (IOMUXC_GPR2_MODE_ENABLED_DI1<<IOMUXC_GPR2_LVDS_CH0_MODE_OFFSET) 669 670/* ECSPI registers */ 671struct cspi_regs { 672 u32 rxdata; 673 u32 txdata; 674 u32 ctrl; 675 u32 cfg; 676 u32 intr; 677 u32 dma; 678 u32 stat; 679 u32 period; 680}; 681 682/* 683 * CSPI register definitions 684 */ 685#define MXC_ECSPI 686#define MXC_CSPICTRL_EN (1 << 0) 687#define MXC_CSPICTRL_MODE (1 << 1) 688#define MXC_CSPICTRL_XCH (1 << 2) 689#define MXC_CSPICTRL_MODE_MASK (0xf << 4) 690#define MXC_CSPICTRL_CHIPSELECT(x) (((x) & 0x3) << 12) 691#define MXC_CSPICTRL_BITCOUNT(x) (((x) & 0xfff) << 20) 692#define MXC_CSPICTRL_PREDIV(x) (((x) & 0xF) << 12) 693#define MXC_CSPICTRL_POSTDIV(x) (((x) & 0xF) << 8) 694#define MXC_CSPICTRL_SELCHAN(x) (((x) & 0x3) << 18) 695#define MXC_CSPICTRL_MAXBITS 0xfff 696#define MXC_CSPICTRL_TC (1 << 7) 697#define MXC_CSPICTRL_RXOVF (1 << 6) 698#define MXC_CSPIPERIOD_32KHZ (1 << 15) 699#define MAX_SPI_BYTES 32 700#define SPI_MAX_NUM 4 701 702/* Bit position inside CTRL register to be associated with SS */ 703#define MXC_CSPICTRL_CHAN 18 704 705/* Bit position inside CON register to be associated with SS */ 706#define MXC_CSPICON_PHA 0 /* SCLK phase control */ 707#define MXC_CSPICON_POL 4 /* SCLK polarity */ 708#define MXC_CSPICON_SSPOL 12 /* SS polarity */ 709#define MXC_CSPICON_CTL 20 /* inactive state of SCLK */ 710#if defined(CONFIG_MX6SLL) || defined(CONFIG_MX6SL) || \ 711 defined(CONFIG_MX6DL) || defined(CONFIG_MX6UL) || defined(CONFIG_MX6ULL) 712#define MXC_SPI_BASE_ADDRESSES \ 713 ECSPI1_BASE_ADDR, \ 714 ECSPI2_BASE_ADDR, \ 715 ECSPI3_BASE_ADDR, \ 716 ECSPI4_BASE_ADDR 717#else 718#define MXC_SPI_BASE_ADDRESSES \ 719 ECSPI1_BASE_ADDR, \ 720 ECSPI2_BASE_ADDR, \ 721 ECSPI3_BASE_ADDR, \ 722 ECSPI4_BASE_ADDR, \ 723 ECSPI5_BASE_ADDR 724#endif 725 726struct ocotp_regs { 727 u32 ctrl; 728 u32 ctrl_set; 729 u32 ctrl_clr; 730 u32 ctrl_tog; 731 u32 timing; 732 u32 rsvd0[3]; 733 u32 data; 734 u32 rsvd1[3]; 735 u32 read_ctrl; 736 u32 rsvd2[3]; 737 u32 read_fuse_data; 738 u32 rsvd3[3]; 739 u32 sw_sticky; 740 u32 rsvd4[3]; 741 u32 scs; 742 u32 scs_set; 743 u32 scs_clr; 744 u32 scs_tog; 745 u32 crc_addr; 746 u32 rsvd5[3]; 747 u32 crc_value; 748 u32 rsvd6[3]; 749 u32 version; 750 u32 rsvd7[0xdb]; 751 752 /* fuse banks */ 753 struct fuse_bank { 754 u32 fuse_regs[0x20]; 755 } bank[0]; 756}; 757 758struct fuse_bank0_regs { 759 u32 lock; 760 u32 rsvd0[3]; 761 u32 uid_low; 762 u32 rsvd1[3]; 763 u32 uid_high; 764 u32 rsvd2[3]; 765 u32 cfg2; 766 u32 rsvd3[3]; 767 u32 cfg3; 768 u32 rsvd4[3]; 769 u32 cfg4; 770 u32 rsvd5[3]; 771 u32 cfg5; 772 u32 rsvd6[3]; 773 u32 cfg6; 774 u32 rsvd7[3]; 775}; 776 777struct fuse_bank1_regs { 778 u32 mem0; 779 u32 rsvd0[3]; 780 u32 mem1; 781 u32 rsvd1[3]; 782 u32 mem2; 783 u32 rsvd2[3]; 784 u32 mem3; 785 u32 rsvd3[3]; 786 u32 mem4; 787 u32 rsvd4[3]; 788 u32 ana0; 789 u32 rsvd5[3]; 790 u32 ana1; 791 u32 rsvd6[3]; 792 u32 ana2; 793 u32 rsvd7[3]; 794}; 795 796struct fuse_bank4_regs { 797 u32 sjc_resp_low; 798 u32 rsvd0[3]; 799 u32 sjc_resp_high; 800 u32 rsvd1[3]; 801 u32 mac_addr0; 802 u32 rsvd2[3]; 803 u32 mac_addr1; 804 u32 rsvd3[3]; 805 u32 mac_addr2; /*For i.MX6SX and i.MX6UL*/ 806 u32 rsvd4[7]; 807 u32 gp1; 808 u32 rsvd5[3]; 809 u32 gp2; 810 u32 rsvd6[3]; 811}; 812 813struct aipstz_regs { 814 u32 mprot0; 815 u32 mprot1; 816 u32 rsvd[0xe]; 817 u32 opacr0; 818 u32 opacr1; 819 u32 opacr2; 820 u32 opacr3; 821 u32 opacr4; 822}; 823 824struct anatop_regs { 825 u32 pll_sys; /* 0x000 */ 826 u32 pll_sys_set; /* 0x004 */ 827 u32 pll_sys_clr; /* 0x008 */ 828 u32 pll_sys_tog; /* 0x00c */ 829 u32 usb1_pll_480_ctrl; /* 0x010 */ 830 u32 usb1_pll_480_ctrl_set; /* 0x014 */ 831 u32 usb1_pll_480_ctrl_clr; /* 0x018 */ 832 u32 usb1_pll_480_ctrl_tog; /* 0x01c */ 833 u32 usb2_pll_480_ctrl; /* 0x020 */ 834 u32 usb2_pll_480_ctrl_set; /* 0x024 */ 835 u32 usb2_pll_480_ctrl_clr; /* 0x028 */ 836 u32 usb2_pll_480_ctrl_tog; /* 0x02c */ 837 u32 pll_528; /* 0x030 */ 838 u32 pll_528_set; /* 0x034 */ 839 u32 pll_528_clr; /* 0x038 */ 840 u32 pll_528_tog; /* 0x03c */ 841 u32 pll_528_ss; /* 0x040 */ 842 u32 rsvd0[3]; 843 u32 pll_528_num; /* 0x050 */ 844 u32 rsvd1[3]; 845 u32 pll_528_denom; /* 0x060 */ 846 u32 rsvd2[3]; 847 u32 pll_audio; /* 0x070 */ 848 u32 pll_audio_set; /* 0x074 */ 849 u32 pll_audio_clr; /* 0x078 */ 850 u32 pll_audio_tog; /* 0x07c */ 851 u32 pll_audio_num; /* 0x080 */ 852 u32 rsvd3[3]; 853 u32 pll_audio_denom; /* 0x090 */ 854 u32 rsvd4[3]; 855 u32 pll_video; /* 0x0a0 */ 856 u32 pll_video_set; /* 0x0a4 */ 857 u32 pll_video_clr; /* 0x0a8 */ 858 u32 pll_video_tog; /* 0x0ac */ 859 u32 pll_video_num; /* 0x0b0 */ 860 u32 rsvd5[3]; 861 u32 pll_video_denom; /* 0x0c0 */ 862 u32 rsvd6[3]; 863 u32 pll_mlb; /* 0x0d0 */ 864 u32 pll_mlb_set; /* 0x0d4 */ 865 u32 pll_mlb_clr; /* 0x0d8 */ 866 u32 pll_mlb_tog; /* 0x0dc */ 867 u32 pll_enet; /* 0x0e0 */ 868 u32 pll_enet_set; /* 0x0e4 */ 869 u32 pll_enet_clr; /* 0x0e8 */ 870 u32 pll_enet_tog; /* 0x0ec */ 871 u32 pfd_480; /* 0x0f0 */ 872 u32 pfd_480_set; /* 0x0f4 */ 873 u32 pfd_480_clr; /* 0x0f8 */ 874 u32 pfd_480_tog; /* 0x0fc */ 875 u32 pfd_528; /* 0x100 */ 876 u32 pfd_528_set; /* 0x104 */ 877 u32 pfd_528_clr; /* 0x108 */ 878 u32 pfd_528_tog; /* 0x10c */ 879 u32 reg_1p1; /* 0x110 */ 880 u32 reg_1p1_set; /* 0x114 */ 881 u32 reg_1p1_clr; /* 0x118 */ 882 u32 reg_1p1_tog; /* 0x11c */ 883 u32 reg_3p0; /* 0x120 */ 884 u32 reg_3p0_set; /* 0x124 */ 885 u32 reg_3p0_clr; /* 0x128 */ 886 u32 reg_3p0_tog; /* 0x12c */ 887 u32 reg_2p5; /* 0x130 */ 888 u32 reg_2p5_set; /* 0x134 */ 889 u32 reg_2p5_clr; /* 0x138 */ 890 u32 reg_2p5_tog; /* 0x13c */ 891 u32 reg_core; /* 0x140 */ 892 u32 reg_core_set; /* 0x144 */ 893 u32 reg_core_clr; /* 0x148 */ 894 u32 reg_core_tog; /* 0x14c */ 895 u32 ana_misc0; /* 0x150 */ 896 u32 ana_misc0_set; /* 0x154 */ 897 u32 ana_misc0_clr; /* 0x158 */ 898 u32 ana_misc0_tog; /* 0x15c */ 899 u32 ana_misc1; /* 0x160 */ 900 u32 ana_misc1_set; /* 0x164 */ 901 u32 ana_misc1_clr; /* 0x168 */ 902 u32 ana_misc1_tog; /* 0x16c */ 903 u32 ana_misc2; /* 0x170 */ 904 u32 ana_misc2_set; /* 0x174 */ 905 u32 ana_misc2_clr; /* 0x178 */ 906 u32 ana_misc2_tog; /* 0x17c */ 907 u32 tempsense0; /* 0x180 */ 908 u32 tempsense0_set; /* 0x184 */ 909 u32 tempsense0_clr; /* 0x188 */ 910 u32 tempsense0_tog; /* 0x18c */ 911 u32 tempsense1; /* 0x190 */ 912 u32 tempsense1_set; /* 0x194 */ 913 u32 tempsense1_clr; /* 0x198 */ 914 u32 tempsense1_tog; /* 0x19c */ 915 u32 usb1_vbus_detect; /* 0x1a0 */ 916 u32 usb1_vbus_detect_set; /* 0x1a4 */ 917 u32 usb1_vbus_detect_clr; /* 0x1a8 */ 918 u32 usb1_vbus_detect_tog; /* 0x1ac */ 919 u32 usb1_chrg_detect; /* 0x1b0 */ 920 u32 usb1_chrg_detect_set; /* 0x1b4 */ 921 u32 usb1_chrg_detect_clr; /* 0x1b8 */ 922 u32 usb1_chrg_detect_tog; /* 0x1bc */ 923 u32 usb1_vbus_det_stat; /* 0x1c0 */ 924 u32 usb1_vbus_det_stat_set; /* 0x1c4 */ 925 u32 usb1_vbus_det_stat_clr; /* 0x1c8 */ 926 u32 usb1_vbus_det_stat_tog; /* 0x1cc */ 927 u32 usb1_chrg_det_stat; /* 0x1d0 */ 928 u32 usb1_chrg_det_stat_set; /* 0x1d4 */ 929 u32 usb1_chrg_det_stat_clr; /* 0x1d8 */ 930 u32 usb1_chrg_det_stat_tog; /* 0x1dc */ 931 u32 usb1_loopback; /* 0x1e0 */ 932 u32 usb1_loopback_set; /* 0x1e4 */ 933 u32 usb1_loopback_clr; /* 0x1e8 */ 934 u32 usb1_loopback_tog; /* 0x1ec */ 935 u32 usb1_misc; /* 0x1f0 */ 936 u32 usb1_misc_set; /* 0x1f4 */ 937 u32 usb1_misc_clr; /* 0x1f8 */ 938 u32 usb1_misc_tog; /* 0x1fc */ 939 u32 usb2_vbus_detect; /* 0x200 */ 940 u32 usb2_vbus_detect_set; /* 0x204 */ 941 u32 usb2_vbus_detect_clr; /* 0x208 */ 942 u32 usb2_vbus_detect_tog; /* 0x20c */ 943 u32 usb2_chrg_detect; /* 0x210 */ 944 u32 usb2_chrg_detect_set; /* 0x214 */ 945 u32 usb2_chrg_detect_clr; /* 0x218 */ 946 u32 usb2_chrg_detect_tog; /* 0x21c */ 947 u32 usb2_vbus_det_stat; /* 0x220 */ 948 u32 usb2_vbus_det_stat_set; /* 0x224 */ 949 u32 usb2_vbus_det_stat_clr; /* 0x228 */ 950 u32 usb2_vbus_det_stat_tog; /* 0x22c */ 951 u32 usb2_chrg_det_stat; /* 0x230 */ 952 u32 usb2_chrg_det_stat_set; /* 0x234 */ 953 u32 usb2_chrg_det_stat_clr; /* 0x238 */ 954 u32 usb2_chrg_det_stat_tog; /* 0x23c */ 955 u32 usb2_loopback; /* 0x240 */ 956 u32 usb2_loopback_set; /* 0x244 */ 957 u32 usb2_loopback_clr; /* 0x248 */ 958 u32 usb2_loopback_tog; /* 0x24c */ 959 u32 usb2_misc; /* 0x250 */ 960 u32 usb2_misc_set; /* 0x254 */ 961 u32 usb2_misc_clr; /* 0x258 */ 962 u32 usb2_misc_tog; /* 0x25c */ 963 u32 digprog; /* 0x260 */ 964 u32 reserved1[7]; 965 u32 digprog_sololite; /* 0x280 */ 966}; 967 968#define ANATOP_PFD_FRAC_SHIFT(n) ((n)*8) 969#define ANATOP_PFD_FRAC_MASK(n) (0x3f<<ANATOP_PFD_FRAC_SHIFT(n)) 970#define ANATOP_PFD_STABLE_SHIFT(n) (6+((n)*8)) 971#define ANATOP_PFD_STABLE_MASK(n) (1<<ANATOP_PFD_STABLE_SHIFT(n)) 972#define ANATOP_PFD_CLKGATE_SHIFT(n) (7+((n)*8)) 973#define ANATOP_PFD_CLKGATE_MASK(n) (1<<ANATOP_PFD_CLKGATE_SHIFT(n)) 974 975struct wdog_regs { 976 u16 wcr; /* Control */ 977 u16 wsr; /* Service */ 978 u16 wrsr; /* Reset Status */ 979 u16 wicr; /* Interrupt Control */ 980 u16 wmcr; /* Miscellaneous Control */ 981}; 982 983#define PWMCR_PRESCALER(x) (((x - 1) & 0xFFF) << 4) 984#define PWMCR_DOZEEN (1 << 24) 985#define PWMCR_WAITEN (1 << 23) 986#define PWMCR_DBGEN (1 << 22) 987#define PWMCR_CLKSRC_IPG_HIGH (2 << 16) 988#define PWMCR_CLKSRC_IPG (1 << 16) 989#define PWMCR_EN (1 << 0) 990 991struct pwm_regs { 992 u32 cr; 993 u32 sr; 994 u32 ir; 995 u32 sar; 996 u32 pr; 997 u32 cnr; 998}; 999 1000/*
1001 * If ROM fail back to USB recover mode, USBPH0_PWD will be clear to use USB 1002 * If boot from the other mode, USB0_PWD will keep reset value 1003 */ 1004#define is_boot_from_usb(void) (!(readl(USB_PHY0_BASE_ADDR) & (1<<20))) 1005 1006#endif /* __ASSEMBLER__*/ 1007#endif /* __ASM_ARCH_MX6_IMX_REGS_H__ */ 1008