LXR uboot/arch/arm/include/asm/arch-tegra/dc.h

   1/* SPDX-License-Identifier: GPL-2.0+ */
   2/*
   3 *  (C) Copyright 2010
   4 *  NVIDIA Corporation <www.nvidia.com>
   5 */
   6
   7#ifndef __ASM_ARCH_TEGRA_DC_H
   8#define __ASM_ARCH_TEGRA_DC_H
   9
  10/* Register definitions for the Tegra display controller */
  11
  12/* CMD register 0x000 ~ 0x43 */
  13struct dc_cmd_reg {
  14        /* Address 0x000 ~ 0x002 */
  15        uint gen_incr_syncpt;           /* _CMD_GENERAL_INCR_SYNCPT_0 */
  16        uint gen_incr_syncpt_ctrl;      /* _CMD_GENERAL_INCR_SYNCPT_CNTRL_0 */
  17        uint gen_incr_syncpt_err;       /* _CMD_GENERAL_INCR_SYNCPT_ERROR_0 */
  18
  19        uint reserved0[5];              /* reserved_0[5] */
  20
  21        /* Address 0x008 ~ 0x00a */
  22        uint win_a_incr_syncpt;         /* _CMD_WIN_A_INCR_SYNCPT_0 */
  23        uint win_a_incr_syncpt_ctrl;    /* _CMD_WIN_A_INCR_SYNCPT_CNTRL_0 */
  24        uint win_a_incr_syncpt_err;     /* _CMD_WIN_A_INCR_SYNCPT_ERROR_0 */
  25
  26        uint reserved1[5];              /* reserved_1[5] */
  27
  28        /* Address 0x010 ~ 0x012 */
  29        uint win_b_incr_syncpt;         /* _CMD_WIN_B_INCR_SYNCPT_0 */
  30        uint win_b_incr_syncpt_ctrl;    /* _CMD_WIN_B_INCR_SYNCPT_CNTRL_0 */
  31        uint win_b_incr_syncpt_err;     /* _CMD_WIN_B_INCR_SYNCPT_ERROR_0 */
  32
  33        uint reserved2[5];              /* reserved_2[5] */
  34
  35        /* Address 0x018 ~ 0x01a */
  36        uint win_c_incr_syncpt;         /* _CMD_WIN_C_INCR_SYNCPT_0 */
  37        uint win_c_incr_syncpt_ctrl;    /* _CMD_WIN_C_INCR_SYNCPT_CNTRL_0 */
  38        uint win_c_incr_syncpt_err;     /* _CMD_WIN_C_INCR_SYNCPT_ERROR_0 */
  39
  40        uint reserved3[13];             /* reserved_3[13] */
  41
  42        /* Address 0x028 */
  43        uint cont_syncpt_vsync;         /* _CMD_CONT_SYNCPT_VSYNC_0 */
  44
  45        uint reserved4[7];              /* reserved_4[7] */
  46
  47        /* Address 0x030 ~ 0x033 */
  48        uint ctxsw;                     /* _CMD_CTXSW_0 */
  49        uint disp_cmd_opt0;             /* _CMD_DISPLAY_COMMAND_OPTION0_0 */
  50        uint disp_cmd;                  /* _CMD_DISPLAY_COMMAND_0 */
  51        uint sig_raise;                 /* _CMD_SIGNAL_RAISE_0 */
  52
  53        uint reserved5[2];              /* reserved_0[2] */
  54
  55        /* Address 0x036 ~ 0x03e */
  56        uint disp_pow_ctrl;             /* _CMD_DISPLAY_POWER_CONTROL_0 */
  57        uint int_stat;                  /* _CMD_INT_STATUS_0 */
  58        uint int_mask;                  /* _CMD_INT_MASK_0 */
  59        uint int_enb;                   /* _CMD_INT_ENABLE_0 */
  60        uint int_type;                  /* _CMD_INT_TYPE_0 */
  61        uint int_polarity;              /* _CMD_INT_POLARITY_0 */
  62        uint sig_raise1;                /* _CMD_SIGNAL_RAISE1_0 */
  63        uint sig_raise2;                /* _CMD_SIGNAL_RAISE2_0 */
  64        uint sig_raise3;                /* _CMD_SIGNAL_RAISE3_0 */
  65
  66        uint reserved6;                 /* reserved_6 */
  67
  68        /* Address 0x040 ~ 0x043 */
  69        uint state_access;              /* _CMD_STATE_ACCESS_0 */
  70        uint state_ctrl;                /* _CMD_STATE_CONTROL_0 */
  71        uint disp_win_header;           /* _CMD_DISPLAY_WINDOW_HEADER_0 */
  72        uint reg_act_ctrl;              /* _CMD_REG_ACT_CONTROL_0 */
  73};
  74
  75enum {
  76        PIN_REG_COUNT           = 4,
  77        PIN_OUTPUT_SEL_COUNT    = 7,
  78};
  79
  80/* COM register 0x300 ~ 0x329 */
  81struct dc_com_reg {
  82        /* Address 0x300 ~ 0x301 */
  83        uint crc_ctrl;                  /* _COM_CRC_CONTROL_0 */
  84        uint crc_checksum;              /* _COM_CRC_CHECKSUM_0 */
  85
  86        /* _COM_PIN_OUTPUT_ENABLE0/1/2/3_0: Address 0x302 ~ 0x305 */
  87        uint pin_output_enb[PIN_REG_COUNT];
  88
  89        /* _COM_PIN_OUTPUT_POLARITY0/1/2/3_0: Address 0x306 ~ 0x309 */
  90        uint pin_output_polarity[PIN_REG_COUNT];
  91
  92        /* _COM_PIN_OUTPUT_DATA0/1/2/3_0: Address 0x30a ~ 0x30d */
  93        uint pin_output_data[PIN_REG_COUNT];
  94
  95        /* _COM_PIN_INPUT_ENABLE0_0: Address 0x30e ~ 0x311 */
  96        uint pin_input_enb[PIN_REG_COUNT];
  97
  98        /* Address 0x312 ~ 0x313 */
  99        uint pin_input_data0;           /* _COM_PIN_INPUT_DATA0_0 */
 100        uint pin_input_data1;           /* _COM_PIN_INPUT_DATA1_0 */
 101
 102        /* _COM_PIN_OUTPUT_SELECT0/1/2/3/4/5/6_0: Address 0x314 ~ 0x31a */
 103        uint pin_output_sel[PIN_OUTPUT_SEL_COUNT];
 104
 105        /* Address 0x31b ~ 0x329 */
 106        uint pin_misc_ctrl;             /* _COM_PIN_MISC_CONTROL_0 */
 107        uint pm0_ctrl;                  /* _COM_PM0_CONTROL_0 */
 108        uint pm0_duty_cycle;            /* _COM_PM0_DUTY_CYCLE_0 */
 109        uint pm1_ctrl;                  /* _COM_PM1_CONTROL_0 */
 110        uint pm1_duty_cycle;            /* _COM_PM1_DUTY_CYCLE_0 */
 111        uint spi_ctrl;                  /* _COM_SPI_CONTROL_0 */
 112        uint spi_start_byte;            /* _COM_SPI_START_BYTE_0 */
 113        uint hspi_wr_data_ab;           /* _COM_HSPI_WRITE_DATA_AB_0 */
 114        uint hspi_wr_data_cd;           /* _COM_HSPI_WRITE_DATA_CD */
 115        uint hspi_cs_dc;                /* _COM_HSPI_CS_DC_0 */
 116        uint scratch_reg_a;             /* _COM_SCRATCH_REGISTER_A_0 */
 117        uint scratch_reg_b;             /* _COM_SCRATCH_REGISTER_B_0 */
 118        uint gpio_ctrl;                 /* _COM_GPIO_CTRL_0 */
 119        uint gpio_debounce_cnt;         /* _COM_GPIO_DEBOUNCE_COUNTER_0 */
 120        uint crc_checksum_latched;      /* _COM_CRC_CHECKSUM_LATCHED_0 */
 121};
 122
 123enum dc_disp_h_pulse_pos {
 124        H_PULSE0_POSITION_A,
 125        H_PULSE0_POSITION_B,
 126        H_PULSE0_POSITION_C,
 127        H_PULSE0_POSITION_D,
 128        H_PULSE0_POSITION_COUNT,
 129};
 130
 131struct _disp_h_pulse {
 132        /* _DISP_H_PULSE0/1/2_CONTROL_0 */
 133        uint h_pulse_ctrl;
 134        /* _DISP_H_PULSE0/1/2_POSITION_A/B/C/D_0 */
 135        uint h_pulse_pos[H_PULSE0_POSITION_COUNT];
 136};
 137
 138enum dc_disp_v_pulse_pos {
 139        V_PULSE0_POSITION_A,
 140        V_PULSE0_POSITION_B,
 141        V_PULSE0_POSITION_C,
 142        V_PULSE0_POSITION_COUNT,
 143};
 144
 145struct _disp_v_pulse0 {
 146        /* _DISP_H_PULSE0/1_CONTROL_0 */
 147        uint v_pulse_ctrl;
 148        /* _DISP_H_PULSE0/1_POSITION_A/B/C_0 */
 149        uint v_pulse_pos[V_PULSE0_POSITION_COUNT];
 150};
 151
 152struct _disp_v_pulse2 {
 153        /* _DISP_H_PULSE2/3_CONTROL_0 */
 154        uint v_pulse_ctrl;
 155        /* _DISP_H_PULSE2/3_POSITION_A_0 */
 156        uint v_pulse_pos_a;
 157};
 158
 159enum dc_disp_h_pulse_reg {
 160        H_PULSE0,
 161        H_PULSE1,
 162        H_PULSE2,
 163        H_PULSE_COUNT,
 164};
 165
 166enum dc_disp_pp_select {
 167        PP_SELECT_A,
 168        PP_SELECT_B,
 169        PP_SELECT_C,
 170        PP_SELECT_D,
 171        PP_SELECT_COUNT,
 172};
 173
 174/* DISP register 0x400 ~ 0x4c1 */
 175struct dc_disp_reg {
 176        /* Address 0x400 ~ 0x40a */
 177        uint disp_signal_opt0;          /* _DISP_DISP_SIGNAL_OPTIONS0_0 */
 178        uint disp_signal_opt1;          /* _DISP_DISP_SIGNAL_OPTIONS1_0 */
 179        uint disp_win_opt;              /* _DISP_DISP_WIN_OPTIONS_0 */
 180        uint mem_high_pri;              /* _DISP_MEM_HIGH_PRIORITY_0 */
 181        uint mem_high_pri_timer;        /* _DISP_MEM_HIGH_PRIORITY_TIMER_0 */
 182        uint disp_timing_opt;           /* _DISP_DISP_TIMING_OPTIONS_0 */
 183        uint ref_to_sync;               /* _DISP_REF_TO_SYNC_0 */
 184        uint sync_width;                /* _DISP_SYNC_WIDTH_0 */
 185        uint back_porch;                /* _DISP_BACK_PORCH_0 */
 186        uint disp_active;               /* _DISP_DISP_ACTIVE_0 */
 187        uint front_porch;               /* _DISP_FRONT_PORCH_0 */
 188
 189        /* Address 0x40b ~ 0x419: _DISP_H_PULSE0/1/2_  */
 190        struct _disp_h_pulse h_pulse[H_PULSE_COUNT];
 191
 192        /* Address 0x41a ~ 0x421 */
 193        struct _disp_v_pulse0 v_pulse0; /* _DISP_V_PULSE0_ */
 194        struct _disp_v_pulse0 v_pulse1; /* _DISP_V_PULSE1_ */
 195
 196        /* Address 0x422 ~ 0x425 */
 197        struct _disp_v_pulse2 v_pulse3; /* _DISP_V_PULSE2_ */
 198        struct _disp_v_pulse2 v_pulse4; /* _DISP_V_PULSE3_ */
 199
 200        /* Address 0x426 ~ 0x429 */
 201        uint m0_ctrl;                   /* _DISP_M0_CONTROL_0 */
 202        uint m1_ctrl;                   /* _DISP_M1_CONTROL_0 */
 203        uint di_ctrl;                   /* _DISP_DI_CONTROL_0 */
 204        uint pp_ctrl;                   /* _DISP_PP_CONTROL_0 */
 205
 206        /* Address 0x42a ~ 0x42d: _DISP_PP_SELECT_A/B/C/D_0 */
 207        uint pp_select[PP_SELECT_COUNT];
 208
 209        /* Address 0x42e ~ 0x435 */
 210        uint disp_clk_ctrl;             /* _DISP_DISP_CLOCK_CONTROL_0 */
 211        uint disp_interface_ctrl;       /* _DISP_DISP_INTERFACE_CONTROL_0 */
 212        uint disp_color_ctrl;           /* _DISP_DISP_COLOR_CONTROL_0 */
 213        uint shift_clk_opt;             /* _DISP_SHIFT_CLOCK_OPTIONS_0 */
 214        uint data_enable_opt;           /* _DISP_DATA_ENABLE_OPTIONS_0 */
 215        uint serial_interface_opt;      /* _DISP_SERIAL_INTERFACE_OPTIONS_0 */
 216        uint lcd_spi_opt;               /* _DISP_LCD_SPI_OPTIONS_0 */
 217        uint border_color;              /* _DISP_BORDER_COLOR_0 */
 218
 219        /* Address 0x436 ~ 0x439 */
 220        uint color_key0_lower;          /* _DISP_COLOR_KEY0_LOWER_0 */
 221        uint color_key0_upper;          /* _DISP_COLOR_KEY0_UPPER_0 */
 222        uint color_key1_lower;          /* _DISP_COLOR_KEY1_LOWER_0 */
 223        uint color_key1_upper;          /* _DISP_COLOR_KEY1_UPPER_0 */
 224
 225        uint reserved0[2];              /* reserved_0[2] */
 226
 227        /* Address 0x43c ~ 0x442 */
 228        uint cursor_foreground;         /* _DISP_CURSOR_FOREGROUND_0 */
 229        uint cursor_background;         /* _DISP_CURSOR_BACKGROUND_0 */
 230        uint cursor_start_addr;         /* _DISP_CURSOR_START_ADDR_0 */
 231        uint cursor_start_addr_ns;      /* _DISP_CURSOR_START_ADDR_NS_0 */
 232        uint cursor_pos;                /* _DISP_CURSOR_POSITION_0 */
 233        uint cursor_pos_ns;             /* _DISP_CURSOR_POSITION_NS_0 */
 234        uint seq_ctrl;                  /* _DISP_INIT_SEQ_CONTROL_0 */
 235
 236        /* Address 0x443 ~ 0x446 */
 237        uint spi_init_seq_data_a;       /* _DISP_SPI_INIT_SEQ_DATA_A_0 */
 238        uint spi_init_seq_data_b;       /* _DISP_SPI_INIT_SEQ_DATA_B_0 */
 239        uint spi_init_seq_data_c;       /* _DISP_SPI_INIT_SEQ_DATA_C_0 */
 240        uint spi_init_seq_data_d;       /* _DISP_SPI_INIT_SEQ_DATA_D_0 */
 241
 242        uint reserved1[0x39];           /* reserved1[0x39], */
 243
 244        /* Address 0x480 ~ 0x484 */
 245        uint dc_mccif_fifoctrl;         /* _DISP_DC_MCCIF_FIFOCTRL_0 */
 246        uint mccif_disp0a_hyst;         /* _DISP_MCCIF_DISPLAY0A_HYST_0 */
 247        uint mccif_disp0b_hyst;         /* _DISP_MCCIF_DISPLAY0B_HYST_0 */
 248        uint mccif_disp0c_hyst;         /* _DISP_MCCIF_DISPLAY0C_HYST_0 */
 249        uint mccif_disp1b_hyst;         /* _DISP_MCCIF_DISPLAY1B_HYST_0 */
 250
 251        uint reserved2[0x3b];           /* reserved2[0x3b] */
 252
 253        /* Address 0x4c0 ~ 0x4c1 */
 254        uint dac_crt_ctrl;              /* _DISP_DAC_CRT_CTRL_0 */
 255        uint disp_misc_ctrl;            /* _DISP_DISP_MISC_CONTROL_0 */
 256
 257        u32 rsvd_4c2[34];               /* 4c2 - 4e3 */
 258
 259        /* Address 0x4e4 */
 260        u32 blend_background_color;     /* _DISP_BLEND_BACKGROUND_COLOR_0 */
 261};
 262
 263enum dc_winc_filter_p {
 264        WINC_FILTER_COUNT       = 0x10,
 265};
 266
 267/* Window A/B/C register 0x500 ~ 0x628 */
 268struct dc_winc_reg {
 269
 270        /* Address 0x500 */
 271        uint color_palette;             /* _WINC_COLOR_PALETTE_0 */
 272
 273        uint reserved0[0xff];           /* reserved_0[0xff] */
 274
 275        /* Address 0x600 */
 276        uint palette_color_ext;         /* _WINC_PALETTE_COLOR_EXT_0 */
 277
 278        /* _WINC_H_FILTER_P00~0F_0 */
 279        /* Address 0x601 ~ 0x610 */
 280        uint h_filter_p[WINC_FILTER_COUNT];
 281
 282        /* Address 0x611 ~ 0x618 */
 283        uint csc_yof;                   /* _WINC_CSC_YOF_0 */
 284        uint csc_kyrgb;                 /* _WINC_CSC_KYRGB_0 */
 285        uint csc_kur;                   /* _WINC_CSC_KUR_0 */
 286        uint csc_kvr;                   /* _WINC_CSC_KVR_0 */
 287        uint csc_kug;                   /* _WINC_CSC_KUG_0 */
 288        uint csc_kvg;                   /* _WINC_CSC_KVG_0 */
 289        uint csc_kub;                   /* _WINC_CSC_KUB_0 */
 290        uint csc_kvb;                   /* _WINC_CSC_KVB_0 */
 291
 292        /* Address 0x619 ~ 0x628: _WINC_V_FILTER_P00~0F_0 */
 293        uint v_filter_p[WINC_FILTER_COUNT];
 294};
 295
 296/* WIN A/B/C Register 0x700 ~ 0x719*/
 297struct dc_win_reg {
 298        /* Address 0x700 ~ 0x719 */
 299        uint win_opt;                   /* _WIN_WIN_OPTIONS_0 */
 300        uint byte_swap;                 /* _WIN_BYTE_SWAP_0 */
 301        uint buffer_ctrl;               /* _WIN_BUFFER_CONTROL_0 */
 302        uint color_depth;               /* _WIN_COLOR_DEPTH_0 */
 303        uint pos;                       /* _WIN_POSITION_0 */
 304        uint size;                      /* _WIN_SIZE_0 */
 305        uint prescaled_size;            /* _WIN_PRESCALED_SIZE_0 */
 306        uint h_initial_dda;             /* _WIN_H_INITIAL_DDA_0 */
 307        uint v_initial_dda;             /* _WIN_V_INITIAL_DDA_0 */
 308        uint dda_increment;             /* _WIN_DDA_INCREMENT_0 */
 309        uint line_stride;               /* _WIN_LINE_STRIDE_0 */
 310        uint buf_stride;                /* _WIN_BUF_STRIDE_0 */
 311        uint uv_buf_stride;             /* _WIN_UV_BUF_STRIDE_0 */
 312        uint buffer_addr_mode;          /* _WIN_BUFFER_ADDR_MODE_0 */
 313        uint dv_ctrl;                   /* _WIN_DV_CONTROL_0 */
 314        uint blend_nokey;               /* _WIN_BLEND_NOKEY_0 */
 315        uint blend_1win;                /* _WIN_BLEND_1WIN_0 */
 316        uint blend_2win_x;              /* _WIN_BLEND_2WIN_X_0 */
 317        uint blend_2win_y;              /* _WIN_BLEND_2WIN_Y_0 */
 318        uint blend_3win_xy;             /* _WIN_BLEND_3WIN_XY_0 */
 319        uint hp_fetch_ctrl;             /* _WIN_HP_FETCH_CONTROL_0 */
 320        uint global_alpha;              /* _WIN_GLOBAL_ALPHA */
 321        uint blend_layer_ctrl;          /* _WINBUF_BLEND_LAYER_CONTROL_0 */
 322        uint blend_match_select;        /* _WINBUF_BLEND_MATCH_SELECT_0 */
 323        uint blend_nomatch_select;      /* _WINBUF_BLEND_NOMATCH_SELECT_0 */
 324        uint blend_alpha_1bit;          /* _WINBUF_BLEND_ALPHA_1BIT_0 */
 325};
 326
 327/* WINBUF A/B/C Register 0x800 ~ 0x80d */
 328struct dc_winbuf_reg {
 329        /* Address 0x800 ~ 0x80d */
 330        uint start_addr;                /* _WINBUF_START_ADDR_0 */
 331        uint start_addr_ns;             /* _WINBUF_START_ADDR_NS_0 */
 332        uint start_addr_u;              /* _WINBUF_START_ADDR_U_0 */
 333        uint start_addr_u_ns;           /* _WINBUF_START_ADDR_U_NS_0 */
 334        uint start_addr_v;              /* _WINBUF_START_ADDR_V_0 */
 335        uint start_addr_v_ns;           /* _WINBUF_START_ADDR_V_NS_0 */
 336        uint addr_h_offset;             /* _WINBUF_ADDR_H_OFFSET_0 */
 337        uint addr_h_offset_ns;          /* _WINBUF_ADDR_H_OFFSET_NS_0 */
 338        uint addr_v_offset;             /* _WINBUF_ADDR_V_OFFSET_0 */
 339        uint addr_v_offset_ns;          /* _WINBUF_ADDR_V_OFFSET_NS_0 */
 340        uint uflow_status;              /* _WINBUF_UFLOW_STATUS_0 */
 341        uint buffer_surface_kind;       /* DC_WIN_BUFFER_SURFACE_KIND */
 342        uint rsvd_80c;
 343        uint start_addr_hi;             /* DC_WINBUF_START_ADDR_HI_0 */
 344};
 345
 346/* Display Controller (DC_) regs */
 347struct dc_ctlr {
 348        struct dc_cmd_reg cmd;          /* CMD register 0x000 ~ 0x43 */
 349        uint reserved0[0x2bc];
 350
 351        struct dc_com_reg com;          /* COM register 0x300 ~ 0x329 */
 352        uint reserved1[0xd6];
 353
 354        struct dc_disp_reg disp;        /* DISP register 0x400 ~ 0x4e4 */
 355        uint reserved2[0x1b];
 356
 357        struct dc_winc_reg winc;        /* Window A/B/C 0x500 ~ 0x628 */
 358        uint reserved3[0xd7];
 359
 360        struct dc_win_reg win;          /* WIN A/B/C 0x700 ~ 0x719*/
 361        uint reserved4[0xe6];
 362
 363        struct dc_winbuf_reg winbuf;    /* WINBUF A/B/C 0x800 ~ 0x80d */
 364};
 365
 366/* DC_CMD_DISPLAY_COMMAND 0x032 */
 367#define CTRL_MODE_SHIFT         5
 368#define CTRL_MODE_MASK          (0x3 << CTRL_MODE_SHIFT)
 369enum {
 370        CTRL_MODE_STOP,
 371        CTRL_MODE_C_DISPLAY,
 372        CTRL_MODE_NC_DISPLAY,
 373};
 374
 375/* _WIN_COLOR_DEPTH_0 */
 376enum win_color_depth_id {
 377        COLOR_DEPTH_P1,
 378        COLOR_DEPTH_P2,
 379        COLOR_DEPTH_P4,
 380        COLOR_DEPTH_P8,
 381        COLOR_DEPTH_B4G4R4A4,
 382        COLOR_DEPTH_B5G5R5A,
 383        COLOR_DEPTH_B5G6R5,
 384        COLOR_DEPTH_AB5G5R5,
 385        COLOR_DEPTH_B8G8R8A8 = 12,
 386        COLOR_DEPTH_R8G8B8A8,
 387        COLOR_DEPTH_B6x2G6x2R6x2A8,
 388        COLOR_DEPTH_R6x2G6x2B6x2A8,
 389        COLOR_DEPTH_YCbCr422,
 390        COLOR_DEPTH_YUV422,
 391        COLOR_DEPTH_YCbCr420P,
 392        COLOR_DEPTH_YUV420P,
 393        COLOR_DEPTH_YCbCr422P,
 394        COLOR_DEPTH_YUV422P,
 395        COLOR_DEPTH_YCbCr422R,
 396        COLOR_DEPTH_YUV422R,
 397        COLOR_DEPTH_YCbCr422RA,
 398        COLOR_DEPTH_YUV422RA,
 399};
 400
 401/* DC_CMD_DISPLAY_POWER_CONTROL 0x036 */
 402#define PW0_ENABLE              BIT(0)
 403#define PW1_ENABLE              BIT(2)
 404#define PW2_ENABLE              BIT(4)
 405#define PW3_ENABLE              BIT(6)
 406#define PW4_ENABLE              BIT(8)
 407#define PM0_ENABLE              BIT(16)
 408#define PM1_ENABLE              BIT(18)
 409#define SPI_ENABLE              BIT(24)
 410#define HSPI_ENABLE             BIT(25)
 411
 412/* DC_CMD_STATE_ACCESS 0x040 */
 413#define  READ_MUX_ASSEMBLY      (0 << 0)
 414#define  READ_MUX_ACTIVE        (1 << 0)
 415#define  WRITE_MUX_ASSEMBLY     (0 << 2)
 416#define  WRITE_MUX_ACTIVE       (1 << 2)
 417
 418/* DC_CMD_STATE_CONTROL 0x041 */
 419#define GENERAL_ACT_REQ         BIT(0)
 420#define WIN_A_ACT_REQ           BIT(1)
 421#define WIN_B_ACT_REQ           BIT(2)
 422#define WIN_C_ACT_REQ           BIT(3)
 423#define WIN_D_ACT_REQ           BIT(4)
 424#define WIN_H_ACT_REQ           BIT(5)
 425#define CURSOR_ACT_REQ          BIT(7)
 426#define GENERAL_UPDATE          BIT(8)
 427#define WIN_A_UPDATE            BIT(9)
 428#define WIN_B_UPDATE            BIT(10)
 429#define WIN_C_UPDATE            BIT(11)
 430#define WIN_D_UPDATE            BIT(12)
 431#define WIN_H_UPDATE            BIT(13)
 432#define CURSOR_UPDATE           BIT(15)
 433#define NC_HOST_TRIG            BIT(24)
 434
 435/* DC_CMD_DISPLAY_WINDOW_HEADER 0x042 */
 436#define WINDOW_A_SELECT         BIT(4)
 437#define WINDOW_B_SELECT         BIT(5)
 438#define WINDOW_C_SELECT         BIT(6)
 439#define WINDOW_D_SELECT         BIT(7)
 440#define WINDOW_H_SELECT         BIT(8)
 441
 442/* DC_DISP_DISP_WIN_OPTIONS 0x402 */
 443#define CURSOR_ENABLE           BIT(16)
 444#define SOR_ENABLE              BIT(25)
 445#define TVO_ENABLE              BIT(28)
 446#define DSI_ENABLE              BIT(29)
 447#define HDMI_ENABLE             BIT(30)
 448
 449/* DC_DISP_DISP_TIMING_OPTIONS 0x405 */
 450#define VSYNC_H_POSITION(x)     ((x) & 0xfff)
 451
 452/* DC_DISP_DISP_CLOCK_CONTROL 0x42e */
 453#define SHIFT_CLK_DIVIDER_SHIFT 0
 454#define SHIFT_CLK_DIVIDER_MASK  (0xff << SHIFT_CLK_DIVIDER_SHIFT)
 455#define PIXEL_CLK_DIVIDER_SHIFT 8
 456#define PIXEL_CLK_DIVIDER_MSK   (0xf << PIXEL_CLK_DIVIDER_SHIFT)
 457enum {
 458        PIXEL_CLK_DIVIDER_PCD1,
 459        PIXEL_CLK_DIVIDER_PCD1H,
 460        PIXEL_CLK_DIVIDER_PCD2,
 461        PIXEL_CLK_DIVIDER_PCD3,
 462        PIXEL_CLK_DIVIDER_PCD4,
 463        PIXEL_CLK_DIVIDER_PCD6,
 464        PIXEL_CLK_DIVIDER_PCD8,
 465        PIXEL_CLK_DIVIDER_PCD9,
 466        PIXEL_CLK_DIVIDER_PCD12,
 467        PIXEL_CLK_DIVIDER_PCD16,
 468        PIXEL_CLK_DIVIDER_PCD18,
 469        PIXEL_CLK_DIVIDER_PCD24,
 470        PIXEL_CLK_DIVIDER_PCD13,
 471};
 472
 473/* DC_DISP_DISP_INTERFACE_CONTROL 0x42f */
 474#define DATA_FORMAT_SHIFT       0
 475#define DATA_FORMAT_MASK        (0xf << DATA_FORMAT_SHIFT)
 476enum {
 477        DATA_FORMAT_DF1P1C,
 478        DATA_FORMAT_DF1P2C24B,
 479        DATA_FORMAT_DF1P2C18B,
 480        DATA_FORMAT_DF1P2C16B,
 481        DATA_FORMAT_DF2S,
 482        DATA_FORMAT_DF3S,
 483        DATA_FORMAT_DFSPI,
 484        DATA_FORMAT_DF1P3C24B,
 485        DATA_FORMAT_DF1P3C18B,
 486};
 487#define DATA_ALIGNMENT_SHIFT    8
 488enum {
 489        DATA_ALIGNMENT_MSB,
 490        DATA_ALIGNMENT_LSB,
 491};
 492#define DATA_ORDER_SHIFT        9
 493enum {
 494        DATA_ORDER_RED_BLUE,
 495        DATA_ORDER_BLUE_RED,
 496};
 497
 498/* DC_DISP_DATA_ENABLE_OPTIONS 0x432 */
 499#define DE_SELECT_SHIFT         0
 500#define DE_SELECT_MASK          (0x3 << DE_SELECT_SHIFT)
 501#define DE_SELECT_ACTIVE_BLANK  0x0
 502#define DE_SELECT_ACTIVE        0x1
 503#define DE_SELECT_ACTIVE_IS     0x2
 504#define DE_CONTROL_SHIFT        2
 505#define DE_CONTROL_MASK         (0x7 << DE_CONTROL_SHIFT)
 506enum {
 507        DE_CONTROL_ONECLK,
 508        DE_CONTROL_NORMAL,
 509        DE_CONTROL_EARLY_EXT,
 510        DE_CONTROL_EARLY,
 511        DE_CONTROL_ACTIVE_BLANK,
 512};
 513
 514/* DC_WIN_WIN_OPTIONS 0x700 */
 515#define H_DIRECTION             BIT(0)
 516enum {
 517        H_DIRECTION_INCREMENT,
 518        H_DIRECTION_DECREMENT,
 519};
 520#define V_DIRECTION             BIT(2)
 521enum {
 522        V_DIRECTION_INCREMENT,
 523        V_DIRECTION_DECREMENT,
 524};
 525#define COLOR_EXPAND            BIT(6)
 526#define CP_ENABLE               BIT(16)
 527#define DV_ENABLE               BIT(20)
 528#define WIN_ENABLE              BIT(30)
 529
 530/* DC_WIN_BYTE_SWAP 0x701 */
 531#define BYTE_SWAP_SHIFT         0
 532#define BYTE_SWAP_MASK          (3 << BYTE_SWAP_SHIFT)
 533enum {
 534        BYTE_SWAP_NOSWAP,
 535        BYTE_SWAP_SWAP2,
 536        BYTE_SWAP_SWAP4,
 537        BYTE_SWAP_SWAP4HW
 538};
 539
 540/* DC_WIN_POSITION 0x704 */
 541#define H_POSITION_SHIFT        0
 542#define H_POSITION_MASK         (0x1FFF << H_POSITION_SHIFT)
 543#define V_POSITION_SHIFT        16
 544#define V_POSITION_MASK         (0x1FFF << V_POSITION_SHIFT)
 545
 546/* DC_WIN_SIZE 0x705 */
 547#define H_SIZE_SHIFT            0
 548#define H_SIZE_MASK             (0x1FFF << H_SIZE_SHIFT)
 549#define V_SIZE_SHIFT            16
 550#define V_SIZE_MASK             (0x1FFF << V_SIZE_SHIFT)
 551
 552/* DC_WIN_PRESCALED_SIZE 0x706 */
 553#define H_PRESCALED_SIZE_SHIFT  0
 554#define H_PRESCALED_SIZE_MASK   (0x7FFF << H_PRESCALED_SIZE)
 555#define V_PRESCALED_SIZE_SHIFT  16
 556#define V_PRESCALED_SIZE_MASK   (0x1FFF << V_PRESCALED_SIZE)
 557
 558/* DC_WIN_DDA_INCREMENT 0x709 */
 559#define H_DDA_INC_SHIFT         0
 560#define H_DDA_INC_MASK          (0xFFFF << H_DDA_INC_SHIFT)
 561#define V_DDA_INC_SHIFT         16
 562#define V_DDA_INC_MASK          (0xFFFF << V_DDA_INC_SHIFT)
 563
 564#define DC_POLL_TIMEOUT_MS              50
 565#define DC_N_WINDOWS                    5
 566#define DC_REG_SAVE_SPACE               (DC_N_WINDOWS + 5)
 567
 568#endif /* __ASM_ARCH_TEGRA_DC_H */
 569