1/* SPDX-License-Identifier: GPL-2.0+ */ 2/* 3 * Freescale i.MX28 BCH Register Definitions 4 * 5 * Copyright (C) 2011 Marek Vasut <marek.vasut@gmail.com> 6 * on behalf of DENX Software Engineering GmbH 7 * 8 * Based on code from LTIB: 9 * Copyright 2008-2010 Freescale Semiconductor, Inc. All Rights Reserved. 10 */ 11 12#ifndef __MX28_REGS_BCH_H__ 13#define __MX28_REGS_BCH_H__ 14 15#include <asm/mach-imx/regs-common.h> 16 17#ifndef __ASSEMBLY__ 18struct mxs_bch_regs { 19 mxs_reg_32(hw_bch_ctrl) 20 mxs_reg_32(hw_bch_status0) 21 mxs_reg_32(hw_bch_mode) 22 mxs_reg_32(hw_bch_encodeptr) 23 mxs_reg_32(hw_bch_dataptr) 24 mxs_reg_32(hw_bch_metaptr) 25 26 uint32_t reserved[4]; 27 28 mxs_reg_32(hw_bch_layoutselect) 29 mxs_reg_32(hw_bch_flash0layout0) 30 mxs_reg_32(hw_bch_flash0layout1) 31 mxs_reg_32(hw_bch_flash1layout0) 32 mxs_reg_32(hw_bch_flash1layout1) 33 mxs_reg_32(hw_bch_flash2layout0) 34 mxs_reg_32(hw_bch_flash2layout1) 35 mxs_reg_32(hw_bch_flash3layout0) 36 mxs_reg_32(hw_bch_flash3layout1) 37 mxs_reg_32(hw_bch_dbgkesread) 38 mxs_reg_32(hw_bch_dbgcsferead) 39 mxs_reg_32(hw_bch_dbgsyndegread) 40 mxs_reg_32(hw_bch_dbgahbmread) 41 mxs_reg_32(hw_bch_blockname) 42 mxs_reg_32(hw_bch_version) 43}; 44#endif 45 46#define BCH_CTRL_SFTRST (1 << 31) 47#define BCH_CTRL_CLKGATE (1 << 30) 48#define BCH_CTRL_DEBUGSYNDROME (1 << 22) 49#define BCH_CTRL_M2M_LAYOUT_MASK (0x3 << 18) 50#define BCH_CTRL_M2M_LAYOUT_OFFSET 18 51#define BCH_CTRL_M2M_ENCODE (1 << 17) 52#define BCH_CTRL_M2M_ENABLE (1 << 16) 53#define BCH_CTRL_DEBUG_STALL_IRQ_EN (1 << 10) 54#define BCH_CTRL_COMPLETE_IRQ_EN (1 << 8) 55#define BCH_CTRL_BM_ERROR_IRQ (1 << 3) 56#define BCH_CTRL_DEBUG_STALL_IRQ (1 << 2) 57#define BCH_CTRL_COMPLETE_IRQ (1 << 0) 58 59#define BCH_STATUS0_HANDLE_MASK (0xfff << 20) 60#define BCH_STATUS0_HANDLE_OFFSET 20 61#define BCH_STATUS0_COMPLETED_CE_MASK (0xf << 16) 62#define BCH_STATUS0_COMPLETED_CE_OFFSET 16 63#define BCH_STATUS0_STATUS_BLK0_MASK (0xff << 8) 64#define BCH_STATUS0_STATUS_BLK0_OFFSET 8 65#define BCH_STATUS0_STATUS_BLK0_ZERO (0x00 << 8) 66#define BCH_STATUS0_STATUS_BLK0_ERROR1 (0x01 << 8) 67#define BCH_STATUS0_STATUS_BLK0_ERROR2 (0x02 << 8) 68#define BCH_STATUS0_STATUS_BLK0_ERROR3 (0x03 << 8) 69#define BCH_STATUS0_STATUS_BLK0_ERROR4 (0x04 << 8) 70#define BCH_STATUS0_STATUS_BLK0_UNCORRECTABLE (0xfe << 8) 71#define BCH_STATUS0_STATUS_BLK0_ERASED (0xff << 8) 72#define BCH_STATUS0_ALLONES (1 << 4) 73#define BCH_STATUS0_CORRECTED (1 << 3) 74#define BCH_STATUS0_UNCORRECTABLE (1 << 2) 75 76#define BCH_MODE_ERASE_THRESHOLD_MASK 0xff 77#define BCH_MODE_ERASE_THRESHOLD_OFFSET 0 78 79#define BCH_ENCODEPTR_ADDR_MASK 0xffffffff 80#define BCH_ENCODEPTR_ADDR_OFFSET 0 81 82#define BCH_DATAPTR_ADDR_MASK 0xffffffff 83#define BCH_DATAPTR_ADDR_OFFSET 0 84 85#define BCH_METAPTR_ADDR_MASK 0xffffffff 86#define BCH_METAPTR_ADDR_OFFSET 0 87 88#define BCH_LAYOUTSELECT_CS15_SELECT_MASK (0x3 << 30) 89#define BCH_LAYOUTSELECT_CS15_SELECT_OFFSET 30 90#define BCH_LAYOUTSELECT_CS14_SELECT_MASK (0x3 << 28) 91#define BCH_LAYOUTSELECT_CS14_SELECT_OFFSET 28 92#define BCH_LAYOUTSELECT_CS13_SELECT_MASK (0x3 << 26) 93#define BCH_LAYOUTSELECT_CS13_SELECT_OFFSET 26 94#define BCH_LAYOUTSELECT_CS12_SELECT_MASK (0x3 << 24) 95#define BCH_LAYOUTSELECT_CS12_SELECT_OFFSET 24 96#define BCH_LAYOUTSELECT_CS11_SELECT_MASK (0x3 << 22) 97#define BCH_LAYOUTSELECT_CS11_SELECT_OFFSET 22 98#define BCH_LAYOUTSELECT_CS10_SELECT_MASK (0x3 << 20) 99#define BCH_LAYOUTSELECT_CS10_SELECT_OFFSET 20 100#define BCH_LAYOUTSELECT_CS9_SELECT_MASK (0x3 << 18) 101#define BCH_LAYOUTSELECT_CS9_SELECT_OFFSET 18 102#define BCH_LAYOUTSELECT_CS8_SELECT_MASK (0x3 << 16) 103#define BCH_LAYOUTSELECT_CS8_SELECT_OFFSET 16 104#define BCH_LAYOUTSELECT_CS7_SELECT_MASK (0x3 << 14) 105#define BCH_LAYOUTSELECT_CS7_SELECT_OFFSET 14 106#define BCH_LAYOUTSELECT_CS6_SELECT_MASK (0x3 << 12) 107#define BCH_LAYOUTSELECT_CS6_SELECT_OFFSET 12 108#define BCH_LAYOUTSELECT_CS5_SELECT_MASK (0x3 << 10) 109#define BCH_LAYOUTSELECT_CS5_SELECT_OFFSET 10 110#define BCH_LAYOUTSELECT_CS4_SELECT_MASK (0x3 << 8) 111#define BCH_LAYOUTSELECT_CS4_SELECT_OFFSET 8 112#define BCH_LAYOUTSELECT_CS3_SELECT_MASK (0x3 << 6) 113#define BCH_LAYOUTSELECT_CS3_SELECT_OFFSET 6 114#define BCH_LAYOUTSELECT_CS2_SELECT_MASK (0x3 << 4) 115#define BCH_LAYOUTSELECT_CS2_SELECT_OFFSET 4 116#define BCH_LAYOUTSELECT_CS1_SELECT_MASK (0x3 << 2) 117#define BCH_LAYOUTSELECT_CS1_SELECT_OFFSET 2 118#define BCH_LAYOUTSELECT_CS0_SELECT_MASK (0x3 << 0) 119#define BCH_LAYOUTSELECT_CS0_SELECT_OFFSET 0 120 121#define BCH_FLASHLAYOUT0_NBLOCKS_MASK (0xff << 24) 122#define BCH_FLASHLAYOUT0_NBLOCKS_OFFSET 24 123#define BCH_FLASHLAYOUT0_META_SIZE_MASK (0xff << 16) 124#define BCH_FLASHLAYOUT0_META_SIZE_OFFSET 16 125#if (defined(CONFIG_MX6) || defined(CONFIG_MX7)) 126#define BCH_FLASHLAYOUT0_ECC0_MASK (0x1f << 11) 127#define BCH_FLASHLAYOUT0_ECC0_OFFSET 11 128#else 129#define BCH_FLASHLAYOUT0_ECC0_MASK (0xf << 12) 130#define BCH_FLASHLAYOUT0_ECC0_OFFSET 12 131#endif 132#define BCH_FLASHLAYOUT0_ECC0_NONE (0x0 << 12) 133#define BCH_FLASHLAYOUT0_ECC0_ECC2 (0x1 << 12) 134#define BCH_FLASHLAYOUT0_ECC0_ECC4 (0x2 << 12) 135#define BCH_FLASHLAYOUT0_ECC0_ECC6 (0x3 << 12) 136#define BCH_FLASHLAYOUT0_ECC0_ECC8 (0x4 << 12) 137#define BCH_FLASHLAYOUT0_ECC0_ECC10 (0x5 << 12) 138#define BCH_FLASHLAYOUT0_ECC0_ECC12 (0x6 << 12) 139#define BCH_FLASHLAYOUT0_ECC0_ECC14 (0x7 << 12) 140#define BCH_FLASHLAYOUT0_ECC0_ECC16 (0x8 << 12) 141#define BCH_FLASHLAYOUT0_ECC0_ECC18 (0x9 << 12) 142#define BCH_FLASHLAYOUT0_ECC0_ECC20 (0xa << 12) 143#define BCH_FLASHLAYOUT0_ECC0_ECC22 (0xb << 12) 144#define BCH_FLASHLAYOUT0_ECC0_ECC24 (0xc << 12) 145#define BCH_FLASHLAYOUT0_ECC0_ECC26 (0xd << 12) 146#define BCH_FLASHLAYOUT0_ECC0_ECC28 (0xe << 12) 147#define BCH_FLASHLAYOUT0_ECC0_ECC30 (0xf << 12) 148#define BCH_FLASHLAYOUT0_ECC0_ECC32 (0x10 << 12) 149#define BCH_FLASHLAYOUT0_GF13_0_GF14_1 (1 << 10) 150#define BCH_FLASHLAYOUT0_GF13_0_GF14_1_OFFSET 10 151#define BCH_FLASHLAYOUT0_DATA0_SIZE_MASK 0xfff 152#define BCH_FLASHLAYOUT0_DATA0_SIZE_OFFSET 0 153 154#define BCH_FLASHLAYOUT1_PAGE_SIZE_MASK (0xffff << 16) 155#define BCH_FLASHLAYOUT1_PAGE_SIZE_OFFSET 16 156#if (defined(CONFIG_MX6) || defined(CONFIG_MX7)) 157#define BCH_FLASHLAYOUT1_ECCN_MASK (0x1f << 11) 158#define BCH_FLASHLAYOUT1_ECCN_OFFSET 11 159#else 160#define BCH_FLASHLAYOUT1_ECCN_MASK (0xf << 12) 161#define BCH_FLASHLAYOUT1_ECCN_OFFSET 12 162#endif 163#define BCH_FLASHLAYOUT1_ECCN_NONE (0x0 << 12) 164#define BCH_FLASHLAYOUT1_ECCN_ECC2 (0x1 << 12) 165#define BCH_FLASHLAYOUT1_ECCN_ECC4 (0x2 << 12) 166#define BCH_FLASHLAYOUT1_ECCN_ECC6 (0x3 << 12) 167#define BCH_FLASHLAYOUT1_ECCN_ECC8 (0x4 << 12) 168#define BCH_FLASHLAYOUT1_ECCN_ECC10 (0x5 << 12) 169#define BCH_FLASHLAYOUT1_ECCN_ECC12 (0x6 << 12) 170#define BCH_FLASHLAYOUT1_ECCN_ECC14 (0x7 << 12) 171#define BCH_FLASHLAYOUT1_ECCN_ECC16 (0x8 << 12) 172#define BCH_FLASHLAYOUT1_ECCN_ECC18 (0x9 << 12) 173#define BCH_FLASHLAYOUT1_ECCN_ECC20 (0xa << 12) 174#define BCH_FLASHLAYOUT1_ECCN_ECC22 (0xb << 12) 175#define BCH_FLASHLAYOUT1_ECCN_ECC24 (0xc << 12) 176#define BCH_FLASHLAYOUT1_ECCN_ECC26 (0xd << 12) 177#define BCH_FLASHLAYOUT1_ECCN_ECC28 (0xe << 12) 178#define BCH_FLASHLAYOUT1_ECCN_ECC30 (0xf << 12) 179#define BCH_FLASHLAYOUT1_ECCN_ECC32 (0x10 << 12) 180#define BCH_FLASHLAYOUT1_GF13_0_GF14_1 (1 << 10) 181#define BCH_FLASHLAYOUT1_GF13_0_GF14_1_OFFSET 10 182#define BCH_FLASHLAYOUT1_DATAN_SIZE_MASK 0xfff 183#define BCH_FLASHLAYOUT1_DATAN_SIZE_OFFSET 0 184 185#define BCH_DEBUG0_RSVD1_MASK (0x1f << 27) 186#define BCH_DEBUG0_RSVD1_OFFSET 27 187#define BCH_DEBUG0_ROM_BIST_ENABLE (1 << 26) 188#define BCH_DEBUG0_ROM_BIST_COMPLETE (1 << 25) 189#define BCH_DEBUG0_KES_DEBUG_SYNDROME_SYMBOL_MASK (0x1ff << 16) 190#define BCH_DEBUG0_KES_DEBUG_SYNDROME_SYMBOL_OFFSET 16 191#define BCH_DEBUG0_KES_DEBUG_SYNDROME_SYMBOL_NORMAL (0x0 << 16) 192#define BCH_DEBUG0_KES_DEBUG_SYNDROME_SYMBOL_TEST_MODE (0x1 << 16) 193#define BCH_DEBUG0_KES_DEBUG_SHIFT_SYND (1 << 15) 194#define BCH_DEBUG0_KES_DEBUG_PAYLOAD_FLAG (1 << 14) 195#define BCH_DEBUG0_KES_DEBUG_MODE4K (1 << 13) 196#define BCH_DEBUG0_KES_DEBUG_KICK (1 << 12) 197#define BCH_DEBUG0_KES_STANDALONE (1 << 11) 198#define BCH_DEBUG0_KES_DEBUG_STEP (1 << 10) 199#define BCH_DEBUG0_KES_DEBUG_STALL (1 << 9) 200#define BCH_DEBUG0_BM_KES_TEST_BYPASS (1 << 8) 201#define BCH_DEBUG0_RSVD0_MASK (0x3 << 6) 202#define BCH_DEBUG0_RSVD0_OFFSET 6 203#define BCH_DEBUG0_DEBUG_REG_SELECT_MASK 0x3f 204#define BCH_DEBUG0_DEBUG_REG_SELECT_OFFSET 0 205 206#define BCH_DBGKESREAD_VALUES_MASK 0xffffffff 207#define BCH_DBGKESREAD_VALUES_OFFSET 0 208 209#define BCH_DBGCSFEREAD_VALUES_MASK 0xffffffff 210#define BCH_DBGCSFEREAD_VALUES_OFFSET 0 211 212#define BCH_DBGSYNDGENREAD_VALUES_MASK 0xffffffff 213#define BCH_DBGSYNDGENREAD_VALUES_OFFSET 0 214 215#define BCH_DBGAHBMREAD_VALUES_MASK 0xffffffff 216#define BCH_DBGAHBMREAD_VALUES_OFFSET 0 217 218#define BCH_BLOCKNAME_NAME_MASK 0xffffffff 219#define BCH_BLOCKNAME_NAME_OFFSET 0 220 221#define BCH_VERSION_MAJOR_MASK (0xff << 24) 222#define BCH_VERSION_MAJOR_OFFSET 24 223#define BCH_VERSION_MINOR_MASK (0xff << 16) 224#define BCH_VERSION_MINOR_OFFSET 16 225#define BCH_VERSION_STEP_MASK 0xffff 226#define BCH_VERSION_STEP_OFFSET 0 227 228#endif /* __MX28_REGS_BCH_H__ */ 229