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8#include <common.h>
9#include <asm/arch/imx-regs.h>
10#include <asm/io.h>
11#include <asm/arch/clock.h>
12#include <asm/arch/sys_proto.h>
13#include <asm/mach-imx/hab.h>
14#include <asm/mach-imx/boot_mode.h>
15#include <asm/mach-imx/syscounter.h>
16#include <asm/armv8/mmu.h>
17#include <errno.h>
18#include <fdt_support.h>
19#include <fsl_wdog.h>
20#include <imx_sip.h>
21
22DECLARE_GLOBAL_DATA_PTR;
23
24#if defined(CONFIG_SECURE_BOOT)
25struct imx_sec_config_fuse_t const imx_sec_config_fuse = {
26 .bank = 1,
27 .word = 3,
28};
29#endif
30
31int timer_init(void)
32{
33#ifdef CONFIG_SPL_BUILD
34 struct sctr_regs *sctr = (struct sctr_regs *)SYSCNT_CTRL_BASE_ADDR;
35 unsigned long freq = readl(&sctr->cntfid0);
36
37
38 asm volatile("msr cntfrq_el0, %0" : : "r" (freq) : "memory");
39
40 clrsetbits_le32(&sctr->cntcr, SC_CNTCR_FREQ0 | SC_CNTCR_FREQ1,
41 SC_CNTCR_FREQ0 | SC_CNTCR_ENABLE | SC_CNTCR_HDBG);
42#endif
43
44 gd->arch.tbl = 0;
45 gd->arch.tbu = 0;
46
47 return 0;
48}
49
50void enable_tzc380(void)
51{
52 struct iomuxc_gpr_base_regs *gpr =
53 (struct iomuxc_gpr_base_regs *)IOMUXC_GPR_BASE_ADDR;
54
55
56 setbits_le32(&gpr->gpr[10], GPR_TZASC_EN);
57 setbits_le32(&gpr->gpr[10], GPR_TZASC_EN_LOCK);
58}
59
60void set_wdog_reset(struct wdog_regs *wdog)
61{
62
63
64
65
66
67
68
69 setbits_le16(&wdog->wcr, WDOG_WDT_MASK | WDOG_WDZST_MASK);
70}
71
72static struct mm_region imx8m_mem_map[] = {
73 {
74
75 .virt = 0x0UL,
76 .phys = 0x0UL,
77 .size = 0x100000UL,
78 .attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL) |
79 PTE_BLOCK_OUTER_SHARE
80 }, {
81
82 .virt = 0x900000UL,
83 .phys = 0x900000UL,
84 .size = 0x200000UL,
85 .attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL) |
86 PTE_BLOCK_OUTER_SHARE
87 }, {
88
89 .virt = 0xB00000UL,
90 .phys = 0xB00000UL,
91 .size = 0x3f500000UL,
92 .attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
93 PTE_BLOCK_NON_SHARE |
94 PTE_BLOCK_PXN | PTE_BLOCK_UXN
95 }, {
96
97 .virt = 0x40000000UL,
98 .phys = 0x40000000UL,
99 .size = 0xC0000000UL,
100 .attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL) |
101 PTE_BLOCK_OUTER_SHARE
102 }, {
103
104 .virt = 0x100000000UL,
105 .phys = 0x100000000UL,
106 .size = 0x040000000UL,
107 .attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL) |
108 PTE_BLOCK_OUTER_SHARE
109 }, {
110
111 0,
112 }
113};
114
115struct mm_region *mem_map = imx8m_mem_map;
116
117u32 get_cpu_rev(void)
118{
119 struct anamix_pll *ana_pll = (struct anamix_pll *)ANATOP_BASE_ADDR;
120 u32 reg = readl(&ana_pll->digprog);
121 u32 type = (reg >> 16) & 0xff;
122 u32 rom_version;
123
124 reg &= 0xff;
125
126 if (reg == CHIP_REV_1_0) {
127
128
129
130
131 rom_version = readl((void __iomem *)ROM_VERSION_A0);
132 if (rom_version != CHIP_REV_1_0) {
133 rom_version = readl((void __iomem *)ROM_VERSION_B0);
134 if (rom_version >= CHIP_REV_2_0)
135 reg = CHIP_REV_2_0;
136 }
137 }
138
139 return (type << 12) | reg;
140}
141
142static void imx_set_wdog_powerdown(bool enable)
143{
144 struct wdog_regs *wdog1 = (struct wdog_regs *)WDOG1_BASE_ADDR;
145 struct wdog_regs *wdog2 = (struct wdog_regs *)WDOG2_BASE_ADDR;
146 struct wdog_regs *wdog3 = (struct wdog_regs *)WDOG3_BASE_ADDR;
147
148
149 writew(enable, &wdog1->wmcr);
150 writew(enable, &wdog2->wmcr);
151 writew(enable, &wdog3->wmcr);
152}
153
154int arch_cpu_init(void)
155{
156
157
158
159
160 timer_init();
161
162 if (IS_ENABLED(CONFIG_SPL_BUILD)) {
163 clock_init();
164 imx_set_wdog_powerdown(false);
165 }
166
167 return 0;
168}
169
170bool is_usb_boot(void)
171{
172 return get_boot_device() == USB_BOOT;
173}
174
175#ifdef CONFIG_OF_SYSTEM_SETUP
176int ft_system_setup(void *blob, bd_t *bd)
177{
178 int i = 0;
179 int rc;
180 int nodeoff;
181
182
183 if (is_soc_rev(CHIP_REV_1_0)) {
184 static const char * const nodes_path[] = {
185 "/cpus/cpu@0",
186 "/cpus/cpu@1",
187 "/cpus/cpu@2",
188 "/cpus/cpu@3",
189 };
190
191 for (i = 0; i < ARRAY_SIZE(nodes_path); i++) {
192 nodeoff = fdt_path_offset(blob, nodes_path[i]);
193 if (nodeoff < 0)
194 continue;
195
196 printf("Found %s node\n", nodes_path[i]);
197
198 rc = fdt_delprop(blob, nodeoff, "cpu-idle-states");
199 if (rc) {
200 printf("Unable to update property %s:%s, err=%s\n",
201 nodes_path[i], "status", fdt_strerror(rc));
202 return rc;
203 }
204
205 printf("Remove %s:%s\n", nodes_path[i],
206 "cpu-idle-states");
207 }
208 }
209
210 return 0;
211}
212#endif
213
214void reset_cpu(ulong addr)
215{
216 struct watchdog_regs *wdog = (struct watchdog_regs *)WDOG1_BASE_ADDR;
217
218
219 writew((WCR_WDE | WCR_SRS), &wdog->wcr);
220
221 while (1) {
222
223
224
225 }
226}
227