LXR uboot/arch/microblaze/cpu/cache.c

   1// SPDX-License-Identifier: GPL-2.0+
   2/*
   3 * (C) Copyright 2007 Michal Simek
   4 *
   5 * Michal SIMEK <monstr@monstr.eu>
   6 */
   7
   8#include <common.h>
   9#include <asm/asm.h>
  10
  11int dcache_status (void)
  12{
  13        int i = 0;
  14        int mask = 0x80;
  15        __asm__ __volatile__ ("mfs %0,rmsr"::"r" (i):"memory");
  16        /* i&=0x80 */
  17        __asm__ __volatile__ ("and %0,%0,%1"::"r" (i), "r" (mask):"memory");
  18        return i;
  19}
  20
  21int icache_status (void)
  22{
  23        int i = 0;
  24        int mask = 0x20;
  25        __asm__ __volatile__ ("mfs %0,rmsr"::"r" (i):"memory");
  26        /* i&=0x20 */
  27        __asm__ __volatile__ ("and %0,%0,%1"::"r" (i), "r" (mask):"memory");
  28        return i;
  29}
  30
  31void    icache_enable (void) {
  32        MSRSET(0x20);
  33}
  34
  35void    icache_disable(void) {
  36        /* we are not generate ICACHE size -> flush whole cache */
  37        flush_cache(0, 32768);
  38        MSRCLR(0x20);
  39}
  40
  41void    dcache_enable (void) {
  42        MSRSET(0x80);
  43}
  44
  45void    dcache_disable(void) {
  46#ifdef XILINX_USE_DCACHE
  47        flush_cache(0, XILINX_DCACHE_BYTE_SIZE);
  48#endif
  49        MSRCLR(0x80);
  50}
  51
  52void flush_cache (ulong addr, ulong size)
  53{
  54        int i;
  55        for (i = 0; i < size; i += 4)
  56                asm volatile (
  57#ifdef CONFIG_ICACHE
  58                                "wic    %0, r0;"
  59#endif
  60                                "nop;"
  61#ifdef CONFIG_DCACHE
  62                                "wdc.flush      %0, r0;"
  63#endif
  64                                "nop;"
  65                                :
  66                                : "r" (addr + i)
  67                                : "memory");
  68}
  69