1/* SPDX-License-Identifier: GPL-2.0+ */ 2/* 3 * Atheros AR71XX/AR724X/AR913X SoC register definitions 4 * 5 * Copyright (C) 2015-2016 Wills Wang <wills.wang@live.com> 6 * Copyright (C) 2010-2011 Jaiganesh Narayanan <jnarayanan@atheros.com> 7 * Copyright (C) 2008-2010 Gabor Juhos <juhosg@openwrt.org> 8 * Copyright (C) 2008 Imre Kaloz <kaloz@openwrt.org> 9 */ 10 11#ifndef __ASM_MACH_AR71XX_REGS_H 12#define __ASM_MACH_AR71XX_REGS_H 13 14#ifndef __ASSEMBLY__ 15#include <linux/bitops.h> 16#else 17#ifndef BIT 18#define BIT(nr) (1 << (nr)) 19#endif 20#endif 21 22#define AR71XX_APB_BASE 0x18000000 23#define AR71XX_GE0_BASE 0x19000000 24#define AR71XX_GE0_SIZE 0x10000 25#define AR71XX_GE1_BASE 0x1a000000 26#define AR71XX_GE1_SIZE 0x10000 27#define AR71XX_EHCI_BASE 0x1b000000 28#define AR71XX_EHCI_SIZE 0x1000 29#define AR71XX_OHCI_BASE 0x1c000000 30#define AR71XX_OHCI_SIZE 0x1000 31#define AR71XX_SPI_BASE 0x1f000000 32#define AR71XX_SPI_SIZE 0x01000000 33 34#define AR71XX_DDR_CTRL_BASE \ 35 (AR71XX_APB_BASE + 0x00000000) 36#define AR71XX_DDR_CTRL_SIZE 0x100 37#define AR71XX_UART_BASE \ 38 (AR71XX_APB_BASE + 0x00020000) 39#define AR71XX_UART_SIZE 0x100 40#define AR71XX_USB_CTRL_BASE \ 41 (AR71XX_APB_BASE + 0x00030000) 42#define AR71XX_USB_CTRL_SIZE 0x100 43#define AR71XX_GPIO_BASE \ 44 (AR71XX_APB_BASE + 0x00040000) 45#define AR71XX_GPIO_SIZE 0x100 46#define AR71XX_PLL_BASE \ 47 (AR71XX_APB_BASE + 0x00050000) 48#define AR71XX_PLL_SIZE 0x100 49#define AR71XX_RESET_BASE \ 50 (AR71XX_APB_BASE + 0x00060000) 51#define AR71XX_RESET_SIZE 0x100 52#define AR71XX_MII_BASE \ 53 (AR71XX_APB_BASE + 0x00070000) 54#define AR71XX_MII_SIZE 0x100 55 56#define AR71XX_PCI_MEM_BASE 0x10000000 57#define AR71XX_PCI_MEM_SIZE 0x07000000 58 59#define AR71XX_PCI_WIN0_OFFS 0x10000000 60#define AR71XX_PCI_WIN1_OFFS 0x11000000 61#define AR71XX_PCI_WIN2_OFFS 0x12000000 62#define AR71XX_PCI_WIN3_OFFS 0x13000000 63#define AR71XX_PCI_WIN4_OFFS 0x14000000 64#define AR71XX_PCI_WIN5_OFFS 0x15000000 65#define AR71XX_PCI_WIN6_OFFS 0x16000000 66#define AR71XX_PCI_WIN7_OFFS 0x07000000 67 68#define AR71XX_PCI_CFG_BASE \ 69 (AR71XX_PCI_MEM_BASE + AR71XX_PCI_WIN7_OFFS + 0x10000) 70#define AR71XX_PCI_CFG_SIZE 0x100 71 72#define AR7240_USB_CTRL_BASE \ 73 (AR71XX_APB_BASE + 0x00030000) 74#define AR7240_USB_CTRL_SIZE 0x100 75#define AR7240_OHCI_BASE 0x1b000000 76#define AR7240_OHCI_SIZE 0x1000 77 78#define AR724X_PCI_MEM_BASE 0x10000000 79#define AR724X_PCI_MEM_SIZE 0x04000000 80 81#define AR724X_PCI_CFG_BASE 0x14000000 82#define AR724X_PCI_CFG_SIZE 0x1000 83#define AR724X_PCI_CRP_BASE \ 84 (AR71XX_APB_BASE + 0x000c0000) 85#define AR724X_PCI_CRP_SIZE 0x1000 86#define AR724X_PCI_CTRL_BASE \ 87 (AR71XX_APB_BASE + 0x000f0000) 88#define AR724X_PCI_CTRL_SIZE 0x100 89 90#define AR724X_EHCI_BASE 0x1b000000 91#define AR724X_EHCI_SIZE 0x1000 92 93#define AR913X_EHCI_BASE 0x1b000000 94#define AR913X_EHCI_SIZE 0x1000 95#define AR913X_WMAC_BASE \ 96 (AR71XX_APB_BASE + 0x000C0000) 97#define AR913X_WMAC_SIZE 0x30000 98 99#define AR933X_UART_BASE \ 100 (AR71XX_APB_BASE + 0x00020000) 101#define AR933X_UART_SIZE 0x14 102#define AR933X_GMAC_BASE \ 103 (AR71XX_APB_BASE + 0x00070000) 104#define AR933X_GMAC_SIZE 0x04 105#define AR933X_WMAC_BASE \ 106 (AR71XX_APB_BASE + 0x00100000) 107#define AR933X_WMAC_SIZE 0x20000 108#define AR933X_RTC_BASE \ 109 (AR71XX_APB_BASE + 0x00107000) 110#define AR933X_RTC_SIZE 0x1000 111#define AR933X_EHCI_BASE 0x1b000000 112#define AR933X_EHCI_SIZE 0x1000 113#define AR933X_SRIF_BASE \ 114 (AR71XX_APB_BASE + 0x00116000) 115#define AR933X_SRIF_SIZE 0x1000 116 117#define AR934X_GMAC_BASE \ 118 (AR71XX_APB_BASE + 0x00070000) 119#define AR934X_GMAC_SIZE 0x14 120#define AR934X_WMAC_BASE \ 121 (AR71XX_APB_BASE + 0x00100000) 122#define AR934X_WMAC_SIZE 0x20000 123#define AR934X_EHCI_BASE 0x1b000000 124#define AR934X_EHCI_SIZE 0x200 125#define AR934X_NFC_BASE 0x1b000200 126#define AR934X_NFC_SIZE 0xb8 127#define AR934X_SRIF_BASE \ 128 (AR71XX_APB_BASE + 0x00116000) 129#define AR934X_SRIF_SIZE 0x1000 130 131#define QCA953X_GMAC_BASE \ 132 (AR71XX_APB_BASE + 0x00070000) 133#define QCA953X_GMAC_SIZE 0x14 134#define QCA953X_WMAC_BASE \ 135 (AR71XX_APB_BASE + 0x00100000) 136#define QCA953X_WMAC_SIZE 0x20000 137#define QCA953X_RTC_BASE \ 138 (AR71XX_APB_BASE + 0x00107000) 139#define QCA953X_RTC_SIZE 0x1000 140#define QCA953X_EHCI_BASE 0x1b000000 141#define QCA953X_EHCI_SIZE 0x200 142#define QCA953X_SRIF_BASE \ 143 (AR71XX_APB_BASE + 0x00116000) 144#define QCA953X_SRIF_SIZE 0x1000 145 146#define QCA953X_PCI_CFG_BASE0 0x14000000 147#define QCA953X_PCI_CTRL_BASE0 \ 148 (AR71XX_APB_BASE + 0x000f0000) 149#define QCA953X_PCI_CRP_BASE0 \ 150 (AR71XX_APB_BASE + 0x000c0000) 151#define QCA953X_PCI_MEM_BASE0 0x10000000 152#define QCA953X_PCI_MEM_SIZE 0x02000000 153 154#define QCA955X_PCI_MEM_BASE0 0x10000000 155#define QCA955X_PCI_MEM_BASE1 0x12000000 156#define QCA955X_PCI_MEM_SIZE 0x02000000 157#define QCA955X_PCI_CFG_BASE0 0x14000000 158#define QCA955X_PCI_CFG_BASE1 0x16000000 159#define QCA955X_PCI_CFG_SIZE 0x1000 160#define QCA955X_PCI_CRP_BASE0 \ 161 (AR71XX_APB_BASE + 0x000c0000) 162#define QCA955X_PCI_CRP_BASE1 \ 163 (AR71XX_APB_BASE + 0x00250000) 164#define QCA955X_PCI_CRP_SIZE 0x1000 165#define QCA955X_PCI_CTRL_BASE0 \ 166 (AR71XX_APB_BASE + 0x000f0000) 167#define QCA955X_PCI_CTRL_BASE1 \ 168 (AR71XX_APB_BASE + 0x00280000) 169#define QCA955X_PCI_CTRL_SIZE 0x100 170 171#define QCA955X_GMAC_BASE \ 172 (AR71XX_APB_BASE + 0x00070000) 173#define QCA955X_GMAC_SIZE 0x40 174#define QCA955X_WMAC_BASE \ 175 (AR71XX_APB_BASE + 0x00100000) 176#define QCA955X_WMAC_SIZE 0x20000 177#define QCA955X_EHCI0_BASE 0x1b000000 178#define QCA955X_EHCI1_BASE 0x1b400000 179#define QCA955X_EHCI_SIZE 0x1000 180#define QCA955X_NFC_BASE 0x1b800200 181#define QCA955X_NFC_SIZE 0xb8 182 183#define QCA956X_PCI_MEM_BASE1 0x12000000 184#define QCA956X_PCI_MEM_SIZE 0x02000000 185#define QCA956X_PCI_CFG_BASE1 0x16000000 186#define QCA956X_PCI_CFG_SIZE 0x1000 187#define QCA956X_PCI_CRP_BASE1 \ 188 (AR71XX_APB_BASE + 0x00250000) 189#define QCA956X_PCI_CRP_SIZE 0x1000 190#define QCA956X_PCI_CTRL_BASE1 \ 191 (AR71XX_APB_BASE + 0x00280000) 192#define QCA956X_PCI_CTRL_SIZE 0x100 193 194#define QCA956X_WMAC_BASE \ 195 (AR71XX_APB_BASE + 0x00100000) 196#define QCA956X_WMAC_SIZE 0x20000 197#define QCA956X_EHCI0_BASE 0x1b000000 198#define QCA956X_EHCI1_BASE 0x1b400000 199#define QCA956X_EHCI_SIZE 0x200 200#define QCA956X_GMAC_BASE \ 201 (AR71XX_APB_BASE + 0x00070000) 202#define QCA956X_GMAC_SIZE 0x64 203 204/* 205 * DDR_CTRL block 206 */ 207#define AR71XX_DDR_REG_CONFIG 0x00 208#define AR71XX_DDR_REG_CONFIG2 0x04 209#define AR71XX_DDR_REG_MODE 0x08 210#define AR71XX_DDR_REG_EMR 0x0c 211#define AR71XX_DDR_REG_CONTROL 0x10 212#define AR71XX_DDR_REG_REFRESH 0x14 213#define AR71XX_DDR_REG_RD_CYCLE 0x18 214#define AR71XX_DDR_REG_TAP_CTRL0 0x1c 215#define AR71XX_DDR_REG_TAP_CTRL1 0x20 216 217#define AR71XX_DDR_REG_PCI_WIN0 0x7c 218#define AR71XX_DDR_REG_PCI_WIN1 0x80 219#define AR71XX_DDR_REG_PCI_WIN2 0x84 220#define AR71XX_DDR_REG_PCI_WIN3 0x88 221#define AR71XX_DDR_REG_PCI_WIN4 0x8c 222#define AR71XX_DDR_REG_PCI_WIN5 0x90 223#define AR71XX_DDR_REG_PCI_WIN6 0x94 224#define AR71XX_DDR_REG_PCI_WIN7 0x98 225#define AR71XX_DDR_REG_FLUSH_GE0 0x9c 226#define AR71XX_DDR_REG_FLUSH_GE1 0xa0 227#define AR71XX_DDR_REG_FLUSH_USB 0xa4 228#define AR71XX_DDR_REG_FLUSH_PCI 0xa8 229 230#define AR724X_DDR_REG_FLUSH_GE0 0x7c 231#define AR724X_DDR_REG_FLUSH_GE1 0x80 232#define AR724X_DDR_REG_FLUSH_USB 0x84 233#define AR724X_DDR_REG_FLUSH_PCIE 0x88 234 235#define AR913X_DDR_REG_FLUSH_GE0 0x7c 236#define AR913X_DDR_REG_FLUSH_GE1 0x80 237#define AR913X_DDR_REG_FLUSH_USB 0x84 238#define AR913X_DDR_REG_FLUSH_WMAC 0x88 239 240#define AR933X_DDR_REG_FLUSH_GE0 0x7c 241#define AR933X_DDR_REG_FLUSH_GE1 0x80 242#define AR933X_DDR_REG_FLUSH_USB 0x84 243#define AR933X_DDR_REG_FLUSH_WMAC 0x88 244#define AR933X_DDR_REG_DDR2_CONFIG 0x8c 245#define AR933X_DDR_REG_EMR2 0x90 246#define AR933X_DDR_REG_EMR3 0x94 247#define AR933X_DDR_REG_BURST 0x98 248#define AR933X_DDR_REG_TIMEOUT_MAX 0x9c 249#define AR933X_DDR_REG_TIMEOUT_CNT 0x9c 250#define AR933X_DDR_REG_TIMEOUT_ADDR 0x9c 251 252#define AR934X_DDR_REG_TAP_CTRL2 0x24 253#define AR934X_DDR_REG_TAP_CTRL3 0x28 254#define AR934X_DDR_REG_FLUSH_GE0 0x9c 255#define AR934X_DDR_REG_FLUSH_GE1 0xa0 256#define AR934X_DDR_REG_FLUSH_USB 0xa4 257#define AR934X_DDR_REG_FLUSH_PCIE 0xa8 258#define AR934X_DDR_REG_FLUSH_WMAC 0xac 259#define AR934X_DDR_REG_FLUSH_SRC1 0xb0 260#define AR934X_DDR_REG_FLUSH_SRC2 0xb4 261#define AR934X_DDR_REG_DDR2_CONFIG 0xb8 262#define AR934X_DDR_REG_EMR2 0xbc 263#define AR934X_DDR_REG_EMR3 0xc0 264#define AR934X_DDR_REG_BURST 0xc4 265#define AR934X_DDR_REG_BURST2 0xc8 266#define AR934X_DDR_REG_TIMEOUT_MAX 0xcc 267#define AR934X_DDR_REG_CTL_CONF 0x108 268 269#define QCA953X_DDR_REG_FLUSH_GE0 0x9c 270#define QCA953X_DDR_REG_FLUSH_GE1 0xa0 271#define QCA953X_DDR_REG_FLUSH_USB 0xa4 272#define QCA953X_DDR_REG_FLUSH_PCIE 0xa8 273#define QCA953X_DDR_REG_FLUSH_WMAC 0xac 274#define QCA953X_DDR_REG_DDR2_CONFIG 0xb8 275#define QCA953X_DDR_REG_BURST 0xc4 276#define QCA953X_DDR_REG_BURST2 0xc8 277#define QCA953X_DDR_REG_TIMEOUT_MAX 0xcc 278#define QCA953X_DDR_REG_CTL_CONF 0x108 279#define QCA953X_DDR_REG_CONFIG3 0x15c 280 281/* 282 * PLL block 283 */ 284#define AR71XX_PLL_REG_CPU_CONFIG 0x00 285#define AR71XX_PLL_REG_SEC_CONFIG 0x04 286#define AR71XX_PLL_REG_ETH0_INT_CLOCK 0x10 287#define AR71XX_PLL_REG_ETH1_INT_CLOCK 0x14 288 289#define AR71XX_PLL_DIV_SHIFT 3 290#define AR71XX_PLL_DIV_MASK 0x1f 291#define AR71XX_CPU_DIV_SHIFT 16 292#define AR71XX_CPU_DIV_MASK 0x3 293#define AR71XX_DDR_DIV_SHIFT 18 294#define AR71XX_DDR_DIV_MASK 0x3 295#define AR71XX_AHB_DIV_SHIFT 20 296#define AR71XX_AHB_DIV_MASK 0x7 297 298#define AR71XX_ETH0_PLL_SHIFT 17 299#define AR71XX_ETH1_PLL_SHIFT 19 300 301#define AR724X_PLL_REG_CPU_CONFIG 0x00 302#define AR724X_PLL_REG_PCIE_CONFIG 0x18 303 304#define AR724X_PLL_DIV_SHIFT 0 305#define AR724X_PLL_DIV_MASK 0x3ff 306#define AR724X_PLL_REF_DIV_SHIFT 10 307#define AR724X_PLL_REF_DIV_MASK 0xf 308#define AR724X_AHB_DIV_SHIFT 19 309#define AR724X_AHB_DIV_MASK 0x1 310#define AR724X_DDR_DIV_SHIFT 22 311#define AR724X_DDR_DIV_MASK 0x3 312 313#define AR7242_PLL_REG_ETH0_INT_CLOCK 0x2c 314 315#define AR913X_PLL_REG_CPU_CONFIG 0x00 316#define AR913X_PLL_REG_ETH_CONFIG 0x04 317#define AR913X_PLL_REG_ETH0_INT_CLOCK 0x14 318#define AR913X_PLL_REG_ETH1_INT_CLOCK 0x18 319 320#define AR913X_PLL_DIV_SHIFT 0 321#define AR913X_PLL_DIV_MASK 0x3ff 322#define AR913X_DDR_DIV_SHIFT 22 323#define AR913X_DDR_DIV_MASK 0x3 324#define AR913X_AHB_DIV_SHIFT 19 325#define AR913X_AHB_DIV_MASK 0x1 326 327#define AR913X_ETH0_PLL_SHIFT 20 328#define AR913X_ETH1_PLL_SHIFT 22 329 330#define AR933X_PLL_CPU_CONFIG_REG 0x00 331#define AR933X_PLL_CLK_CTRL_REG 0x08 332#define AR933X_PLL_DITHER_FRAC_REG 0x10 333#define AR933X_PLL_SWITCH_CLOCK_CONTROL_REG 0x24 334 335#define AR933X_PLL_CPU_CONFIG_NINT_SHIFT 10 336#define AR933X_PLL_CPU_CONFIG_NINT_MASK 0x3f 337#define AR933X_PLL_CPU_CONFIG_REFDIV_SHIFT 16 338#define AR933X_PLL_CPU_CONFIG_REFDIV_MASK 0x1f 339#define AR933X_PLL_CPU_CONFIG_OUTDIV_SHIFT 23 340#define AR933X_PLL_CPU_CONFIG_OUTDIV_MASK 0x7 341 342#define AR933X_PLL_CLK_CTRL_BYPASS BIT(2) 343#define AR933X_PLL_CLK_CTRL_CPU_POST_DIV_SHIFT 5 344#define AR933X_PLL_CLK_CTRL_CPU_POST_DIV_MASK 0x3 345#define AR933X_PLL_CLK_CTRL_DDR_POST_DIV_SHIFT 10 346#define AR933X_PLL_CLK_CTRL_DDR_POST_DIV_MASK 0x3 347#define AR933X_PLL_CLK_CTRL_AHB_POST_DIV_SHIFT 15 348#define AR933X_PLL_CLK_CTRL_AHB_POST_DIV_MASK 0x7 349 350#define AR934X_PLL_CPU_CONFIG_REG 0x00 351#define AR934X_PLL_DDR_CONFIG_REG 0x04 352#define AR934X_PLL_CPU_DDR_CLK_CTRL_REG 0x08 353#define AR934X_PLL_SWITCH_CLOCK_CONTROL_REG 0x24 354#define AR934X_PLL_ETH_XMII_CONTROL_REG 0x2c 355#define AR934X_PLL_DDR_DIT_FRAC_REG 0x44 356#define AR934X_PLL_CPU_DIT_FRAC_REG 0x48 357 358#define AR934X_PLL_CPU_CONFIG_NFRAC_SHIFT 0 359#define AR934X_PLL_CPU_CONFIG_NFRAC_MASK 0x3f 360#define AR934X_PLL_CPU_CONFIG_NINT_SHIFT 6 361#define AR934X_PLL_CPU_CONFIG_NINT_MASK 0x3f 362#define AR934X_PLL_CPU_CONFIG_REFDIV_SHIFT 12 363#define AR934X_PLL_CPU_CONFIG_REFDIV_MASK 0x1f 364#define AR934X_PLL_CPU_CONFIG_RANGE_SHIFT 17 365#define AR934X_PLL_CPU_CONFIG_RANGE_MASK 0x3 366#define AR934X_PLL_CPU_CONFIG_OUTDIV_SHIFT 19 367#define AR934X_PLL_CPU_CONFIG_OUTDIV_MASK 0x3 368#define AR934X_PLL_CPU_CONFIG_PLLPWD BIT(30) 369#define AR934X_PLL_CPU_CONFIG_UPDATING BIT(31) 370 371#define AR934X_PLL_DDR_CONFIG_NFRAC_SHIFT 0 372#define AR934X_PLL_DDR_CONFIG_NFRAC_MASK 0x3ff 373#define AR934X_PLL_DDR_CONFIG_NINT_SHIFT 10 374#define AR934X_PLL_DDR_CONFIG_NINT_MASK 0x3f 375#define AR934X_PLL_DDR_CONFIG_REFDIV_SHIFT 16 376#define AR934X_PLL_DDR_CONFIG_REFDIV_MASK 0x1f 377#define AR934X_PLL_DDR_CONFIG_RANGE_SHIFT 21 378#define AR934X_PLL_DDR_CONFIG_RANGE_MASK 0x3 379#define AR934X_PLL_DDR_CONFIG_OUTDIV_SHIFT 23 380#define AR934X_PLL_DDR_CONFIG_OUTDIV_MASK 0x7 381#define AR934X_PLL_DDR_CONFIG_PLLPWD BIT(30) 382#define AR934X_PLL_DDR_CONFIG_UPDATING BIT(31) 383 384#define AR934X_PLL_CLK_CTRL_CPU_PLL_BYPASS BIT(2) 385#define AR934X_PLL_CLK_CTRL_DDR_PLL_BYPASS BIT(3) 386#define AR934X_PLL_CLK_CTRL_AHB_PLL_BYPASS BIT(4) 387#define AR934X_PLL_CLK_CTRL_CPU_POST_DIV_SHIFT 5 388#define AR934X_PLL_CLK_CTRL_CPU_POST_DIV_MASK 0x1f 389#define AR934X_PLL_CLK_CTRL_DDR_POST_DIV_SHIFT 10 390#define AR934X_PLL_CLK_CTRL_DDR_POST_DIV_MASK 0x1f 391#define AR934X_PLL_CLK_CTRL_AHB_POST_DIV_SHIFT 15 392#define AR934X_PLL_CLK_CTRL_AHB_POST_DIV_MASK 0x1f 393#define AR934X_PLL_CLK_CTRL_CPUCLK_FROM_CPUPLL BIT(20) 394#define AR934X_PLL_CLK_CTRL_DDRCLK_FROM_DDRPLL BIT(21) 395#define AR934X_PLL_CLK_CTRL_AHBCLK_FROM_DDRPLL BIT(24) 396 397#define AR934X_PLL_SWITCH_CLK_CTRL_MDIO_CLK_SEL BIT(6) 398 399#define AR934X_PLL_DDR_DIT_FRAC_MAX_SHIFT 0 400#define AR934X_PLL_DDR_DIT_FRAC_MAX_MASK 0x3ff 401#define AR934X_PLL_DDR_DIT_FRAC_MIN_SHIFT 10 402#define AR934X_PLL_DDR_DIT_FRAC_MIN_MASK 0x3ff 403#define AR934X_PLL_DDR_DIT_FRAC_STEP_SHIFT 20 404#define AR934X_PLL_DDR_DIT_FRAC_STEP_MASK 0x3f 405#define AR934X_PLL_DDR_DIT_UPD_CNT_SHIFT 27 406#define AR934X_PLL_DDR_DIT_UPD_CNT_MASK 0x3f 407#define AR934X_PLL_DDR_DIT_DITHER_EN BIT(31) 408 409#define AR934X_PLL_CPU_DIT_FRAC_MAX_SHIFT 0 410#define AR934X_PLL_CPU_DIT_FRAC_MAX_MASK 0x3f 411#define AR934X_PLL_CPU_DIT_FRAC_MIN_SHIFT 6 412#define AR934X_PLL_CPU_DIT_FRAC_MIN_MASK 0x3f 413#define AR934X_PLL_CPU_DIT_FRAC_STEP_SHIFT 12 414#define AR934X_PLL_CPU_DIT_FRAC_STEP_MASK 0x3f 415#define AR934X_PLL_CPU_DIT_UPD_CNT_SHIFT 18 416#define AR934X_PLL_CPU_DIT_UPD_CNT_MASK 0x3f 417#define AR934X_PLL_CPU_DIT_DITHER_EN BIT(31) 418 419#define QCA953X_PLL_CPU_CONFIG_REG 0x00 420#define QCA953X_PLL_DDR_CONFIG_REG 0x04 421#define QCA953X_PLL_CLK_CTRL_REG 0x08 422#define QCA953X_PLL_SWITCH_CLOCK_CONTROL_REG 0x24 423#define QCA953X_PLL_ETH_XMII_CONTROL_REG 0x2c 424#define QCA953X_PLL_DDR_DIT_FRAC_REG 0x44 425#define QCA953X_PLL_CPU_DIT_FRAC_REG 0x48 426 427#define QCA953X_PLL_CPU_CONFIG_NFRAC_SHIFT 0 428#define QCA953X_PLL_CPU_CONFIG_NFRAC_MASK 0x3f 429#define QCA953X_PLL_CPU_CONFIG_NINT_SHIFT 6 430#define QCA953X_PLL_CPU_CONFIG_NINT_MASK 0x3f 431#define QCA953X_PLL_CPU_CONFIG_REFDIV_SHIFT 12 432#define QCA953X_PLL_CPU_CONFIG_REFDIV_MASK 0x1f 433#define QCA953X_PLL_CPU_CONFIG_OUTDIV_SHIFT 19 434#define QCA953X_PLL_CPU_CONFIG_OUTDIV_MASK 0x7 435 436#define QCA953X_PLL_DDR_CONFIG_NFRAC_SHIFT 0 437#define QCA953X_PLL_DDR_CONFIG_NFRAC_MASK 0x3ff 438#define QCA953X_PLL_DDR_CONFIG_NINT_SHIFT 10 439#define QCA953X_PLL_DDR_CONFIG_NINT_MASK 0x3f 440#define QCA953X_PLL_DDR_CONFIG_REFDIV_SHIFT 16 441#define QCA953X_PLL_DDR_CONFIG_REFDIV_MASK 0x1f 442#define QCA953X_PLL_DDR_CONFIG_OUTDIV_SHIFT 23 443#define QCA953X_PLL_DDR_CONFIG_OUTDIV_MASK 0x7 444 445#define QCA953X_PLL_CONFIG_PWD BIT(30) 446 447#define QCA953X_PLL_CLK_CTRL_CPU_PLL_BYPASS BIT(2) 448#define QCA953X_PLL_CLK_CTRL_DDR_PLL_BYPASS BIT(3) 449#define QCA953X_PLL_CLK_CTRL_AHB_PLL_BYPASS BIT(4) 450#define QCA953X_PLL_CLK_CTRL_CPU_POST_DIV_SHIFT 5 451#define QCA953X_PLL_CLK_CTRL_CPU_POST_DIV_MASK 0x1f 452#define QCA953X_PLL_CLK_CTRL_DDR_POST_DIV_SHIFT 10 453#define QCA953X_PLL_CLK_CTRL_DDR_POST_DIV_MASK 0x1f 454#define QCA953X_PLL_CLK_CTRL_AHB_POST_DIV_SHIFT 15 455#define QCA953X_PLL_CLK_CTRL_AHB_POST_DIV_MASK 0x1f 456#define QCA953X_PLL_CLK_CTRL_CPUCLK_FROM_CPUPLL BIT(20) 457#define QCA953X_PLL_CLK_CTRL_DDRCLK_FROM_DDRPLL BIT(21) 458#define QCA953X_PLL_CLK_CTRL_AHBCLK_FROM_DDRPLL BIT(24) 459 460#define QCA953X_PLL_CPU_DIT_FRAC_MAX_SHIFT 0 461#define QCA953X_PLL_CPU_DIT_FRAC_MAX_MASK 0x3f 462#define QCA953X_PLL_CPU_DIT_FRAC_MIN_SHIFT 6 463#define QCA953X_PLL_CPU_DIT_FRAC_MIN_MASK 0x3f 464#define QCA953X_PLL_CPU_DIT_FRAC_STEP_SHIFT 12 465#define QCA953X_PLL_CPU_DIT_FRAC_STEP_MASK 0x3f 466#define QCA953X_PLL_CPU_DIT_UPD_CNT_SHIFT 18 467#define QCA953X_PLL_CPU_DIT_UPD_CNT_MASK 0x3f 468 469#define QCA953X_PLL_DDR_DIT_FRAC_MAX_SHIFT 0 470#define QCA953X_PLL_DDR_DIT_FRAC_MAX_MASK 0x3ff 471#define QCA953X_PLL_DDR_DIT_FRAC_MIN_SHIFT 9 472#define QCA953X_PLL_DDR_DIT_FRAC_MIN_MASK 0x3ff 473#define QCA953X_PLL_DDR_DIT_FRAC_STEP_SHIFT 20 474#define QCA953X_PLL_DDR_DIT_FRAC_STEP_MASK 0x3f 475#define QCA953X_PLL_DDR_DIT_UPD_CNT_SHIFT 27 476#define QCA953X_PLL_DDR_DIT_UPD_CNT_MASK 0x3f 477 478#define QCA953X_PLL_DIT_FRAC_EN BIT(31) 479 480#define QCA955X_PLL_CPU_CONFIG_REG 0x00 481#define QCA955X_PLL_DDR_CONFIG_REG 0x04 482#define QCA955X_PLL_CLK_CTRL_REG 0x08 483#define QCA955X_PLL_ETH_XMII_CONTROL_REG 0x28 484#define QCA955X_PLL_ETH_SGMII_CONTROL_REG 0x48 485 486#define QCA955X_PLL_CPU_CONFIG_NFRAC_SHIFT 0 487#define QCA955X_PLL_CPU_CONFIG_NFRAC_MASK 0x3f 488#define QCA955X_PLL_CPU_CONFIG_NINT_SHIFT 6 489#define QCA955X_PLL_CPU_CONFIG_NINT_MASK 0x3f 490#define QCA955X_PLL_CPU_CONFIG_REFDIV_SHIFT 12 491#define QCA955X_PLL_CPU_CONFIG_REFDIV_MASK 0x1f 492#define QCA955X_PLL_CPU_CONFIG_OUTDIV_SHIFT 19 493#define QCA955X_PLL_CPU_CONFIG_OUTDIV_MASK 0x3 494 495#define QCA955X_PLL_DDR_CONFIG_NFRAC_SHIFT 0 496#define QCA955X_PLL_DDR_CONFIG_NFRAC_MASK 0x3ff 497#define QCA955X_PLL_DDR_CONFIG_NINT_SHIFT 10 498#define QCA955X_PLL_DDR_CONFIG_NINT_MASK 0x3f 499#define QCA955X_PLL_DDR_CONFIG_REFDIV_SHIFT 16 500#define QCA955X_PLL_DDR_CONFIG_REFDIV_MASK 0x1f 501#define QCA955X_PLL_DDR_CONFIG_OUTDIV_SHIFT 23 502#define QCA955X_PLL_DDR_CONFIG_OUTDIV_MASK 0x7 503 504#define QCA955X_PLL_CLK_CTRL_CPU_PLL_BYPASS BIT(2) 505#define QCA955X_PLL_CLK_CTRL_DDR_PLL_BYPASS BIT(3) 506#define QCA955X_PLL_CLK_CTRL_AHB_PLL_BYPASS BIT(4) 507#define QCA955X_PLL_CLK_CTRL_CPU_POST_DIV_SHIFT 5 508#define QCA955X_PLL_CLK_CTRL_CPU_POST_DIV_MASK 0x1f 509#define QCA955X_PLL_CLK_CTRL_DDR_POST_DIV_SHIFT 10 510#define QCA955X_PLL_CLK_CTRL_DDR_POST_DIV_MASK 0x1f 511#define QCA955X_PLL_CLK_CTRL_AHB_POST_DIV_SHIFT 15 512#define QCA955X_PLL_CLK_CTRL_AHB_POST_DIV_MASK 0x1f 513#define QCA955X_PLL_CLK_CTRL_CPUCLK_FROM_CPUPLL BIT(20) 514#define QCA955X_PLL_CLK_CTRL_DDRCLK_FROM_DDRPLL BIT(21) 515#define QCA955X_PLL_CLK_CTRL_AHBCLK_FROM_DDRPLL BIT(24) 516 517#define QCA956X_PLL_CPU_CONFIG_REG 0x00 518#define QCA956X_PLL_CPU_CONFIG1_REG 0x04 519#define QCA956X_PLL_DDR_CONFIG_REG 0x08 520#define QCA956X_PLL_DDR_CONFIG1_REG 0x0c 521#define QCA956X_PLL_CLK_CTRL_REG 0x10 522 523#define QCA956X_PLL_CPU_CONFIG_REFDIV_SHIFT 12 524#define QCA956X_PLL_CPU_CONFIG_REFDIV_MASK 0x1f 525#define QCA956X_PLL_CPU_CONFIG_OUTDIV_SHIFT 19 526#define QCA956X_PLL_CPU_CONFIG_OUTDIV_MASK 0x7 527 528#define QCA956X_PLL_CPU_CONFIG1_NFRAC_L_SHIFT 0 529#define QCA956X_PLL_CPU_CONFIG1_NFRAC_L_MASK 0x1f 530#define QCA956X_PLL_CPU_CONFIG1_NFRAC_H_SHIFT 5 531#define QCA956X_PLL_CPU_CONFIG1_NFRAC_H_MASK 0x3fff 532#define QCA956X_PLL_CPU_CONFIG1_NINT_SHIFT 18 533#define QCA956X_PLL_CPU_CONFIG1_NINT_MASK 0x1ff 534 535#define QCA956X_PLL_DDR_CONFIG_REFDIV_SHIFT 16 536#define QCA956X_PLL_DDR_CONFIG_REFDIV_MASK 0x1f 537#define QCA956X_PLL_DDR_CONFIG_OUTDIV_SHIFT 23 538#define QCA956X_PLL_DDR_CONFIG_OUTDIV_MASK 0x7 539 540#define QCA956X_PLL_DDR_CONFIG1_NFRAC_L_SHIFT 0 541#define QCA956X_PLL_DDR_CONFIG1_NFRAC_L_MASK 0x1f 542#define QCA956X_PLL_DDR_CONFIG1_NFRAC_H_SHIFT 5 543#define QCA956X_PLL_DDR_CONFIG1_NFRAC_H_MASK 0x3fff 544#define QCA956X_PLL_DDR_CONFIG1_NINT_SHIFT 18 545#define QCA956X_PLL_DDR_CONFIG1_NINT_MASK 0x1ff 546 547#define QCA956X_PLL_CLK_CTRL_CPU_PLL_BYPASS BIT(2) 548#define QCA956X_PLL_CLK_CTRL_DDR_PLL_BYPASS BIT(3) 549#define QCA956X_PLL_CLK_CTRL_AHB_PLL_BYPASS BIT(4) 550#define QCA956X_PLL_CLK_CTRL_CPU_POST_DIV_SHIFT 5 551#define QCA956X_PLL_CLK_CTRL_CPU_POST_DIV_MASK 0x1f 552#define QCA956X_PLL_CLK_CTRL_DDR_POST_DIV_SHIFT 10 553#define QCA956X_PLL_CLK_CTRL_DDR_POST_DIV_MASK 0x1f 554#define QCA956X_PLL_CLK_CTRL_AHB_POST_DIV_SHIFT 15 555#define QCA956X_PLL_CLK_CTRL_AHB_POST_DIV_MASK 0x1f 556#define QCA956X_PLL_CLK_CTRL_CPU_DDRCLK_FROM_DDRPLL BIT(20) 557#define QCA956X_PLL_CLK_CTRL_CPU_DDRCLK_FROM_CPUPLL BIT(21) 558#define QCA956X_PLL_CLK_CTRL_AHBCLK_FROM_DDRPLL BIT(24) 559 560/* 561 * USB_CONFIG block 562 */ 563#define AR71XX_USB_CTRL_REG_FLADJ 0x00 564#define AR71XX_USB_CTRL_REG_CONFIG 0x04 565 566/* 567 * RESET block 568 */ 569#define AR71XX_RESET_REG_TIMER 0x00 570#define AR71XX_RESET_REG_TIMER_RELOAD 0x04 571#define AR71XX_RESET_REG_WDOG_CTRL 0x08 572#define AR71XX_RESET_REG_WDOG 0x0c 573#define AR71XX_RESET_REG_MISC_INT_STATUS 0x10 574#define AR71XX_RESET_REG_MISC_INT_ENABLE 0x14 575#define AR71XX_RESET_REG_PCI_INT_STATUS 0x18 576#define AR71XX_RESET_REG_PCI_INT_ENABLE 0x1c 577#define AR71XX_RESET_REG_GLOBAL_INT_STATUS 0x20 578#define AR71XX_RESET_REG_RESET_MODULE 0x24 579#define AR71XX_RESET_REG_PERFC_CTRL 0x2c 580#define AR71XX_RESET_REG_PERFC0 0x30 581#define AR71XX_RESET_REG_PERFC1 0x34 582#define AR71XX_RESET_REG_REV_ID 0x90 583 584#define AR913X_RESET_REG_GLOBAL_INT_STATUS 0x18 585#define AR913X_RESET_REG_RESET_MODULE 0x1c 586#define AR913X_RESET_REG_PERF_CTRL 0x20 587#define AR913X_RESET_REG_PERFC0 0x24 588#define AR913X_RESET_REG_PERFC1 0x28 589 590#define AR724X_RESET_REG_RESET_MODULE 0x1c 591 592#define AR933X_RESET_REG_RESET_MODULE 0x1c 593#define AR933X_RESET_REG_BOOTSTRAP 0xac 594 595#define AR934X_RESET_REG_RESET_MODULE 0x1c 596#define AR934X_RESET_REG_BOOTSTRAP 0xb0 597#define AR934X_RESET_REG_PCIE_WMAC_INT_STATUS 0xac 598 599#define QCA953X_RESET_REG_RESET_MODULE 0x1c 600#define QCA953X_RESET_REG_BOOTSTRAP 0xb0 601#define QCA953X_RESET_REG_PCIE_WMAC_INT_STATUS 0xac 602 603#define QCA955X_RESET_REG_RESET_MODULE 0x1c 604#define QCA955X_RESET_REG_BOOTSTRAP 0xb0 605#define QCA955X_RESET_REG_EXT_INT_STATUS 0xac 606 607#define QCA956X_RESET_REG_RESET_MODULE 0x1c 608#define QCA956X_RESET_REG_BOOTSTRAP 0xb0 609#define QCA956X_RESET_REG_EXT_INT_STATUS 0xac 610 611#define MISC_INT_MIPS_SI_TIMERINT_MASK BIT(28) 612#define MISC_INT_ETHSW BIT(12) 613#define MISC_INT_TIMER4 BIT(10) 614#define MISC_INT_TIMER3 BIT(9) 615#define MISC_INT_TIMER2 BIT(8) 616#define MISC_INT_DMA BIT(7) 617#define MISC_INT_OHCI BIT(6) 618#define MISC_INT_PERFC BIT(5) 619#define MISC_INT_WDOG BIT(4) 620#define MISC_INT_UART BIT(3) 621#define MISC_INT_GPIO BIT(2) 622#define MISC_INT_ERROR BIT(1) 623#define MISC_INT_TIMER BIT(0) 624 625#define AR71XX_RESET_EXTERNAL BIT(28) 626#define AR71XX_RESET_FULL_CHIP BIT(24) 627#define AR71XX_RESET_CPU_NMI BIT(21) 628#define AR71XX_RESET_CPU_COLD BIT(20) 629#define AR71XX_RESET_DMA BIT(19) 630#define AR71XX_RESET_SLIC BIT(18) 631#define AR71XX_RESET_STEREO BIT(17) 632#define AR71XX_RESET_DDR BIT(16) 633#define AR71XX_RESET_GE1_MAC BIT(13) 634#define AR71XX_RESET_GE1_PHY BIT(12) 635#define AR71XX_RESET_USBSUS_OVERRIDE BIT(10) 636#define AR71XX_RESET_GE0_MAC BIT(9) 637#define AR71XX_RESET_GE0_PHY BIT(8) 638#define AR71XX_RESET_USB_OHCI_DLL BIT(6) 639#define AR71XX_RESET_USB_HOST BIT(5) 640#define AR71XX_RESET_USB_PHY BIT(4) 641#define AR71XX_RESET_PCI_BUS BIT(1) 642#define AR71XX_RESET_PCI_CORE BIT(0) 643 644#define AR7240_RESET_USB_HOST BIT(5) 645#define AR7240_RESET_OHCI_DLL BIT(3) 646 647#define AR724X_RESET_GE1_MDIO BIT(23) 648#define AR724X_RESET_GE0_MDIO BIT(22) 649#define AR724X_RESET_PCIE_PHY_SERIAL BIT(10) 650#define AR724X_RESET_PCIE_PHY BIT(7) 651#define AR724X_RESET_PCIE BIT(6) 652#define AR724X_RESET_USB_HOST BIT(5) 653#define AR724X_RESET_USB_PHY BIT(4) 654#define AR724X_RESET_USBSUS_OVERRIDE BIT(3) 655 656#define AR913X_RESET_AMBA2WMAC BIT(22) 657#define AR913X_RESET_USBSUS_OVERRIDE BIT(10) 658#define AR913X_RESET_USB_HOST BIT(5) 659#define AR913X_RESET_USB_PHY BIT(4) 660 661#define AR933X_RESET_GE1_MDIO BIT(23) 662#define AR933X_RESET_GE0_MDIO BIT(22) 663#define AR933X_RESET_ETH_SWITCH_ANALOG BIT(14) 664#define AR933X_RESET_GE1_MAC BIT(13) 665#define AR933X_RESET_WMAC BIT(11) 666#define AR933X_RESET_GE0_MAC BIT(9) 667#define AR933X_RESET_ETH_SWITCH BIT(8) 668#define AR933X_RESET_USB_HOST BIT(5) 669#define AR933X_RESET_USB_PHY BIT(4) 670#define AR933X_RESET_USBSUS_OVERRIDE BIT(3) 671 672#define AR934X_RESET_HOST BIT(31) 673#define AR934X_RESET_SLIC BIT(30) 674#define AR934X_RESET_HDMA BIT(29) 675#define AR934X_RESET_EXTERNAL BIT(28) 676#define AR934X_RESET_RTC BIT(27) 677#define AR934X_RESET_PCIE_EP_INT BIT(26) 678#define AR934X_RESET_CHKSUM_ACC BIT(25) 679#define AR934X_RESET_FULL_CHIP BIT(24) 680#define AR934X_RESET_GE1_MDIO BIT(23) 681#define AR934X_RESET_GE0_MDIO BIT(22) 682#define AR934X_RESET_CPU_NMI BIT(21) 683#define AR934X_RESET_CPU_COLD BIT(20) 684#define AR934X_RESET_HOST_RESET_INT BIT(19) 685#define AR934X_RESET_PCIE_EP BIT(18) 686#define AR934X_RESET_UART1 BIT(17) 687#define AR934X_RESET_DDR BIT(16) 688#define AR934X_RESET_USB_PHY_PLL_PWD_EXT BIT(15) 689#define AR934X_RESET_NANDF BIT(14) 690#define AR934X_RESET_GE1_MAC BIT(13) 691#define AR934X_RESET_ETH_SWITCH_ANALOG BIT(12) 692#define AR934X_RESET_USB_PHY_ANALOG BIT(11) 693#define AR934X_RESET_HOST_DMA_INT BIT(10) 694#define AR934X_RESET_GE0_MAC BIT(9) 695#define AR934X_RESET_ETH_SWITCH BIT(8) 696#define AR934X_RESET_PCIE_PHY BIT(7) 697#define AR934X_RESET_PCIE BIT(6) 698#define AR934X_RESET_USB_HOST BIT(5) 699#define AR934X_RESET_USB_PHY BIT(4) 700#define AR934X_RESET_USBSUS_OVERRIDE BIT(3) 701#define AR934X_RESET_LUT BIT(2) 702#define AR934X_RESET_MBOX BIT(1) 703#define AR934X_RESET_I2S BIT(0) 704 705#define QCA953X_RESET_USB_EXT_PWR BIT(29) 706#define QCA953X_RESET_EXTERNAL BIT(28) 707#define QCA953X_RESET_RTC BIT(27) 708#define QCA953X_RESET_FULL_CHIP BIT(24) 709#define QCA953X_RESET_GE1_MDIO BIT(23) 710#define QCA953X_RESET_GE0_MDIO BIT(22) 711#define QCA953X_RESET_CPU_NMI BIT(21) 712#define QCA953X_RESET_CPU_COLD BIT(20) 713#define QCA953X_RESET_DDR BIT(16) 714#define QCA953X_RESET_USB_PHY_PLL_PWD_EXT BIT(15) 715#define QCA953X_RESET_GE1_MAC BIT(13) 716#define QCA953X_RESET_ETH_SWITCH_ANALOG BIT(12) 717#define QCA953X_RESET_USB_PHY_ANALOG BIT(11) 718#define QCA953X_RESET_GE0_MAC BIT(9) 719#define QCA953X_RESET_ETH_SWITCH BIT(8) 720#define QCA953X_RESET_PCIE_PHY BIT(7) 721#define QCA953X_RESET_PCIE BIT(6) 722#define QCA953X_RESET_USB_HOST BIT(5) 723#define QCA953X_RESET_USB_PHY BIT(4) 724#define QCA953X_RESET_USBSUS_OVERRIDE BIT(3) 725 726#define QCA955X_RESET_HOST BIT(31) 727#define QCA955X_RESET_SLIC BIT(30) 728#define QCA955X_RESET_HDMA BIT(29) 729#define QCA955X_RESET_EXTERNAL BIT(28) 730#define QCA955X_RESET_RTC BIT(27) 731#define QCA955X_RESET_PCIE_EP_INT BIT(26) 732#define QCA955X_RESET_CHKSUM_ACC BIT(25) 733#define QCA955X_RESET_FULL_CHIP BIT(24) 734#define QCA955X_RESET_GE1_MDIO BIT(23) 735#define QCA955X_RESET_GE0_MDIO BIT(22) 736#define QCA955X_RESET_CPU_NMI BIT(21) 737#define QCA955X_RESET_CPU_COLD BIT(20) 738#define QCA955X_RESET_HOST_RESET_INT BIT(19) 739#define QCA955X_RESET_PCIE_EP BIT(18) 740#define QCA955X_RESET_UART1 BIT(17) 741#define QCA955X_RESET_DDR BIT(16) 742#define QCA955X_RESET_USB_PHY_PLL_PWD_EXT BIT(15) 743#define QCA955X_RESET_NANDF BIT(14) 744#define QCA955X_RESET_GE1_MAC BIT(13) 745#define QCA955X_RESET_SGMII_ANALOG BIT(12) 746#define QCA955X_RESET_USB_PHY_ANALOG BIT(11) 747#define QCA955X_RESET_HOST_DMA_INT BIT(10) 748#define QCA955X_RESET_GE0_MAC BIT(9) 749#define QCA955X_RESET_SGMII BIT(8) 750#define QCA955X_RESET_PCIE_PHY BIT(7) 751#define QCA955X_RESET_PCIE BIT(6) 752#define QCA955X_RESET_USB_HOST BIT(5) 753#define QCA955X_RESET_USB_PHY BIT(4) 754#define QCA955X_RESET_USBSUS_OVERRIDE BIT(3) 755#define QCA955X_RESET_LUT BIT(2) 756#define QCA955X_RESET_MBOX BIT(1) 757#define QCA955X_RESET_I2S BIT(0) 758 759#define AR933X_BOOTSTRAP_MDIO_GPIO_EN BIT(18) 760#define AR933X_BOOTSTRAP_DDR2 BIT(13) 761#define AR933X_BOOTSTRAP_EEPBUSY BIT(4) 762#define AR933X_BOOTSTRAP_REF_CLK_40 BIT(0) 763 764#define AR934X_BOOTSTRAP_SW_OPTION8 BIT(23) 765#define AR934X_BOOTSTRAP_SW_OPTION7 BIT(22) 766#define AR934X_BOOTSTRAP_SW_OPTION6 BIT(21) 767#define AR934X_BOOTSTRAP_SW_OPTION5 BIT(20) 768#define AR934X_BOOTSTRAP_SW_OPTION4 BIT(19) 769#define AR934X_BOOTSTRAP_SW_OPTION3 BIT(18) 770#define AR934X_BOOTSTRAP_SW_OPTION2 BIT(17) 771#define AR934X_BOOTSTRAP_SW_OPTION1 BIT(16) 772#define AR934X_BOOTSTRAP_USB_MODE_DEVICE BIT(7) 773#define AR934X_BOOTSTRAP_PCIE_RC BIT(6) 774#define AR934X_BOOTSTRAP_EJTAG_MODE BIT(5) 775#define AR934X_BOOTSTRAP_REF_CLK_40 BIT(4) 776#define AR934X_BOOTSTRAP_BOOT_FROM_SPI BIT(2) 777#define AR934X_BOOTSTRAP_SDRAM_DISABLED BIT(1) 778#define AR934X_BOOTSTRAP_DDR1 BIT(0) 779 780#define QCA953X_BOOTSTRAP_SW_OPTION2 BIT(12) 781#define QCA953X_BOOTSTRAP_SW_OPTION1 BIT(11) 782#define QCA953X_BOOTSTRAP_EJTAG_MODE BIT(5) 783#define QCA953X_BOOTSTRAP_REF_CLK_40 BIT(4) 784#define QCA953X_BOOTSTRAP_SDRAM_DISABLED BIT(1) 785#define QCA953X_BOOTSTRAP_DDR1 BIT(0) 786 787#define QCA955X_BOOTSTRAP_REF_CLK_40 BIT(4) 788 789#define QCA956X_BOOTSTRAP_REF_CLK_40 BIT(2) 790 791#define AR934X_PCIE_WMAC_INT_WMAC_MISC BIT(0) 792#define AR934X_PCIE_WMAC_INT_WMAC_TX BIT(1) 793#define AR934X_PCIE_WMAC_INT_WMAC_RXLP BIT(2) 794#define AR934X_PCIE_WMAC_INT_WMAC_RXHP BIT(3) 795#define AR934X_PCIE_WMAC_INT_PCIE_RC BIT(4) 796#define AR934X_PCIE_WMAC_INT_PCIE_RC0 BIT(5) 797#define AR934X_PCIE_WMAC_INT_PCIE_RC1 BIT(6) 798#define AR934X_PCIE_WMAC_INT_PCIE_RC2 BIT(7) 799#define AR934X_PCIE_WMAC_INT_PCIE_RC3 BIT(8) 800#define AR934X_PCIE_WMAC_INT_WMAC_ALL \ 801 (AR934X_PCIE_WMAC_INT_WMAC_MISC | AR934X_PCIE_WMAC_INT_WMAC_TX | \ 802 AR934X_PCIE_WMAC_INT_WMAC_RXLP | AR934X_PCIE_WMAC_INT_WMAC_RXHP) 803 804#define AR934X_PCIE_WMAC_INT_PCIE_ALL \ 805 (AR934X_PCIE_WMAC_INT_PCIE_RC | AR934X_PCIE_WMAC_INT_PCIE_RC0 | \ 806 AR934X_PCIE_WMAC_INT_PCIE_RC1 | AR934X_PCIE_WMAC_INT_PCIE_RC2 | \ 807 AR934X_PCIE_WMAC_INT_PCIE_RC3) 808 809#define QCA953X_PCIE_WMAC_INT_WMAC_MISC BIT(0) 810#define QCA953X_PCIE_WMAC_INT_WMAC_TX BIT(1) 811#define QCA953X_PCIE_WMAC_INT_WMAC_RXLP BIT(2) 812#define QCA953X_PCIE_WMAC_INT_WMAC_RXHP BIT(3) 813#define QCA953X_PCIE_WMAC_INT_PCIE_RC BIT(4) 814#define QCA953X_PCIE_WMAC_INT_PCIE_RC0 BIT(5) 815#define QCA953X_PCIE_WMAC_INT_PCIE_RC1 BIT(6) 816#define QCA953X_PCIE_WMAC_INT_PCIE_RC2 BIT(7) 817#define QCA953X_PCIE_WMAC_INT_PCIE_RC3 BIT(8) 818#define QCA953X_PCIE_WMAC_INT_WMAC_ALL \ 819 (QCA953X_PCIE_WMAC_INT_WMAC_MISC | QCA953X_PCIE_WMAC_INT_WMAC_TX | \ 820 QCA953X_PCIE_WMAC_INT_WMAC_RXLP | QCA953X_PCIE_WMAC_INT_WMAC_RXHP) 821 822#define QCA953X_PCIE_WMAC_INT_PCIE_ALL \ 823 (QCA953X_PCIE_WMAC_INT_PCIE_RC | QCA953X_PCIE_WMAC_INT_PCIE_RC0 | \ 824 QCA953X_PCIE_WMAC_INT_PCIE_RC1 | QCA953X_PCIE_WMAC_INT_PCIE_RC2 | \ 825 QCA953X_PCIE_WMAC_INT_PCIE_RC3) 826 827#define QCA955X_EXT_INT_WMAC_MISC BIT(0) 828#define QCA955X_EXT_INT_WMAC_TX BIT(1) 829#define QCA955X_EXT_INT_WMAC_RXLP BIT(2) 830#define QCA955X_EXT_INT_WMAC_RXHP BIT(3) 831#define QCA955X_EXT_INT_PCIE_RC1 BIT(4) 832#define QCA955X_EXT_INT_PCIE_RC1_INT0 BIT(5) 833#define QCA955X_EXT_INT_PCIE_RC1_INT1 BIT(6) 834#define QCA955X_EXT_INT_PCIE_RC1_INT2 BIT(7) 835#define QCA955X_EXT_INT_PCIE_RC1_INT3 BIT(8) 836#define QCA955X_EXT_INT_PCIE_RC2 BIT(12) 837#define QCA955X_EXT_INT_PCIE_RC2_INT0 BIT(13) 838#define QCA955X_EXT_INT_PCIE_RC2_INT1 BIT(14) 839#define QCA955X_EXT_INT_PCIE_RC2_INT2 BIT(15) 840#define QCA955X_EXT_INT_PCIE_RC2_INT3 BIT(16) 841#define QCA955X_EXT_INT_USB1 BIT(24) 842#define QCA955X_EXT_INT_USB2 BIT(28) 843 844#define QCA955X_EXT_INT_WMAC_ALL \ 845 (QCA955X_EXT_INT_WMAC_MISC | QCA955X_EXT_INT_WMAC_TX | \ 846 QCA955X_EXT_INT_WMAC_RXLP | QCA955X_EXT_INT_WMAC_RXHP) 847 848#define QCA955X_EXT_INT_PCIE_RC1_ALL \ 849 (QCA955X_EXT_INT_PCIE_RC1 | QCA955X_EXT_INT_PCIE_RC1_INT0 | \ 850 QCA955X_EXT_INT_PCIE_RC1_INT1 | QCA955X_EXT_INT_PCIE_RC1_INT2 | \ 851 QCA955X_EXT_INT_PCIE_RC1_INT3) 852 853#define QCA955X_EXT_INT_PCIE_RC2_ALL \ 854 (QCA955X_EXT_INT_PCIE_RC2 | QCA955X_EXT_INT_PCIE_RC2_INT0 | \ 855 QCA955X_EXT_INT_PCIE_RC2_INT1 | QCA955X_EXT_INT_PCIE_RC2_INT2 | \ 856 QCA955X_EXT_INT_PCIE_RC2_INT3) 857 858#define QCA956X_EXT_INT_WMAC_MISC BIT(0) 859#define QCA956X_EXT_INT_WMAC_TX BIT(1) 860#define QCA956X_EXT_INT_WMAC_RXLP BIT(2) 861#define QCA956X_EXT_INT_WMAC_RXHP BIT(3) 862#define QCA956X_EXT_INT_PCIE_RC1 BIT(4) 863#define QCA956X_EXT_INT_PCIE_RC1_INT0 BIT(5) 864#define QCA956X_EXT_INT_PCIE_RC1_INT1 BIT(6) 865#define QCA956X_EXT_INT_PCIE_RC1_INT2 BIT(7) 866#define QCA956X_EXT_INT_PCIE_RC1_INT3 BIT(8) 867#define QCA956X_EXT_INT_PCIE_RC2 BIT(12) 868#define QCA956X_EXT_INT_PCIE_RC2_INT0 BIT(13) 869#define QCA956X_EXT_INT_PCIE_RC2_INT1 BIT(14) 870#define QCA956X_EXT_INT_PCIE_RC2_INT2 BIT(15) 871#define QCA956X_EXT_INT_PCIE_RC2_INT3 BIT(16) 872#define QCA956X_EXT_INT_USB1 BIT(24) 873#define QCA956X_EXT_INT_USB2 BIT(28) 874 875#define QCA956X_EXT_INT_WMAC_ALL \ 876 (QCA956X_EXT_INT_WMAC_MISC | QCA956X_EXT_INT_WMAC_TX | \ 877 QCA956X_EXT_INT_WMAC_RXLP | QCA956X_EXT_INT_WMAC_RXHP) 878 879#define QCA956X_EXT_INT_PCIE_RC1_ALL \ 880 (QCA956X_EXT_INT_PCIE_RC1 | QCA956X_EXT_INT_PCIE_RC1_INT0 | \ 881 QCA956X_EXT_INT_PCIE_RC1_INT1 | QCA956X_EXT_INT_PCIE_RC1_INT2 | \ 882 QCA956X_EXT_INT_PCIE_RC1_INT3) 883 884#define QCA956X_EXT_INT_PCIE_RC2_ALL \ 885 (QCA956X_EXT_INT_PCIE_RC2 | QCA956X_EXT_INT_PCIE_RC2_INT0 | \ 886 QCA956X_EXT_INT_PCIE_RC2_INT1 | QCA956X_EXT_INT_PCIE_RC2_INT2 | \ 887 QCA956X_EXT_INT_PCIE_RC2_INT3) 888 889#define REV_ID_MAJOR_MASK 0xfff0 890#define REV_ID_MAJOR_AR71XX 0x00a0 891#define REV_ID_MAJOR_AR913X 0x00b0 892#define REV_ID_MAJOR_AR7240 0x00c0 893#define REV_ID_MAJOR_AR7241 0x0100 894#define REV_ID_MAJOR_AR7242 0x1100 895#define REV_ID_MAJOR_AR9330 0x0110 896#define REV_ID_MAJOR_AR9331 0x1110 897#define REV_ID_MAJOR_AR9341 0x0120 898#define REV_ID_MAJOR_AR9342 0x1120 899#define REV_ID_MAJOR_AR9344 0x2120 900#define REV_ID_MAJOR_QCA9533 0x0140 901#define REV_ID_MAJOR_QCA9533_V2 0x0160 902#define REV_ID_MAJOR_QCA9556 0x0130 903#define REV_ID_MAJOR_QCA9558 0x1130 904#define REV_ID_MAJOR_TP9343 0x0150 905#define REV_ID_MAJOR_QCA9561 0x1150 906 907#define AR71XX_REV_ID_MINOR_MASK 0x3 908#define AR71XX_REV_ID_MINOR_AR7130 0x0 909#define AR71XX_REV_ID_MINOR_AR7141 0x1 910#define AR71XX_REV_ID_MINOR_AR7161 0x2 911#define AR913X_REV_ID_MINOR_AR9130 0x0 912#define AR913X_REV_ID_MINOR_AR9132 0x1 913 914#define AR71XX_REV_ID_REVISION_MASK 0x3 915#define AR71XX_REV_ID_REVISION_SHIFT 2 916#define AR71XX_REV_ID_REVISION2_MASK 0xf 917 918/* 919 * RTC block 920 */ 921#define AR933X_RTC_REG_RESET 0x40 922#define AR933X_RTC_REG_STATUS 0x44 923#define AR933X_RTC_REG_DERIVED 0x48 924#define AR933X_RTC_REG_FORCE_WAKE 0x4c 925#define AR933X_RTC_REG_INT_CAUSE 0x50 926#define AR933X_RTC_REG_CAUSE_CLR 0x50 927#define AR933X_RTC_REG_INT_ENABLE 0x54 928#define AR933X_RTC_REG_INT_MASKE 0x58 929 930#define QCA953X_RTC_REG_SYNC_RESET 0x40 931#define QCA953X_RTC_REG_SYNC_STATUS 0x44 932 933/* 934 * SPI block 935 */ 936#define AR71XX_SPI_REG_FS 0x00 937#define AR71XX_SPI_REG_CTRL 0x04 938#define AR71XX_SPI_REG_IOC 0x08 939#define AR71XX_SPI_REG_RDS 0x0c 940 941#define AR71XX_SPI_FS_GPIO BIT(0) 942 943#define AR71XX_SPI_CTRL_RD BIT(6) 944#define AR71XX_SPI_CTRL_DIV_MASK 0x3f 945 946#define AR71XX_SPI_IOC_DO BIT(0) 947#define AR71XX_SPI_IOC_CLK BIT(8) 948#define AR71XX_SPI_IOC_CS(n) BIT(16 + (n)) 949#define AR71XX_SPI_IOC_CS0 AR71XX_SPI_IOC_CS(0) 950#define AR71XX_SPI_IOC_CS1 AR71XX_SPI_IOC_CS(1) 951#define AR71XX_SPI_IOC_CS2 AR71XX_SPI_IOC_CS(2) 952#define AR71XX_SPI_IOC_CS_ALL \ 953 (AR71XX_SPI_IOC_CS0 | AR71XX_SPI_IOC_CS1 | AR71XX_SPI_IOC_CS2) 954 955/* 956 * GPIO block 957 */ 958#define AR71XX_GPIO_REG_OE 0x00 959#define AR71XX_GPIO_REG_IN 0x04 960#define AR71XX_GPIO_REG_OUT 0x08 961#define AR71XX_GPIO_REG_SET 0x0c 962#define AR71XX_GPIO_REG_CLEAR 0x10 963#define AR71XX_GPIO_REG_INT_MODE 0x14 964#define AR71XX_GPIO_REG_INT_TYPE 0x18 965#define AR71XX_GPIO_REG_INT_POLARITY 0x1c 966#define AR71XX_GPIO_REG_INT_PENDING 0x20 967#define AR71XX_GPIO_REG_INT_ENABLE 0x24 968#define AR71XX_GPIO_REG_FUNC 0x28 969#define AR933X_GPIO_REG_FUNC 0x30 970 971#define AR934X_GPIO_REG_OUT_FUNC0 0x2c 972#define AR934X_GPIO_REG_OUT_FUNC1 0x30 973#define AR934X_GPIO_REG_OUT_FUNC2 0x34 974#define AR934X_GPIO_REG_OUT_FUNC3 0x38 975#define AR934X_GPIO_REG_OUT_FUNC4 0x3c 976#define AR934X_GPIO_REG_OUT_FUNC5 0x40 977#define AR934X_GPIO_REG_FUNC 0x6c 978 979#define QCA953X_GPIO_REG_OUT_FUNC0 0x2c 980#define QCA953X_GPIO_REG_OUT_FUNC1 0x30 981#define QCA953X_GPIO_REG_OUT_FUNC2 0x34 982#define QCA953X_GPIO_REG_OUT_FUNC3 0x38 983#define QCA953X_GPIO_REG_OUT_FUNC4 0x3c 984#define QCA953X_GPIO_REG_IN_ENABLE0 0x44 985#define QCA953X_GPIO_REG_FUNC 0x6c 986 987#define QCA955X_GPIO_REG_OUT_FUNC0 0x2c 988#define QCA955X_GPIO_REG_OUT_FUNC1 0x30 989#define QCA955X_GPIO_REG_OUT_FUNC2 0x34 990#define QCA955X_GPIO_REG_OUT_FUNC3 0x38 991#define QCA955X_GPIO_REG_OUT_FUNC4 0x3c 992#define QCA955X_GPIO_REG_OUT_FUNC5 0x40 993#define QCA955X_GPIO_REG_FUNC 0x6c 994 995#define QCA956X_GPIO_REG_OUT_FUNC0 0x2c 996#define QCA956X_GPIO_REG_OUT_FUNC1 0x30 997#define QCA956X_GPIO_REG_OUT_FUNC2 0x34 998#define QCA956X_GPIO_REG_OUT_FUNC3 0x38 999#define QCA956X_GPIO_REG_OUT_FUNC4 0x3c 1000#define QCA956X_GPIO_REG_OUT_FUNC5 0x40
1001#define QCA956X_GPIO_REG_IN_ENABLE0 0x44 1002#define QCA956X_GPIO_REG_IN_ENABLE3 0x50 1003#define QCA956X_GPIO_REG_FUNC 0x6c 1004 1005#define AR71XX_GPIO_FUNC_STEREO_EN BIT(17) 1006#define AR71XX_GPIO_FUNC_SLIC_EN BIT(16) 1007#define AR71XX_GPIO_FUNC_SPI_CS2_EN BIT(13) 1008#define AR71XX_GPIO_FUNC_SPI_CS1_EN BIT(12) 1009#define AR71XX_GPIO_FUNC_UART_EN BIT(8) 1010#define AR71XX_GPIO_FUNC_USB_OC_EN BIT(4) 1011#define AR71XX_GPIO_FUNC_USB_CLK_EN BIT(0) 1012 1013#define AR724X_GPIO_FUNC_GE0_MII_CLK_EN BIT(19) 1014#define AR724X_GPIO_FUNC_SPI_EN BIT(18) 1015#define AR724X_GPIO_FUNC_SPI_CS_EN2 BIT(14) 1016#define AR724X_GPIO_FUNC_SPI_CS_EN1 BIT(13) 1017#define AR724X_GPIO_FUNC_CLK_OBS5_EN BIT(12) 1018#define AR724X_GPIO_FUNC_CLK_OBS4_EN BIT(11) 1019#define AR724X_GPIO_FUNC_CLK_OBS3_EN BIT(10) 1020#define AR724X_GPIO_FUNC_CLK_OBS2_EN BIT(9) 1021#define AR724X_GPIO_FUNC_CLK_OBS1_EN BIT(8) 1022#define AR724X_GPIO_FUNC_ETH_SWITCH_LED4_EN BIT(7) 1023#define AR724X_GPIO_FUNC_ETH_SWITCH_LED3_EN BIT(6) 1024#define AR724X_GPIO_FUNC_ETH_SWITCH_LED2_EN BIT(5) 1025#define AR724X_GPIO_FUNC_ETH_SWITCH_LED1_EN BIT(4) 1026#define AR724X_GPIO_FUNC_ETH_SWITCH_LED0_EN BIT(3) 1027#define AR724X_GPIO_FUNC_UART_RTS_CTS_EN BIT(2) 1028#define AR724X_GPIO_FUNC_UART_EN BIT(1) 1029#define AR724X_GPIO_FUNC_JTAG_DISABLE BIT(0) 1030 1031#define AR913X_GPIO_FUNC_WMAC_LED_EN BIT(22) 1032#define AR913X_GPIO_FUNC_EXP_PORT_CS_EN BIT(21) 1033#define AR913X_GPIO_FUNC_I2S_REFCLKEN BIT(20) 1034#define AR913X_GPIO_FUNC_I2S_MCKEN BIT(19) 1035#define AR913X_GPIO_FUNC_I2S1_EN BIT(18) 1036#define AR913X_GPIO_FUNC_I2S0_EN BIT(17) 1037#define AR913X_GPIO_FUNC_SLIC_EN BIT(16) 1038#define AR913X_GPIO_FUNC_UART_RTSCTS_EN BIT(9) 1039#define AR913X_GPIO_FUNC_UART_EN BIT(8) 1040#define AR913X_GPIO_FUNC_USB_CLK_EN BIT(4) 1041 1042#define AR933X_GPIO(x) BIT(x) 1043#define AR933X_GPIO_FUNC_SPDIF2TCK BIT(31) 1044#define AR933X_GPIO_FUNC_SPDIF_EN BIT(30) 1045#define AR933X_GPIO_FUNC_I2SO_22_18_EN BIT(29) 1046#define AR933X_GPIO_FUNC_I2S_MCK_EN BIT(27) 1047#define AR933X_GPIO_FUNC_I2SO_EN BIT(26) 1048#define AR933X_GPIO_FUNC_ETH_SWITCH_LED_DUPL BIT(25) 1049#define AR933X_GPIO_FUNC_ETH_SWITCH_LED_COLL BIT(24) 1050#define AR933X_GPIO_FUNC_ETH_SWITCH_LED_ACT BIT(23) 1051#define AR933X_GPIO_FUNC_SPI_EN BIT(18) 1052#define AR933X_GPIO_FUNC_RES_TRUE BIT(15) 1053#define AR933X_GPIO_FUNC_SPI_CS_EN2 BIT(14) 1054#define AR933X_GPIO_FUNC_SPI_CS_EN1 BIT(13) 1055#define AR933X_GPIO_FUNC_XLNA_EN BIT(12) 1056#define AR933X_GPIO_FUNC_ETH_SWITCH_LED4_EN BIT(7) 1057#define AR933X_GPIO_FUNC_ETH_SWITCH_LED3_EN BIT(6) 1058#define AR933X_GPIO_FUNC_ETH_SWITCH_LED2_EN BIT(5) 1059#define AR933X_GPIO_FUNC_ETH_SWITCH_LED1_EN BIT(4) 1060#define AR933X_GPIO_FUNC_ETH_SWITCH_LED0_EN BIT(3) 1061#define AR933X_GPIO_FUNC_UART_RTS_CTS_EN BIT(2) 1062#define AR933X_GPIO_FUNC_UART_EN BIT(1) 1063#define AR933X_GPIO_FUNC_JTAG_DISABLE BIT(0) 1064 1065#define AR934X_GPIO_FUNC_CLK_OBS7_EN BIT(9) 1066#define AR934X_GPIO_FUNC_CLK_OBS6_EN BIT(8) 1067#define AR934X_GPIO_FUNC_CLK_OBS5_EN BIT(7) 1068#define AR934X_GPIO_FUNC_CLK_OBS4_EN BIT(6) 1069#define AR934X_GPIO_FUNC_CLK_OBS3_EN BIT(5) 1070#define AR934X_GPIO_FUNC_CLK_OBS2_EN BIT(4) 1071#define AR934X_GPIO_FUNC_CLK_OBS1_EN BIT(3) 1072#define AR934X_GPIO_FUNC_CLK_OBS0_EN BIT(2) 1073#define AR934X_GPIO_FUNC_JTAG_DISABLE BIT(1) 1074 1075#define AR934X_GPIO_OUT_GPIO 0 1076#define AR934X_GPIO_OUT_SPI_CS1 7 1077#define AR934X_GPIO_OUT_LED_LINK0 41 1078#define AR934X_GPIO_OUT_LED_LINK1 42 1079#define AR934X_GPIO_OUT_LED_LINK2 43 1080#define AR934X_GPIO_OUT_LED_LINK3 44 1081#define AR934X_GPIO_OUT_LED_LINK4 45 1082#define AR934X_GPIO_OUT_EXT_LNA0 46 1083#define AR934X_GPIO_OUT_EXT_LNA1 47 1084 1085#define QCA953X_GPIO(x) BIT(x) 1086#define QCA953X_GPIO_MUX_MASK(x) (0xff << (x)) 1087#define QCA953X_GPIO_OUT_MUX_SPI_CS1 10 1088#define QCA953X_GPIO_OUT_MUX_SPI_CS2 11 1089#define QCA953X_GPIO_OUT_MUX_SPI_CS0 9 1090#define QCA953X_GPIO_OUT_MUX_SPI_CLK 8 1091#define QCA953X_GPIO_OUT_MUX_SPI_MOSI 12 1092#define QCA953X_GPIO_OUT_MUX_UART0_SOUT 22 1093#define QCA953X_GPIO_OUT_MUX_LED_LINK1 41 1094#define QCA953X_GPIO_OUT_MUX_LED_LINK2 42 1095#define QCA953X_GPIO_OUT_MUX_LED_LINK3 43 1096#define QCA953X_GPIO_OUT_MUX_LED_LINK4 44 1097#define QCA953X_GPIO_OUT_MUX_LED_LINK5 45 1098 1099#define QCA953X_GPIO_IN_MUX_UART0_SIN 9 1100#define QCA953X_GPIO_IN_MUX_SPI_DATA_IN 8 1101 1102#define QCA956X_GPIO_OUT_MUX_GE0_MDO 32 1103#define QCA956X_GPIO_OUT_MUX_GE0_MDC 33 1104 1105#define AR71XX_GPIO_COUNT 16 1106#define AR7240_GPIO_COUNT 18 1107#define AR7241_GPIO_COUNT 20 1108#define AR913X_GPIO_COUNT 22 1109#define AR933X_GPIO_COUNT 30 1110#define AR934X_GPIO_COUNT 23 1111#define QCA953X_GPIO_COUNT 18 1112#define QCA955X_GPIO_COUNT 24 1113#define QCA956X_GPIO_COUNT 23 1114 1115/* 1116 * SRIF block 1117 */ 1118#define AR933X_SRIF_DDR_DPLL1_REG 0x240 1119#define AR933X_SRIF_DDR_DPLL2_REG 0x244 1120#define AR933X_SRIF_DDR_DPLL3_REG 0x248 1121#define AR933X_SRIF_DDR_DPLL4_REG 0x24c 1122 1123#define AR934X_SRIF_CPU_DPLL1_REG 0x1c0 1124#define AR934X_SRIF_CPU_DPLL2_REG 0x1c4 1125#define AR934X_SRIF_CPU_DPLL3_REG 0x1c8 1126#define AR934X_SRIF_CPU_DPLL4_REG 0x1cc 1127 1128#define AR934X_SRIF_DDR_DPLL1_REG 0x240 1129#define AR934X_SRIF_DDR_DPLL2_REG 0x244 1130#define AR934X_SRIF_DDR_DPLL3_REG 0x248 1131#define AR934X_SRIF_DDR_DPLL4_REG 0x24c 1132 1133#define AR934X_SRIF_DPLL1_REFDIV_SHIFT 27 1134#define AR934X_SRIF_DPLL1_REFDIV_MASK 0x1f 1135#define AR934X_SRIF_DPLL1_NINT_SHIFT 18 1136#define AR934X_SRIF_DPLL1_NINT_MASK 0x1ff 1137#define AR934X_SRIF_DPLL1_NFRAC_MASK 0x0003ffff 1138 1139#define AR934X_SRIF_DPLL2_LOCAL_PLL BIT(30) 1140#define AR934X_SRIF_DPLL2_OUTDIV_SHIFT 13 1141#define AR934X_SRIF_DPLL2_OUTDIV_MASK 0x7 1142 1143#define QCA953X_SRIF_BB_DPLL1_REG 0x180 1144#define QCA953X_SRIF_BB_DPLL2_REG 0x184 1145#define QCA953X_SRIF_BB_DPLL3_REG 0x188 1146 1147#define QCA953X_SRIF_CPU_DPLL1_REG 0x1c0 1148#define QCA953X_SRIF_CPU_DPLL2_REG 0x1c4 1149#define QCA953X_SRIF_CPU_DPLL3_REG 0x1c8 1150 1151#define QCA953X_SRIF_DDR_DPLL1_REG 0x240 1152#define QCA953X_SRIF_DDR_DPLL2_REG 0x244 1153#define QCA953X_SRIF_DDR_DPLL3_REG 0x248 1154 1155#define QCA953X_SRIF_PCIE_DPLL1_REG 0xc00 1156#define QCA953X_SRIF_PCIE_DPLL2_REG 0xc04 1157#define QCA953X_SRIF_PCIE_DPLL3_REG 0xc08 1158 1159#define QCA953X_SRIF_PMU1_REG 0xc40 1160#define QCA953X_SRIF_PMU2_REG 0xc44 1161 1162#define QCA953X_SRIF_DPLL1_REFDIV_SHIFT 27 1163#define QCA953X_SRIF_DPLL1_REFDIV_MASK 0x1f 1164 1165#define QCA953X_SRIF_DPLL1_NINT_SHIFT 18 1166#define QCA953X_SRIF_DPLL1_NINT_MASK 0x1ff 1167#define QCA953X_SRIF_DPLL1_NFRAC_MASK 0x0003ffff 1168 1169#define QCA953X_SRIF_DPLL2_LOCAL_PLL BIT(30) 1170 1171#define QCA953X_SRIF_DPLL2_KI_SHIFT 29 1172#define QCA953X_SRIF_DPLL2_KI_MASK 0x3 1173 1174#define QCA953X_SRIF_DPLL2_KD_SHIFT 25 1175#define QCA953X_SRIF_DPLL2_KD_MASK 0xf 1176 1177#define QCA953X_SRIF_DPLL2_PWD BIT(22) 1178 1179#define QCA953X_SRIF_DPLL2_OUTDIV_SHIFT 13 1180#define QCA953X_SRIF_DPLL2_OUTDIV_MASK 0x7 1181 1182/* 1183 * MII_CTRL block 1184 */ 1185#define AR71XX_MII_REG_MII0_CTRL 0x00 1186#define AR71XX_MII_REG_MII1_CTRL 0x04 1187 1188#define AR71XX_MII_CTRL_IF_MASK 3 1189#define AR71XX_MII_CTRL_SPEED_SHIFT 4 1190#define AR71XX_MII_CTRL_SPEED_MASK 3 1191#define AR71XX_MII_CTRL_SPEED_10 0 1192#define AR71XX_MII_CTRL_SPEED_100 1 1193#define AR71XX_MII_CTRL_SPEED_1000 2 1194 1195#define AR71XX_MII0_CTRL_IF_GMII 0 1196#define AR71XX_MII0_CTRL_IF_MII 1 1197#define AR71XX_MII0_CTRL_IF_RGMII 2 1198#define AR71XX_MII0_CTRL_IF_RMII 3 1199 1200#define AR71XX_MII1_CTRL_IF_RGMII 0 1201#define AR71XX_MII1_CTRL_IF_RMII 1 1202 1203/* 1204 * AR933X GMAC interface 1205 */ 1206#define AR933X_GMAC_REG_ETH_CFG 0x00 1207 1208#define AR933X_ETH_CFG_RGMII_GE0 BIT(0) 1209#define AR933X_ETH_CFG_MII_GE0 BIT(1) 1210#define AR933X_ETH_CFG_GMII_GE0 BIT(2) 1211#define AR933X_ETH_CFG_MII_GE0_MASTER BIT(3) 1212#define AR933X_ETH_CFG_MII_GE0_SLAVE BIT(4) 1213#define AR933X_ETH_CFG_MII_GE0_ERR_EN BIT(5) 1214#define AR933X_ETH_CFG_SW_PHY_SWAP BIT(7) 1215#define AR933X_ETH_CFG_SW_PHY_ADDR_SWAP BIT(8) 1216#define AR933X_ETH_CFG_RMII_GE0 BIT(9) 1217#define AR933X_ETH_CFG_RMII_GE0_SPD_10 0 1218#define AR933X_ETH_CFG_RMII_GE0_SPD_100 BIT(10) 1219 1220/* 1221 * AR934X GMAC Interface 1222 */ 1223#define AR934X_GMAC_REG_ETH_CFG 0x00 1224 1225#define AR934X_ETH_CFG_RGMII_GMAC0 BIT(0) 1226#define AR934X_ETH_CFG_MII_GMAC0 BIT(1) 1227#define AR934X_ETH_CFG_GMII_GMAC0 BIT(2) 1228#define AR934X_ETH_CFG_MII_GMAC0_MASTER BIT(3) 1229#define AR934X_ETH_CFG_MII_GMAC0_SLAVE BIT(4) 1230#define AR934X_ETH_CFG_MII_GMAC0_ERR_EN BIT(5) 1231#define AR934X_ETH_CFG_SW_ONLY_MODE BIT(6) 1232#define AR934X_ETH_CFG_SW_PHY_SWAP BIT(7) 1233#define AR934X_ETH_CFG_SW_APB_ACCESS BIT(9) 1234#define AR934X_ETH_CFG_RMII_GMAC0 BIT(10) 1235#define AR933X_ETH_CFG_MII_CNTL_SPEED BIT(11) 1236#define AR934X_ETH_CFG_RMII_GMAC0_MASTER BIT(12) 1237#define AR933X_ETH_CFG_SW_ACC_MSB_FIRST BIT(13) 1238#define AR934X_ETH_CFG_RXD_DELAY BIT(14) 1239#define AR934X_ETH_CFG_RXD_DELAY_MASK 0x3 1240#define AR934X_ETH_CFG_RXD_DELAY_SHIFT 14 1241#define AR934X_ETH_CFG_RDV_DELAY BIT(16) 1242#define AR934X_ETH_CFG_RDV_DELAY_MASK 0x3 1243#define AR934X_ETH_CFG_RDV_DELAY_SHIFT 16 1244 1245/* 1246 * QCA953X GMAC Interface 1247 */ 1248#define QCA953X_GMAC_REG_ETH_CFG 0x00 1249 1250#define QCA953X_ETH_CFG_SW_ONLY_MODE BIT(6) 1251#define QCA953X_ETH_CFG_SW_PHY_SWAP BIT(7) 1252#define QCA953X_ETH_CFG_SW_APB_ACCESS BIT(9) 1253#define QCA953X_ETH_CFG_SW_ACC_MSB_FIRST BIT(13) 1254 1255/* 1256 * QCA955X GMAC Interface 1257 */ 1258 1259#define QCA955X_GMAC_REG_ETH_CFG 0x00 1260 1261#define QCA955X_ETH_CFG_RGMII_EN BIT(0) 1262#define QCA955X_ETH_CFG_GE0_SGMII BIT(6) 1263 1264#endif /* __ASM_AR71XX_H */ 1265