LXR uboot/board/barco/platinum/platinum

   1// SPDX-License-Identifier: GPL-2.0+
   2/*
   3 * Copyright (C) 2014, Barco (www.barco.com)
   4 * Copyright (C) 2014 Stefan Roese <sr@denx.de>
   5 */
   6
   7#include <common.h>
   8#include <asm/gpio.h>
   9#include <asm/io.h>
  10#include <asm/arch/clock.h>
  11#include <asm/arch/iomux.h>
  12#include <asm/arch/mx6-pins.h>
  13#include <asm/mach-imx/iomux-v3.h>
  14#include <asm/mach-imx/mxc_i2c.h>
  15#include <i2c.h>
  16#include <miiphy.h>
  17
  18#include "platinum.h"
  19
  20#define GPIO_IP_NCONFIG         IMX_GPIO_NR(5, 18)
  21#define GPIO_HK_NCONFIG         IMX_GPIO_NR(7, 13)
  22#define GPIO_LS_NCONFIG         IMX_GPIO_NR(5, 19)
  23
  24#define GPIO_I2C0_SEL0          IMX_GPIO_NR(5,  2)
  25#define GPIO_I2C0_SEL1          IMX_GPIO_NR(1, 11)
  26#define GPIO_I2C0_ENBN          IMX_GPIO_NR(1, 13)
  27
  28#define GPIO_I2C2_SEL0          IMX_GPIO_NR(1, 17)
  29#define GPIO_I2C2_SEL1          IMX_GPIO_NR(1, 20)
  30#define GPIO_I2C2_ENBN          IMX_GPIO_NR(1, 14)
  31
  32#define GPIO_USB_RESET          IMX_GPIO_NR(1,  5)
  33
  34iomux_v3_cfg_t const ecspi1_pads[] = {
  35        MX6_PAD_EIM_D16__ECSPI1_SCLK            | MUX_PAD_CTRL(ECSPI1_PAD_CLK),
  36        MX6_PAD_EIM_D17__ECSPI1_MISO            | MUX_PAD_CTRL(ECSPI_PAD_MISO),
  37        MX6_PAD_EIM_D18__ECSPI1_MOSI            | MUX_PAD_CTRL(ECSPI_PAD_MOSI),
  38        MX6_PAD_CSI0_DAT7__ECSPI1_SS0           | MUX_PAD_CTRL(ECSPI_PAD_SS),
  39        MX6_PAD_EIM_D24__ECSPI1_SS2             | MUX_PAD_CTRL(ECSPI_PAD_SS),
  40        MX6_PAD_EIM_D25__ECSPI1_SS3             | MUX_PAD_CTRL(ECSPI_PAD_SS),
  41};
  42
  43iomux_v3_cfg_t const ecspi2_pads[] = {
  44        MX6_PAD_EIM_CS0__ECSPI2_SCLK            | MUX_PAD_CTRL(ECSPI2_PAD_CLK),
  45        MX6_PAD_EIM_OE__ECSPI2_MISO             | MUX_PAD_CTRL(ECSPI_PAD_MISO),
  46        MX6_PAD_EIM_CS1__ECSPI2_MOSI            | MUX_PAD_CTRL(ECSPI_PAD_MOSI),
  47        MX6_PAD_EIM_RW__ECSPI2_SS0              | MUX_PAD_CTRL(ECSPI_PAD_SS),
  48        MX6_PAD_EIM_LBA__ECSPI2_SS1             | MUX_PAD_CTRL(ECSPI_PAD_SS),
  49};
  50
  51iomux_v3_cfg_t const enet_pads[] = {
  52        MX6_PAD_ENET_MDIO__ENET_MDIO            | MUX_PAD_CTRL(ENET_PAD_CTRL),
  53        MX6_PAD_ENET_MDC__ENET_MDC              | MUX_PAD_CTRL(ENET_PAD_CTRL),
  54        MX6_PAD_ENET_CRS_DV__ENET_RX_EN         | MUX_PAD_CTRL(ENET_PAD_CTRL),
  55        MX6_PAD_GPIO_16__ENET_REF_CLK           | MUX_PAD_CTRL(ENET_PAD_CTRL),
  56        MX6_PAD_ENET_RX_ER__ENET_RX_ER          | MUX_PAD_CTRL(ENET_PAD_CTRL),
  57        MX6_PAD_ENET_RXD0__ENET_RX_DATA0        | MUX_PAD_CTRL(ENET_PAD_CTRL),
  58        MX6_PAD_ENET_RXD1__ENET_RX_DATA1        | MUX_PAD_CTRL(ENET_PAD_CTRL),
  59        MX6_PAD_ENET_TX_EN__ENET_TX_EN          | MUX_PAD_CTRL(ENET_PAD_CTRL),
  60        MX6_PAD_ENET_TXD0__ENET_TX_DATA0        | MUX_PAD_CTRL(ENET_PAD_CTRL),
  61        MX6_PAD_ENET_TXD1__ENET_TX_DATA1        | MUX_PAD_CTRL(ENET_PAD_CTRL),
  62};
  63
  64/* PHY nRESET */
  65iomux_v3_cfg_t const phy_reset_pad = {
  66        MX6_PAD_SD1_DAT2__GPIO1_IO19            | MUX_PAD_CTRL(NO_PAD_CTRL),
  67};
  68
  69iomux_v3_cfg_t const uart1_pads[] = {
  70        MX6_PAD_SD3_DAT6__UART1_RX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL),
  71        MX6_PAD_SD3_DAT7__UART1_TX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL),
  72};
  73
  74iomux_v3_cfg_t const uart4_pads[] = {
  75        MX6_PAD_CSI0_DAT12__UART4_TX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL),
  76        MX6_PAD_CSI0_DAT13__UART4_RX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL),
  77        MX6_PAD_CSI0_DAT16__UART4_RTS_B   | MUX_PAD_CTRL(UART_PAD_CTRL),
  78        MX6_PAD_CSI0_DAT17__UART4_CTS_B   | MUX_PAD_CTRL(UART_PAD_CTRL),
  79};
  80
  81iomux_v3_cfg_t const uart5_pads[] = {
  82        MX6_PAD_CSI0_DAT14__UART5_TX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL),
  83        MX6_PAD_CSI0_DAT15__UART5_RX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL),
  84        MX6_PAD_CSI0_DAT18__UART5_RTS_B   | MUX_PAD_CTRL(UART_PAD_CTRL),
  85        MX6_PAD_CSI0_DAT19__UART5_CTS_B   | MUX_PAD_CTRL(UART_PAD_CTRL),
  86};
  87
  88iomux_v3_cfg_t const i2c0_mux_pads[] = {
  89        MX6_PAD_EIM_A25__GPIO5_IO02             | MUX_PAD_CTRL(NO_PAD_CTRL),
  90        MX6_PAD_SD2_CMD__GPIO1_IO11             | MUX_PAD_CTRL(NO_PAD_CTRL),
  91        MX6_PAD_SD2_DAT2__GPIO1_IO13            | MUX_PAD_CTRL(NO_PAD_CTRL),
  92};
  93
  94iomux_v3_cfg_t const i2c2_mux_pads[] = {
  95        MX6_PAD_SD1_DAT1__GPIO1_IO17            | MUX_PAD_CTRL(NO_PAD_CTRL),
  96        MX6_PAD_SD1_CLK__GPIO1_IO20             | MUX_PAD_CTRL(NO_PAD_CTRL),
  97        MX6_PAD_SD2_DAT1__GPIO1_IO14            | MUX_PAD_CTRL(NO_PAD_CTRL),
  98};
  99
 100struct i2c_pads_info i2c_pad_info0 = {
 101        .scl = {
 102                .i2c_mode  = MX6_PAD_CSI0_DAT9__I2C1_SCL        | PC_SCL,
 103                .gpio_mode = MX6_PAD_CSI0_DAT9__GPIO5_IO27      | PC_SCL,
 104                .gp = IMX_GPIO_NR(5, 27)
 105        },
 106        .sda = {
 107                .i2c_mode = MX6_PAD_CSI0_DAT8__I2C1_SDA         | PC,
 108                .gpio_mode = MX6_PAD_CSI0_DAT8__GPIO5_IO26      | PC,
 109                .gp = IMX_GPIO_NR(5, 26)
 110         }
 111};
 112
 113struct i2c_pads_info i2c_pad_info2 = {
 114        .scl = {
 115                .i2c_mode = MX6_PAD_GPIO_3__I2C3_SCL            | PC_SCL,
 116                .gpio_mode = MX6_PAD_GPIO_3__GPIO1_IO03         | PC_SCL,
 117                .gp = IMX_GPIO_NR(1, 3)
 118        },
 119        .sda = {
 120                .i2c_mode = MX6_PAD_GPIO_6__I2C3_SDA            | PC,
 121                .gpio_mode = MX6_PAD_GPIO_6__GPIO1_IO06         | PC,
 122                .gp = IMX_GPIO_NR(1, 6)
 123         }
 124};
 125
 126/*
 127 * This enet related pin-muxing and GPIO handling is done
 128 * in SPL U-Boot. For early initialization. And to give the
 129 * PHY some time to come out of reset before the U-Boot
 130 * ethernet driver tries to access its registers via MDIO.
 131 */
 132int platinum_setup_enet(void)
 133{
 134        struct iomuxc *iomux = (struct iomuxc *)IOMUXC_BASE_ADDR;
 135        unsigned phy_reset = IMX_GPIO_NR(1, 19);
 136
 137        /* First configure PHY reset GPIO pin */
 138        imx_iomux_v3_setup_pad(phy_reset_pad);
 139
 140        /* Reconfigure enet muxing while PHY is in reset */
 141        gpio_direction_output(phy_reset, 0);
 142        imx_iomux_v3_setup_multiple_pads(enet_pads, ARRAY_SIZE(enet_pads));
 143        mdelay(10);
 144        gpio_set_value(phy_reset, 1);
 145        udelay(100);
 146
 147        /* set GPIO_16 as ENET_REF_CLK_OUT */
 148        setbits_le32(&iomux->gpr[1], IOMUXC_GPR1_ENET_CLK_SEL_MASK);
 149
 150        return enable_fec_anatop_clock(0, ENET_50MHZ);
 151}
 152
 153int platinum_setup_i2c(void)
 154{
 155        imx_iomux_v3_setup_multiple_pads(i2c0_mux_pads,
 156                                         ARRAY_SIZE(i2c0_mux_pads));
 157        imx_iomux_v3_setup_multiple_pads(i2c2_mux_pads,
 158                                         ARRAY_SIZE(i2c2_mux_pads));
 159
 160        mdelay(10);
 161
 162        /* Disable i2c mux 0 */
 163        gpio_direction_output(GPIO_I2C0_SEL0, 0);
 164        gpio_direction_output(GPIO_I2C0_SEL1, 0);
 165        gpio_direction_output(GPIO_I2C0_ENBN, 1);
 166
 167        /* Disable i2c mux 1 */
 168        gpio_direction_output(GPIO_I2C2_SEL0, 0);
 169        gpio_direction_output(GPIO_I2C2_SEL1, 0);
 170        gpio_direction_output(GPIO_I2C2_ENBN, 1);
 171
 172        udelay(10);
 173
 174        setup_i2c(0, CONFIG_SYS_I2C_SPEED, 0x7f, &i2c_pad_info0);
 175        setup_i2c(2, CONFIG_SYS_I2C_SPEED, 0x7f, &i2c_pad_info2);
 176
 177        /* Disable all leds */
 178        i2c_set_bus_num(0);
 179        i2c_reg_write(0x60, 0x05, 0x55);
 180
 181        return 0;
 182}
 183
 184int platinum_setup_spi(void)
 185{
 186        imx_iomux_v3_setup_multiple_pads(ecspi1_pads, ARRAY_SIZE(ecspi1_pads));
 187        imx_iomux_v3_setup_multiple_pads(ecspi2_pads, ARRAY_SIZE(ecspi2_pads));
 188
 189        return 0;
 190}
 191
 192int platinum_setup_uart(void)
 193{
 194        imx_iomux_v3_setup_multiple_pads(uart1_pads, ARRAY_SIZE(uart1_pads));
 195        imx_iomux_v3_setup_multiple_pads(uart4_pads, ARRAY_SIZE(uart4_pads));
 196        imx_iomux_v3_setup_multiple_pads(uart5_pads, ARRAY_SIZE(uart5_pads));
 197
 198        return 0;
 199}
 200
 201int platinum_phy_config(struct phy_device *phydev)
 202{
 203        /* Use generic infrastructure, no specific setup */
 204        if (phydev->drv->config)
 205                phydev->drv->config(phydev);
 206
 207        return 0;
 208}
 209
 210int platinum_init_gpio(void)
 211{
 212        /* Reset FPGA's */
 213        gpio_direction_output(GPIO_IP_NCONFIG, 0);
 214        gpio_direction_output(GPIO_HK_NCONFIG, 0);
 215        gpio_direction_output(GPIO_LS_NCONFIG, 0);
 216        udelay(3);
 217        gpio_set_value(GPIO_IP_NCONFIG, 1);
 218        gpio_set_value(GPIO_HK_NCONFIG, 1);
 219        gpio_set_value(GPIO_LS_NCONFIG, 1);
 220
 221        /* no dmd configuration yet */
 222
 223        return 0;
 224}
 225
 226int platinum_init_usb(void)
 227{
 228        /* Reset usb hub */
 229        gpio_direction_output(GPIO_USB_RESET, 0);
 230        udelay(100);
 231        gpio_set_value(GPIO_USB_RESET, 1);
 232
 233        return 0;
 234}
 235
 236int platinum_init_finished(void)
 237{
 238        /* Enable led 0 */
 239        i2c_set_bus_num(0);
 240        i2c_reg_write(0x60, 0x05, 0x54);
 241
 242        return 0;
 243}
 244