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8#include <common.h>
9#include <malloc.h>
10#include <dm/platform_data/serial_sh.h>
11#include <asm/processor.h>
12#include <asm/mach-types.h>
13#include <asm/io.h>
14#include <linux/errno.h>
15#include <asm/arch/sys_proto.h>
16#include <asm/gpio.h>
17#include <asm/arch/rmobile.h>
18#include <asm/arch/rcar-mstp.h>
19
20#include <spl.h>
21
22#define TMU0_MSTP125 BIT(25)
23#define SCIF2_MSTP719 BIT(19)
24#define QSPI_MSTP917 BIT(17)
25
26#define SD1CKCR 0xE6150078
27#define SD_97500KHZ 0x7
28
29struct reg_config {
30 u16 off;
31 u32 val;
32};
33
34static void dbsc_wait(u16 reg)
35{
36 static const u32 dbsc3_0_base = DBSC3_0_BASE;
37
38 while (!(readl(dbsc3_0_base + reg) & BIT(0)))
39 ;
40}
41
42static void spl_init_sys(void)
43{
44 u32 r0 = 0;
45
46 writel(0xa5a5a500, 0xe6020004);
47 writel(0xa5a5a500, 0xe6030004);
48
49 asm volatile(
50
51 "mcr 15, 0, %0, cr7, cr5, 0 \n"
52
53 "mcr 15, 0, %0, cr7, cr5, 6 \n"
54
55 "mrc 15, 0, %0, cr1, cr0, 0 \n"
56 "orr %0, #0x1800 \n"
57 "mcr 15, 0, %0, cr1, cr0, 0 \n"
58 "isb sy \n"
59 :"=r"(r0));
60}
61
62static void spl_init_pfc(void)
63{
64 static const struct reg_config pfc_with_unlock[] = {
65 { 0x0090, 0x00018040 },
66 { 0x0094, 0x00000000 },
67 { 0x0098, 0x00000000 },
68 { 0x0020, 0x94000000 },
69 { 0x0024, 0x00000006 },
70 { 0x0028, 0x40000000 },
71 { 0x002c, 0x00000155 },
72 { 0x0030, 0x00000002 },
73 { 0x0034, 0x00000000 },
74 { 0x0038, 0x00000000 },
75 { 0x003c, 0x00000000 },
76 { 0x0040, 0x60000000 },
77 { 0x0044, 0x36dab6db },
78 { 0x0048, 0x926da012 },
79 { 0x004c, 0x0008c383 },
80 { 0x0050, 0x00000000 },
81 { 0x0054, 0x00000140 },
82 { 0x0004, 0xffffffff },
83 { 0x0008, 0x00ec3fff },
84 { 0x000c, 0x5bffffff },
85 { 0x0010, 0x01bfe1ff },
86 { 0x0014, 0x5bffffff },
87 { 0x0018, 0x0f4b200f },
88 { 0x001c, 0x03ffffff },
89 };
90
91 static const struct reg_config pfc_without_unlock[] = {
92 { 0x0100, 0x00000000 },
93 { 0x0104, 0x4203fdf0 },
94 { 0x0108, 0x00000000 },
95 { 0x010c, 0x159007ff },
96 { 0x0110, 0x80000000 },
97 { 0x0114, 0x00de481f },
98 { 0x0118, 0x00000000 },
99 };
100
101 static const struct reg_config pfc_with_unlock2[] = {
102 { 0x0060, 0xffffffff },
103 { 0x0064, 0xfffff000 },
104 { 0x0068, 0x55555500 },
105 { 0x006c, 0xffffff00 },
106 { 0x0070, 0x00000000 },
107 };
108
109 static const u32 pfc_base = 0xe6060000;
110
111 unsigned int i;
112
113 for (i = 0; i < ARRAY_SIZE(pfc_with_unlock); i++) {
114 writel(~pfc_with_unlock[i].val, pfc_base);
115 writel(pfc_with_unlock[i].val,
116 pfc_base | pfc_with_unlock[i].off);
117 }
118
119 for (i = 0; i < ARRAY_SIZE(pfc_without_unlock); i++)
120 writel(pfc_without_unlock[i].val,
121 pfc_base | pfc_without_unlock[i].off);
122
123 for (i = 0; i < ARRAY_SIZE(pfc_with_unlock2); i++) {
124 writel(~pfc_with_unlock2[i].val, pfc_base);
125 writel(pfc_with_unlock2[i].val,
126 pfc_base | pfc_with_unlock2[i].off);
127 }
128}
129
130static void spl_init_gpio(void)
131{
132 static const u16 gpio_offs[] = {
133 0x1000, 0x2000, 0x3000, 0x4000
134 };
135
136 static const struct reg_config gpio_set[] = {
137 { 0x2000, 0x24000000 },
138 { 0x4000, 0xa4000000 },
139 { 0x5000, 0x0084c000 },
140 };
141
142 static const struct reg_config gpio_clr[] = {
143 { 0x1000, 0x01000000 },
144 { 0x2000, 0x24000000 },
145 { 0x3000, 0x00000000 },
146 { 0x4000, 0xa4000000 },
147 { 0x5000, 0x00044380 },
148 };
149
150 static const u32 gpio_base = 0xe6050000;
151
152 unsigned int i;
153
154 for (i = 0; i < ARRAY_SIZE(gpio_offs); i++)
155 writel(0, gpio_base | 0x20 | gpio_offs[i]);
156 writel(BIT(23), gpio_base | 0x5020);
157
158 for (i = 0; i < ARRAY_SIZE(gpio_offs); i++)
159 writel(0, gpio_base | 0x00 | gpio_offs[i]);
160 writel(BIT(23), gpio_base | 0x5000);
161
162 for (i = 0; i < ARRAY_SIZE(gpio_set); i++)
163 writel(gpio_set[i].val, gpio_base | 0x08 | gpio_set[i].off);
164
165 for (i = 0; i < ARRAY_SIZE(gpio_clr); i++)
166 writel(gpio_clr[i].val, gpio_base | 0x04 | gpio_clr[i].off);
167}
168
169static void spl_init_lbsc(void)
170{
171 static const struct reg_config lbsc_config[] = {
172 { 0x00, 0x00000020 },
173 { 0x08, 0x00002020 },
174 { 0x30, 0x2a103320 },
175 { 0x38, 0xff70ff70 },
176 };
177
178 static const u16 lbsc_offs[] = {
179 0x80, 0x84, 0x88, 0x8c, 0xa0, 0xc0, 0xc4, 0xc8
180 };
181
182 static const u32 lbsc_base = 0xfec00200;
183
184 unsigned int i;
185
186 for (i = 0; i < ARRAY_SIZE(lbsc_config); i++) {
187 writel(lbsc_config[i].val,
188 lbsc_base | lbsc_config[i].off);
189 writel(lbsc_config[i].val,
190 lbsc_base | (lbsc_config[i].off + 4));
191 }
192
193 for (i = 0; i < ARRAY_SIZE(lbsc_offs); i++)
194 writel(0, lbsc_base | lbsc_offs[i]);
195}
196
197static void spl_init_dbsc(void)
198{
199 static const struct reg_config dbsc_config1[] = {
200 { 0x0018, 0x21000000 },
201 { 0x0018, 0x11000000 },
202 { 0x0018, 0x10000000 },
203 { 0x0280, 0x0000a55a },
204 { 0x0290, 0x00000001 },
205 { 0x02a0, 0x80000000 },
206 { 0x0290, 0x00000004 },
207 };
208
209 static const struct reg_config dbsc_config2[] = {
210 { 0x0290, 0x00000006 },
211 { 0x02a0, 0x0005c000 },
212 };
213
214 static const struct reg_config dbsc_config3r2[] = {
215 { 0x0290, 0x0000000f },
216 { 0x02a0, 0x00181224 },
217 };
218
219 static const struct reg_config dbsc_config4[] = {
220 { 0x0290, 0x00000010 },
221 { 0x02a0, 0xf004649b },
222 { 0x0290, 0x00000061 },
223 { 0x02a0, 0x0000006d },
224 { 0x0290, 0x00000001 },
225 { 0x02a0, 0x00000073 },
226 { 0x0020, 0x00000007 },
227 { 0x0024, 0x0f030a02 },
228 { 0x0030, 0x00000001 },
229 { 0x00b0, 0x00000000 },
230 { 0x0040, 0x00000009 },
231 { 0x0044, 0x00000007 },
232 { 0x0048, 0x00000000 },
233 { 0x0050, 0x00000009 },
234 { 0x0054, 0x000a0009 },
235 { 0x0058, 0x00000021 },
236 { 0x005c, 0x00000018 },
237 { 0x0060, 0x00000005 },
238 { 0x0064, 0x00000020 },
239 { 0x0068, 0x00000007 },
240 { 0x006c, 0x0000000a },
241 { 0x0070, 0x00000009 },
242 { 0x0074, 0x00000010 },
243 { 0x0078, 0x000000ae },
244 { 0x007c, 0x00140005 },
245 { 0x0080, 0x00050004 },
246 { 0x0084, 0x50213005 },
247 { 0x0088, 0x000c0000 },
248 { 0x008c, 0x00000200 },
249 { 0x0090, 0x00000040 },
250 { 0x0100, 0x00000001 },
251 { 0x00c0, 0x00020001 },
252 { 0x00c8, 0x20042004 },
253 { 0x0380, 0x00020003 },
254 { 0x0390, 0x0000001f },
255 };
256
257 static const struct reg_config dbsc_config5[] = {
258 { 0x0244, 0x00000011 },
259 { 0x0290, 0x00000003 },
260 { 0x02a0, 0x0300c4e1 },
261 { 0x0290, 0x00000023 },
262 { 0x02a0, 0x00fcb6d0 },
263 { 0x0290, 0x00000011 },
264 { 0x02a0, 0x1000040b },
265 { 0x0290, 0x00000012 },
266 { 0x02a0, 0x85589955 },
267 { 0x0290, 0x00000013 },
268 { 0x02a0, 0x1a852400 },
269 { 0x0290, 0x00000014 },
270 { 0x02a0, 0x300210b4 },
271 { 0x0290, 0x00000015 },
272 { 0x02a0, 0x00000b50 },
273 { 0x0290, 0x00000016 },
274 { 0x02a0, 0x00000006 },
275 { 0x0290, 0x00000017 },
276 { 0x02a0, 0x00000010 },
277 { 0x0290, 0x0000001a },
278 { 0x02a0, 0x910035c7 },
279 { 0x0290, 0x00000004 },
280 };
281
282 static const struct reg_config dbsc_config6[] = {
283 { 0x0290, 0x00000001 },
284 { 0x02a0, 0x00000181 },
285 { 0x0018, 0x11000000 },
286 { 0x0290, 0x00000004 },
287 };
288
289 static const struct reg_config dbsc_config7[] = {
290 { 0x0290, 0x00000001 },
291 { 0x02a0, 0x0000fe01 },
292 { 0x0304, 0x00000000 },
293 { 0x00f4, 0x01004c20 },
294 { 0x00f8, 0x012c00be },
295 { 0x00e0, 0x00000140 },
296 { 0x00e4, 0x00081450 },
297 { 0x00e8, 0x00010000 },
298 { 0x0290, 0x00000004 },
299 };
300
301 static const struct reg_config dbsc_config8[] = {
302 { 0x0014, 0x00000001 },
303 { 0x0290, 0x00000010 },
304 { 0x02a0, 0xf00464db },
305 { 0x0010, 0x00000001 },
306 { 0x0280, 0x00000000 },
307 };
308
309 static const u32 dbsc3_0_base = DBSC3_0_BASE;
310 unsigned int i;
311
312 for (i = 0; i < ARRAY_SIZE(dbsc_config1); i++)
313 writel(dbsc_config1[i].val, dbsc3_0_base | dbsc_config1[i].off);
314
315 dbsc_wait(0x2a0);
316
317 for (i = 0; i < ARRAY_SIZE(dbsc_config2); i++)
318 writel(dbsc_config2[i].val, dbsc3_0_base | dbsc_config2[i].off);
319
320 for (i = 0; i < ARRAY_SIZE(dbsc_config3r2); i++) {
321 writel(dbsc_config3r2[i].val,
322 dbsc3_0_base | dbsc_config3r2[i].off);
323 }
324
325 for (i = 0; i < ARRAY_SIZE(dbsc_config4); i++)
326 writel(dbsc_config4[i].val, dbsc3_0_base | dbsc_config4[i].off);
327
328 dbsc_wait(0x240);
329
330 for (i = 0; i < ARRAY_SIZE(dbsc_config5); i++)
331 writel(dbsc_config5[i].val, dbsc3_0_base | dbsc_config5[i].off);
332
333 dbsc_wait(0x2a0);
334
335 for (i = 0; i < ARRAY_SIZE(dbsc_config6); i++)
336 writel(dbsc_config6[i].val, dbsc3_0_base | dbsc_config6[i].off);
337
338 dbsc_wait(0x2a0);
339
340 for (i = 0; i < ARRAY_SIZE(dbsc_config7); i++)
341 writel(dbsc_config7[i].val, dbsc3_0_base | dbsc_config7[i].off);
342
343 dbsc_wait(0x2a0);
344
345 for (i = 0; i < ARRAY_SIZE(dbsc_config8); i++)
346 writel(dbsc_config8[i].val, dbsc3_0_base | dbsc_config8[i].off);
347
348}
349
350static void spl_init_qspi(void)
351{
352 mstp_clrbits_le32(MSTPSR9, SMSTPCR9, QSPI_MSTP917);
353
354 static const u32 qspi_base = 0xe6b10000;
355
356 writeb(0x08, qspi_base + 0x00);
357 writeb(0x00, qspi_base + 0x01);
358 writeb(0x06, qspi_base + 0x02);
359 writeb(0x01, qspi_base + 0x0a);
360 writeb(0x00, qspi_base + 0x0b);
361 writeb(0x00, qspi_base + 0x0c);
362 writeb(0x00, qspi_base + 0x0d);
363 writeb(0x00, qspi_base + 0x0e);
364
365 writew(0xe080, qspi_base + 0x10);
366
367 writeb(0xc0, qspi_base + 0x18);
368 writeb(0x00, qspi_base + 0x18);
369 writeb(0x00, qspi_base + 0x08);
370 writeb(0x48, qspi_base + 0x00);
371}
372
373void board_init_f(ulong dummy)
374{
375 mstp_clrbits_le32(MSTPSR1, SMSTPCR1, TMU0_MSTP125);
376 mstp_clrbits_le32(MSTPSR7, SMSTPCR7, SCIF2_MSTP719);
377
378
379 writel(SD_97500KHZ, SD1CKCR);
380
381 spl_init_sys();
382 spl_init_pfc();
383 spl_init_gpio();
384 spl_init_lbsc();
385 spl_init_dbsc();
386 spl_init_qspi();
387}
388
389void spl_board_init(void)
390{
391
392 preloader_console_init();
393}
394
395void board_boot_order(u32 *spl_boot_list)
396{
397 const u32 jtag_magic = 0x1337c0de;
398 const u32 load_magic = 0xb33fc0de;
399
400
401
402
403
404 if (readl(CONFIG_SPL_TEXT_BASE + 0x20) == jtag_magic) {
405 printf("JTAG boot detected!\n");
406
407 while (readl(CONFIG_SPL_TEXT_BASE + 0x24) != load_magic)
408 ;
409
410 spl_boot_list[0] = BOOT_DEVICE_RAM;
411 spl_boot_list[1] = BOOT_DEVICE_NONE;
412
413 return;
414 }
415
416
417 spl_boot_list[0] = BOOT_DEVICE_SPI;
418 spl_boot_list[1] = BOOT_DEVICE_UART;
419 spl_boot_list[2] = BOOT_DEVICE_NONE;
420}
421
422void reset_cpu(ulong addr)
423{
424}
425
