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7#ifndef SATA_SIL3132_H
8#define SATA_SIL3132_H
9
10#define READ_CMD 0
11#define WRITE_CMD 1
12
13
14
15
16struct sil_sata {
17 char name[12];
18 void *port;
19 int lba48;
20 u16 pio;
21 u16 mwdma;
22 u16 udma;
23 pci_dev_t devno;
24 int wcache;
25 int flush;
26 int flush_ext;
27};
28
29
30struct sata_info {
31 ulong iobase[3];
32 pci_dev_t devno;
33 int portbase;
34 int maxport;
35};
36
37
38
39
40struct sil_sge {
41 __le64 addr;
42 __le32 cnt;
43 __le32 flags;
44} __attribute__ ((aligned(8), packed));
45
46
47
48
49struct sil_prb {
50 __le16 ctrl;
51 __le16 prot;
52 __le32 rx_cnt;
53 struct sata_fis_h2d fis;
54} __attribute__ ((aligned(8), packed));
55
56struct sil_cmd_block {
57 struct sil_prb prb;
58 struct sil_sge sge;
59};
60
61enum {
62 HOST_SLOT_STAT = 0x00,
63 HOST_CTRL = 0x40,
64 HOST_IRQ_STAT = 0x44,
65 HOST_PHY_CFG = 0x48,
66 HOST_BIST_CTRL = 0x50,
67 HOST_BIST_PTRN = 0x54,
68 HOST_BIST_STAT = 0x58,
69 HOST_MEM_BIST_STAT = 0x5c,
70 HOST_FLASH_CMD = 0x70,
71
72 HOST_FLASH_DATA = 0x74,
73 HOST_TRANSITION_DETECT = 0x75,
74 HOST_GPIO_CTRL = 0x76,
75 HOST_I2C_ADDR = 0x78,
76 HOST_I2C_DATA = 0x7c,
77 HOST_I2C_XFER_CNT = 0x7e,
78 HOST_I2C_CTRL = 0x7f,
79
80
81 HOST_SSTAT_ATTN = (1 << 31),
82
83
84 HOST_CTRL_M66EN = (1 << 16),
85 HOST_CTRL_TRDY = (1 << 17),
86 HOST_CTRL_STOP = (1 << 18),
87 HOST_CTRL_DEVSEL = (1 << 19),
88 HOST_CTRL_REQ64 = (1 << 20),
89 HOST_CTRL_GLOBAL_RST = (1 << 31),
90
91
92
93
94
95 PORT_REGS_SIZE = 0x2000,
96
97 PORT_LRAM = 0x0000,
98 PORT_LRAM_SLOT_SZ = 0x0080,
99
100 PORT_PMP = 0x0f80,
101 PORT_PMP_STATUS = 0x0000,
102 PORT_PMP_QACTIVE = 0x0004,
103 PORT_PMP_SIZE = 0x0008,
104
105
106 PORT_CTRL_STAT = 0x1000,
107 PORT_CTRL_CLR = 0x1004,
108 PORT_IRQ_STAT = 0x1008,
109 PORT_IRQ_ENABLE_SET = 0x1010,
110 PORT_IRQ_ENABLE_CLR = 0x1014,
111 PORT_ACTIVATE_UPPER_ADDR = 0x101c,
112 PORT_EXEC_FIFO = 0x1020,
113 PORT_CMD_ERR = 0x1024,
114 PORT_FIS_CFG = 0x1028,
115 PORT_FIFO_THRES = 0x102c,
116
117
118 PORT_DECODE_ERR_CNT = 0x1040,
119 PORT_DECODE_ERR_THRESH = 0x1042,
120 PORT_CRC_ERR_CNT = 0x1044,
121 PORT_CRC_ERR_THRESH = 0x1046,
122 PORT_HSHK_ERR_CNT = 0x1048,
123 PORT_HSHK_ERR_THRESH = 0x104a,
124
125
126 PORT_PHY_CFG = 0x1050,
127 PORT_SLOT_STAT = 0x1800,
128 PORT_CMD_ACTIVATE = 0x1c00,
129 PORT_CONTEXT = 0x1e04,
130 PORT_EXEC_DIAG = 0x1e00,
131 PORT_PSD_DIAG = 0x1e40,
132 PORT_SCONTROL = 0x1f00,
133 PORT_SSTATUS = 0x1f04,
134 PORT_SERROR = 0x1f08,
135 PORT_SACTIVE = 0x1f0c,
136
137
138 PORT_CS_PORT_RST = (1 << 0),
139 PORT_CS_DEV_RST = (1 << 1),
140 PORT_CS_INIT = (1 << 2),
141 PORT_CS_IRQ_WOC = (1 << 3),
142 PORT_CS_CDB16 = (1 << 5),
143 PORT_CS_PMP_RESUME = (1 << 6),
144 PORT_CS_32BIT_ACTV = (1 << 10),
145 PORT_CS_PMP_EN = (1 << 13),
146 PORT_CS_RDY = (1 << 31),
147
148
149
150 PORT_IRQ_COMPLETE = (1 << 0),
151 PORT_IRQ_ERROR = (1 << 1),
152 PORT_IRQ_PORTRDY_CHG = (1 << 2),
153 PORT_IRQ_PWR_CHG = (1 << 3),
154 PORT_IRQ_PHYRDY_CHG = (1 << 4),
155 PORT_IRQ_COMWAKE = (1 << 5),
156 PORT_IRQ_UNK_FIS = (1 << 6),
157 PORT_IRQ_DEV_XCHG = (1 << 7),
158 PORT_IRQ_8B10B = (1 << 8),
159 PORT_IRQ_CRC = (1 << 9),
160 PORT_IRQ_HANDSHAKE = (1 << 10),
161 PORT_IRQ_SDB_NOTIFY = (1 << 11),
162
163 DEF_PORT_IRQ = PORT_IRQ_COMPLETE | PORT_IRQ_ERROR |
164 PORT_IRQ_PHYRDY_CHG | PORT_IRQ_DEV_XCHG |
165 PORT_IRQ_UNK_FIS | PORT_IRQ_SDB_NOTIFY,
166
167
168 PORT_IRQ_RAW_SHIFT = 16,
169 PORT_IRQ_MASKED_MASK = 0x7ff,
170 PORT_IRQ_RAW_MASK = (0x7ff << PORT_IRQ_RAW_SHIFT),
171
172
173 PORT_IRQ_STEER_SHIFT = 30,
174 PORT_IRQ_STEER_MASK = (3 << PORT_IRQ_STEER_SHIFT),
175
176
177 PORT_CERR_DEV = 1,
178 PORT_CERR_SDB = 2,
179 PORT_CERR_DATA = 3,
180 PORT_CERR_SEND = 4,
181 PORT_CERR_INCONSISTENT = 5,
182 PORT_CERR_DIRECTION = 6,
183 PORT_CERR_UNDERRUN = 7,
184 PORT_CERR_OVERRUN = 8,
185
186
187 PRB_CTRL_PROTOCOL = (1 << 0),
188 PRB_CTRL_PACKET_READ = (1 << 4),
189 PRB_CTRL_PACKET_WRITE = (1 << 5),
190 PRB_CTRL_NIEN = (1 << 6),
191 PRB_CTRL_SRST = (1 << 7),
192
193
194 PRB_PROT_PACKET = (1 << 0),
195 PRB_PROT_TCQ = (1 << 1),
196 PRB_PROT_NCQ = (1 << 2),
197 PRB_PROT_READ = (1 << 3),
198 PRB_PROT_WRITE = (1 << 4),
199 PRB_PROT_TRANSPARENT = (1 << 5),
200
201
202
203
204 SGE_TRM = (1 << 31),
205 SGE_LNK = (1 << 30),
206
207 SGE_DRD = (1 << 29),
208
209
210 CMD_ERR = 0x21,
211};
212
213#endif
214