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9
10#include <common.h>
11#include <dm.h>
12#include <environment.h>
13#include <malloc.h>
14#include <memalign.h>
15#include <miiphy.h>
16#include <net.h>
17#include <netdev.h>
18
19#include <asm/io.h>
20#include <linux/errno.h>
21#include <linux/compiler.h>
22
23#include <asm/arch/clock.h>
24#include <asm/arch/imx-regs.h>
25#include <asm/mach-imx/sys_proto.h>
26#include <asm-generic/gpio.h>
27
28#include "fec_mxc.h"
29
30DECLARE_GLOBAL_DATA_PTR;
31
32
33
34
35
36#define FEC_XFER_TIMEOUT 5000
37
38
39
40
41
42
43
44#define FEC_DMA_RX_MINALIGN 64
45
46#ifndef CONFIG_MII
47#error "CONFIG_MII has to be defined!"
48#endif
49
50#ifndef CONFIG_FEC_XCV_TYPE
51#define CONFIG_FEC_XCV_TYPE MII100
52#endif
53
54
55
56
57
58#ifdef CONFIG_MX28
59#define CONFIG_FEC_MXC_SWAP_PACKET
60#endif
61
62#define RXDESC_PER_CACHELINE (ARCH_DMA_MINALIGN/sizeof(struct fec_bd))
63
64
65#if ((ARCH_DMA_MINALIGN < 16) || (ARCH_DMA_MINALIGN % 16 != 0))
66#error "ARCH_DMA_MINALIGN must be multiple of 16!"
67#endif
68
69#if ((PKTALIGN < ARCH_DMA_MINALIGN) || \
70 (PKTALIGN % ARCH_DMA_MINALIGN != 0))
71#error "PKTALIGN must be multiple of ARCH_DMA_MINALIGN!"
72#endif
73
74#undef DEBUG
75
76#ifdef CONFIG_FEC_MXC_SWAP_PACKET
77static void swap_packet(uint32_t *packet, int length)
78{
79 int i;
80
81 for (i = 0; i < DIV_ROUND_UP(length, 4); i++)
82 packet[i] = __swab32(packet[i]);
83}
84#endif
85
86
87static int fec_mdio_read(struct ethernet_regs *eth, uint8_t phyaddr,
88 uint8_t regaddr)
89{
90 uint32_t reg;
91 uint32_t phy;
92 uint32_t start;
93 int val;
94
95
96
97
98
99 writel(FEC_IEVENT_MII, ð->ievent);
100 reg = regaddr << FEC_MII_DATA_RA_SHIFT;
101 phy = phyaddr << FEC_MII_DATA_PA_SHIFT;
102
103 writel(FEC_MII_DATA_ST | FEC_MII_DATA_OP_RD | FEC_MII_DATA_TA |
104 phy | reg, ð->mii_data);
105
106
107 start = get_timer(0);
108 while (!(readl(ð->ievent) & FEC_IEVENT_MII)) {
109 if (get_timer(start) > (CONFIG_SYS_HZ / 1000)) {
110 printf("Read MDIO failed...\n");
111 return -1;
112 }
113 }
114
115
116 writel(FEC_IEVENT_MII, ð->ievent);
117
118
119 val = (unsigned short)readl(ð->mii_data);
120 debug("%s: phy: %02x reg:%02x val:%#x\n", __func__, phyaddr,
121 regaddr, val);
122 return val;
123}
124
125static void fec_mii_setspeed(struct ethernet_regs *eth)
126{
127
128
129
130
131
132
133
134
135
136
137
138
139
140
141
142 u32 pclk = imx_get_fecclk();
143 u32 speed = DIV_ROUND_UP(pclk, 5000000);
144 u32 hold = DIV_ROUND_UP(pclk, 100000000) - 1;
145#ifdef FEC_QUIRK_ENET_MAC
146 speed--;
147#endif
148 writel(speed << 1 | hold << 8, ð->mii_speed);
149 debug("%s: mii_speed %08x\n", __func__, readl(ð->mii_speed));
150}
151
152static int fec_mdio_write(struct ethernet_regs *eth, uint8_t phyaddr,
153 uint8_t regaddr, uint16_t data)
154{
155 uint32_t reg;
156 uint32_t phy;
157 uint32_t start;
158
159 reg = regaddr << FEC_MII_DATA_RA_SHIFT;
160 phy = phyaddr << FEC_MII_DATA_PA_SHIFT;
161
162 writel(FEC_MII_DATA_ST | FEC_MII_DATA_OP_WR |
163 FEC_MII_DATA_TA | phy | reg | data, ð->mii_data);
164
165
166 start = get_timer(0);
167 while (!(readl(ð->ievent) & FEC_IEVENT_MII)) {
168 if (get_timer(start) > (CONFIG_SYS_HZ / 1000)) {
169 printf("Write MDIO failed...\n");
170 return -1;
171 }
172 }
173
174
175 writel(FEC_IEVENT_MII, ð->ievent);
176 debug("%s: phy: %02x reg:%02x val:%#x\n", __func__, phyaddr,
177 regaddr, data);
178
179 return 0;
180}
181
182static int fec_phy_read(struct mii_dev *bus, int phyaddr, int dev_addr,
183 int regaddr)
184{
185 return fec_mdio_read(bus->priv, phyaddr, regaddr);
186}
187
188static int fec_phy_write(struct mii_dev *bus, int phyaddr, int dev_addr,
189 int regaddr, u16 data)
190{
191 return fec_mdio_write(bus->priv, phyaddr, regaddr, data);
192}
193
194#ifndef CONFIG_PHYLIB
195static int miiphy_restart_aneg(struct eth_device *dev)
196{
197 int ret = 0;
198#if !defined(CONFIG_FEC_MXC_NO_ANEG)
199 struct fec_priv *fec = (struct fec_priv *)dev->priv;
200 struct ethernet_regs *eth = fec->bus->priv;
201
202
203
204
205
206#ifdef CONFIG_MX27
207 fec_mdio_write(eth, fec->phy_id, MII_DCOUNTER, 0x00FF);
208#endif
209 fec_mdio_write(eth, fec->phy_id, MII_BMCR, BMCR_RESET);
210 udelay(1000);
211
212
213 fec_mdio_write(eth, fec->phy_id, MII_ADVERTISE,
214 LPA_100FULL | LPA_100HALF | LPA_10FULL |
215 LPA_10HALF | PHY_ANLPAR_PSB_802_3);
216 fec_mdio_write(eth, fec->phy_id, MII_BMCR,
217 BMCR_ANENABLE | BMCR_ANRESTART);
218
219 if (fec->mii_postcall)
220 ret = fec->mii_postcall(fec->phy_id);
221
222#endif
223 return ret;
224}
225
226#ifndef CONFIG_FEC_FIXED_SPEED
227static int miiphy_wait_aneg(struct eth_device *dev)
228{
229 uint32_t start;
230 int status;
231 struct fec_priv *fec = (struct fec_priv *)dev->priv;
232 struct ethernet_regs *eth = fec->bus->priv;
233
234
235 start = get_timer(0);
236 do {
237 if (get_timer(start) > (CONFIG_SYS_HZ * 5)) {
238 printf("%s: Autonegotiation timeout\n", dev->name);
239 return -1;
240 }
241
242 status = fec_mdio_read(eth, fec->phy_id, MII_BMSR);
243 if (status < 0) {
244 printf("%s: Autonegotiation failed. status: %d\n",
245 dev->name, status);
246 return -1;
247 }
248 } while (!(status & BMSR_LSTATUS));
249
250 return 0;
251}
252#endif
253#endif
254
255static int fec_rx_task_enable(struct fec_priv *fec)
256{
257 writel(FEC_R_DES_ACTIVE_RDAR, &fec->eth->r_des_active);
258 return 0;
259}
260
261static int fec_rx_task_disable(struct fec_priv *fec)
262{
263 return 0;
264}
265
266static int fec_tx_task_enable(struct fec_priv *fec)
267{
268 writel(FEC_X_DES_ACTIVE_TDAR, &fec->eth->x_des_active);
269 return 0;
270}
271
272static int fec_tx_task_disable(struct fec_priv *fec)
273{
274 return 0;
275}
276
277
278
279
280
281
282
283
284
285
286static void fec_rbd_init(struct fec_priv *fec, int count, int dsize)
287{
288 uint32_t size;
289 ulong data;
290 int i;
291
292
293
294
295
296 size = roundup(dsize, ARCH_DMA_MINALIGN);
297 for (i = 0; i < count; i++) {
298 data = fec->rbd_base[i].data_pointer;
299 memset((void *)data, 0, dsize);
300 flush_dcache_range(data, data + size);
301
302 fec->rbd_base[i].status = FEC_RBD_EMPTY;
303 fec->rbd_base[i].data_length = 0;
304 }
305
306
307 fec->rbd_base[i - 1].status = FEC_RBD_WRAP | FEC_RBD_EMPTY;
308 fec->rbd_index = 0;
309
310 flush_dcache_range((ulong)fec->rbd_base,
311 (ulong)fec->rbd_base + size);
312}
313
314
315
316
317
318
319
320
321
322
323
324
325
326static void fec_tbd_init(struct fec_priv *fec)
327{
328 ulong addr = (ulong)fec->tbd_base;
329 unsigned size = roundup(2 * sizeof(struct fec_bd),
330 ARCH_DMA_MINALIGN);
331
332 memset(fec->tbd_base, 0, size);
333 fec->tbd_base[0].status = 0;
334 fec->tbd_base[1].status = FEC_TBD_WRAP;
335 fec->tbd_index = 0;
336 flush_dcache_range(addr, addr + size);
337}
338
339
340
341
342
343
344static void fec_rbd_clean(int last, struct fec_bd *prbd)
345{
346 unsigned short flags = FEC_RBD_EMPTY;
347 if (last)
348 flags |= FEC_RBD_WRAP;
349 writew(flags, &prbd->status);
350 writew(0, &prbd->data_length);
351}
352
353static int fec_get_hwaddr(int dev_id, unsigned char *mac)
354{
355 imx_get_mac_from_fuse(dev_id, mac);
356 return !is_valid_ethaddr(mac);
357}
358
359#ifdef CONFIG_DM_ETH
360static int fecmxc_set_hwaddr(struct udevice *dev)
361#else
362static int fec_set_hwaddr(struct eth_device *dev)
363#endif
364{
365#ifdef CONFIG_DM_ETH
366 struct fec_priv *fec = dev_get_priv(dev);
367 struct eth_pdata *pdata = dev_get_platdata(dev);
368 uchar *mac = pdata->enetaddr;
369#else
370 uchar *mac = dev->enetaddr;
371 struct fec_priv *fec = (struct fec_priv *)dev->priv;
372#endif
373
374 writel(0, &fec->eth->iaddr1);
375 writel(0, &fec->eth->iaddr2);
376 writel(0, &fec->eth->gaddr1);
377 writel(0, &fec->eth->gaddr2);
378
379
380 writel((mac[0] << 24) + (mac[1] << 16) + (mac[2] << 8) + mac[3],
381 &fec->eth->paddr1);
382 writel((mac[4] << 24) + (mac[5] << 16) + 0x8808, &fec->eth->paddr2);
383
384 return 0;
385}
386
387
388static void fec_reg_setup(struct fec_priv *fec)
389{
390 uint32_t rcntrl;
391
392
393 writel(0x00000000, &fec->eth->imask);
394
395
396 writel(0xffffffff, &fec->eth->ievent);
397
398
399
400
401 rcntrl = PKTSIZE << FEC_RCNTRL_MAX_FL_SHIFT;
402 if (fec->xcv_type != SEVENWIRE)
403 rcntrl |= FEC_RCNTRL_FCE | FEC_RCNTRL_MII_MODE;
404 if (fec->xcv_type == RGMII)
405 rcntrl |= FEC_RCNTRL_RGMII;
406 else if (fec->xcv_type == RMII)
407 rcntrl |= FEC_RCNTRL_RMII;
408
409 writel(rcntrl, &fec->eth->r_cntrl);
410}
411
412
413
414
415
416#ifdef CONFIG_DM_ETH
417static int fec_open(struct udevice *dev)
418#else
419static int fec_open(struct eth_device *edev)
420#endif
421{
422#ifdef CONFIG_DM_ETH
423 struct fec_priv *fec = dev_get_priv(dev);
424#else
425 struct fec_priv *fec = (struct fec_priv *)edev->priv;
426#endif
427 int speed;
428 ulong addr, size;
429 int i;
430
431 debug("fec_open: fec_open(dev)\n");
432
433 writel(1 << 2, &fec->eth->x_cntrl);
434 fec->rbd_index = 0;
435
436
437 for (i = 0; i < FEC_RBD_NUM - 1; i++)
438 fec_rbd_clean(0, &fec->rbd_base[i]);
439 fec_rbd_clean(1, &fec->rbd_base[i]);
440
441
442 size = roundup(FEC_RBD_NUM * sizeof(struct fec_bd),
443 ARCH_DMA_MINALIGN);
444 addr = (ulong)fec->rbd_base;
445 flush_dcache_range(addr, addr + size);
446
447#ifdef FEC_QUIRK_ENET_MAC
448
449 writel(readl(&fec->eth->ecntrl) | FEC_ECNTRL_DBSWAP,
450 &fec->eth->ecntrl);
451
452 writel(readl(&fec->eth->x_wmrk) | FEC_X_WMRK_STRFWD,
453 &fec->eth->x_wmrk);
454#endif
455
456 writel(readl(&fec->eth->ecntrl) | FEC_ECNTRL_ETHER_EN,
457 &fec->eth->ecntrl);
458
459#if defined(CONFIG_MX25) || defined(CONFIG_MX53) || defined(CONFIG_MX6SL)
460 udelay(100);
461
462
463
464 writew(0, &fec->eth->miigsk_enr);
465
466
467 while (readw(&fec->eth->miigsk_enr) & MIIGSK_ENR_READY)
468 udelay(2);
469
470
471 writew(MIIGSK_CFGR_IF_MODE_RMII, &fec->eth->miigsk_cfgr);
472
473
474 writew(MIIGSK_ENR_EN, &fec->eth->miigsk_enr);
475
476
477 int max_loops = 10;
478 while ((readw(&fec->eth->miigsk_enr) & MIIGSK_ENR_READY) == 0) {
479 if (--max_loops <= 0) {
480 printf("WAIT for MII Gasket ready timed out\n");
481 break;
482 }
483 }
484#endif
485
486#ifdef CONFIG_PHYLIB
487 {
488
489 int ret = phy_startup(fec->phydev);
490
491 if (ret) {
492 printf("Could not initialize PHY %s\n",
493 fec->phydev->dev->name);
494 return ret;
495 }
496 speed = fec->phydev->speed;
497 }
498#elif CONFIG_FEC_FIXED_SPEED
499 speed = CONFIG_FEC_FIXED_SPEED;
500#else
501 miiphy_wait_aneg(edev);
502 speed = miiphy_speed(edev->name, fec->phy_id);
503 miiphy_duplex(edev->name, fec->phy_id);
504#endif
505
506#ifdef FEC_QUIRK_ENET_MAC
507 {
508 u32 ecr = readl(&fec->eth->ecntrl) & ~FEC_ECNTRL_SPEED;
509 u32 rcr = readl(&fec->eth->r_cntrl) & ~FEC_RCNTRL_RMII_10T;
510 if (speed == _1000BASET)
511 ecr |= FEC_ECNTRL_SPEED;
512 else if (speed != _100BASET)
513 rcr |= FEC_RCNTRL_RMII_10T;
514 writel(ecr, &fec->eth->ecntrl);
515 writel(rcr, &fec->eth->r_cntrl);
516 }
517#endif
518 debug("%s:Speed=%i\n", __func__, speed);
519
520
521 fec_rx_task_enable(fec);
522
523 udelay(100000);
524 return 0;
525}
526
527#ifdef CONFIG_DM_ETH
528static int fecmxc_init(struct udevice *dev)
529#else
530static int fec_init(struct eth_device *dev, bd_t *bd)
531#endif
532{
533#ifdef CONFIG_DM_ETH
534 struct fec_priv *fec = dev_get_priv(dev);
535#else
536 struct fec_priv *fec = (struct fec_priv *)dev->priv;
537#endif
538 u8 *mib_ptr = (uint8_t *)&fec->eth->rmon_t_drop;
539 u8 *i;
540 ulong addr;
541
542
543#ifdef CONFIG_DM_ETH
544 fecmxc_set_hwaddr(dev);
545#else
546 fec_set_hwaddr(dev);
547#endif
548
549
550 fec_tbd_init(fec);
551
552
553 fec_rbd_init(fec, FEC_RBD_NUM, FEC_MAX_PKT_SIZE);
554
555 fec_reg_setup(fec);
556
557 if (fec->xcv_type != SEVENWIRE)
558 fec_mii_setspeed(fec->bus->priv);
559
560
561 writel(0x00010020, &fec->eth->op_pause);
562 writel(0x2, &fec->eth->x_wmrk);
563
564
565 writel(0x00000000, &fec->eth->gaddr1);
566 writel(0x00000000, &fec->eth->gaddr2);
567
568
569 if (!is_mx6ul() && !is_mx6ull() && !is_mx8m()) {
570
571 for (i = mib_ptr; i <= mib_ptr + 0xfc; i += 4)
572 writel(0, i);
573
574
575 writel(0x520, &fec->eth->r_fstart);
576 }
577
578
579 writel(FEC_MAX_PKT_SIZE, &fec->eth->emrbr);
580
581 addr = (ulong)fec->tbd_base;
582 writel((uint32_t)addr, &fec->eth->etdsr);
583
584 addr = (ulong)fec->rbd_base;
585 writel((uint32_t)addr, &fec->eth->erdsr);
586
587#ifndef CONFIG_PHYLIB
588 if (fec->xcv_type != SEVENWIRE)
589 miiphy_restart_aneg(dev);
590#endif
591 fec_open(dev);
592 return 0;
593}
594
595
596
597
598
599#ifdef CONFIG_DM_ETH
600static void fecmxc_halt(struct udevice *dev)
601#else
602static void fec_halt(struct eth_device *dev)
603#endif
604{
605#ifdef CONFIG_DM_ETH
606 struct fec_priv *fec = dev_get_priv(dev);
607#else
608 struct fec_priv *fec = (struct fec_priv *)dev->priv;
609#endif
610 int counter = 0xffff;
611
612
613 writel(FEC_TCNTRL_GTS | readl(&fec->eth->x_cntrl),
614 &fec->eth->x_cntrl);
615
616 debug("eth_halt: wait for stop regs\n");
617
618 while ((counter--) && (!(readl(&fec->eth->ievent) & FEC_IEVENT_GRA)))
619 udelay(1);
620
621
622 fec_tx_task_disable(fec);
623 fec_rx_task_disable(fec);
624
625
626
627
628
629 writel(readl(&fec->eth->ecntrl) & ~FEC_ECNTRL_ETHER_EN,
630 &fec->eth->ecntrl);
631 fec->rbd_index = 0;
632 fec->tbd_index = 0;
633 debug("eth_halt: done\n");
634}
635
636
637
638
639
640
641
642
643#ifdef CONFIG_DM_ETH
644static int fecmxc_send(struct udevice *dev, void *packet, int length)
645#else
646static int fec_send(struct eth_device *dev, void *packet, int length)
647#endif
648{
649 unsigned int status;
650 u32 size;
651 ulong addr, end;
652 int timeout = FEC_XFER_TIMEOUT;
653 int ret = 0;
654
655
656
657
658
659#ifdef CONFIG_DM_ETH
660 struct fec_priv *fec = dev_get_priv(dev);
661#else
662 struct fec_priv *fec = (struct fec_priv *)dev->priv;
663#endif
664
665
666
667
668 if ((length > 1500) || (length <= 0)) {
669 printf("Payload (%d) too large\n", length);
670 return -1;
671 }
672
673
674
675
676
677
678#ifdef CONFIG_FEC_MXC_SWAP_PACKET
679 swap_packet((uint32_t *)packet, length);
680#endif
681
682 addr = (ulong)packet;
683 end = roundup(addr + length, ARCH_DMA_MINALIGN);
684 addr &= ~(ARCH_DMA_MINALIGN - 1);
685 flush_dcache_range(addr, end);
686
687 writew(length, &fec->tbd_base[fec->tbd_index].data_length);
688 writel((uint32_t)addr, &fec->tbd_base[fec->tbd_index].data_pointer);
689
690
691
692
693
694
695
696
697
698 status = readw(&fec->tbd_base[fec->tbd_index].status) & FEC_TBD_WRAP;
699 status |= FEC_TBD_LAST | FEC_TBD_TC | FEC_TBD_READY;
700 writew(status, &fec->tbd_base[fec->tbd_index].status);
701
702
703
704
705
706
707 size = roundup(2 * sizeof(struct fec_bd), ARCH_DMA_MINALIGN);
708 addr = (ulong)fec->tbd_base;
709 flush_dcache_range(addr, addr + size);
710
711
712
713
714
715
716
717
718
719
720
721
722
723
724
725
726
727
728
729
730
731 readl(addr + size - 4);
732
733
734 fec_tx_task_enable(fec);
735
736
737
738
739
740
741 while (--timeout) {
742 if (!(readl(&fec->eth->x_des_active) & FEC_X_DES_ACTIVE_TDAR))
743 break;
744 }
745
746 if (!timeout) {
747 ret = -EINVAL;
748 goto out;
749 }
750
751
752
753
754
755
756
757
758
759
760
761
762
763
764
765 timeout = FEC_XFER_TIMEOUT;
766 while (--timeout) {
767 invalidate_dcache_range(addr, addr + size);
768 if (!(readw(&fec->tbd_base[fec->tbd_index].status) &
769 FEC_TBD_READY))
770 break;
771 }
772
773 if (!timeout)
774 ret = -EINVAL;
775
776out:
777 debug("fec_send: status 0x%x index %d ret %i\n",
778 readw(&fec->tbd_base[fec->tbd_index].status),
779 fec->tbd_index, ret);
780
781 if (fec->tbd_index)
782 fec->tbd_index = 0;
783 else
784 fec->tbd_index = 1;
785
786 return ret;
787}
788
789
790
791
792
793
794#ifdef CONFIG_DM_ETH
795static int fecmxc_recv(struct udevice *dev, int flags, uchar **packetp)
796#else
797static int fec_recv(struct eth_device *dev)
798#endif
799{
800#ifdef CONFIG_DM_ETH
801 struct fec_priv *fec = dev_get_priv(dev);
802#else
803 struct fec_priv *fec = (struct fec_priv *)dev->priv;
804#endif
805 struct fec_bd *rbd = &fec->rbd_base[fec->rbd_index];
806 unsigned long ievent;
807 int frame_length, len = 0;
808 uint16_t bd_status;
809 ulong addr, size, end;
810 int i;
811
812#ifdef CONFIG_DM_ETH
813 *packetp = memalign(ARCH_DMA_MINALIGN, FEC_MAX_PKT_SIZE);
814 if (*packetp == 0) {
815 printf("%s: error allocating packetp\n", __func__);
816 return -ENOMEM;
817 }
818#else
819 ALLOC_CACHE_ALIGN_BUFFER(uchar, buff, FEC_MAX_PKT_SIZE);
820#endif
821
822
823 ievent = readl(&fec->eth->ievent);
824 writel(ievent, &fec->eth->ievent);
825 debug("fec_recv: ievent 0x%lx\n", ievent);
826 if (ievent & FEC_IEVENT_BABR) {
827#ifdef CONFIG_DM_ETH
828 fecmxc_halt(dev);
829 fecmxc_init(dev);
830#else
831 fec_halt(dev);
832 fec_init(dev, fec->bd);
833#endif
834 printf("some error: 0x%08lx\n", ievent);
835 return 0;
836 }
837 if (ievent & FEC_IEVENT_HBERR) {
838
839 writel(0x00000001 | readl(&fec->eth->x_cntrl),
840 &fec->eth->x_cntrl);
841 }
842 if (ievent & FEC_IEVENT_GRA) {
843
844 if (readl(&fec->eth->x_cntrl) & 0x00000001) {
845#ifdef CONFIG_DM_ETH
846 fecmxc_halt(dev);
847#else
848 fec_halt(dev);
849#endif
850 writel(~0x00000001 & readl(&fec->eth->x_cntrl),
851 &fec->eth->x_cntrl);
852#ifdef CONFIG_DM_ETH
853 fecmxc_init(dev);
854#else
855 fec_init(dev, fec->bd);
856#endif
857 }
858 }
859
860
861
862
863
864
865
866
867
868
869
870
871
872
873 addr = (ulong)rbd;
874 addr &= ~(ARCH_DMA_MINALIGN - 1);
875 size = roundup(sizeof(struct fec_bd), ARCH_DMA_MINALIGN);
876 invalidate_dcache_range(addr, addr + size);
877
878 bd_status = readw(&rbd->status);
879 debug("fec_recv: status 0x%x\n", bd_status);
880
881 if (!(bd_status & FEC_RBD_EMPTY)) {
882 if ((bd_status & FEC_RBD_LAST) && !(bd_status & FEC_RBD_ERR) &&
883 ((readw(&rbd->data_length) - 4) > 14)) {
884
885 addr = readl(&rbd->data_pointer);
886 frame_length = readw(&rbd->data_length) - 4;
887
888 end = roundup(addr + frame_length, ARCH_DMA_MINALIGN);
889 addr &= ~(ARCH_DMA_MINALIGN - 1);
890 invalidate_dcache_range(addr, end);
891
892
893#ifdef CONFIG_FEC_MXC_SWAP_PACKET
894 swap_packet((uint32_t *)addr, frame_length);
895#endif
896
897#ifdef CONFIG_DM_ETH
898 memcpy(*packetp, (char *)addr, frame_length);
899#else
900 memcpy(buff, (char *)addr, frame_length);
901 net_process_received_packet(buff, frame_length);
902#endif
903 len = frame_length;
904 } else {
905 if (bd_status & FEC_RBD_ERR)
906 debug("error frame: 0x%08lx 0x%08x\n",
907 addr, bd_status);
908 }
909
910
911
912
913
914
915
916 size = RXDESC_PER_CACHELINE - 1;
917 if ((fec->rbd_index & size) == size) {
918 i = fec->rbd_index - size;
919 addr = (ulong)&fec->rbd_base[i];
920 for (; i <= fec->rbd_index ; i++) {
921 fec_rbd_clean(i == (FEC_RBD_NUM - 1),
922 &fec->rbd_base[i]);
923 }
924 flush_dcache_range(addr,
925 addr + ARCH_DMA_MINALIGN);
926 }
927
928 fec_rx_task_enable(fec);
929 fec->rbd_index = (fec->rbd_index + 1) % FEC_RBD_NUM;
930 }
931 debug("fec_recv: stop\n");
932
933 return len;
934}
935
936static void fec_set_dev_name(char *dest, int dev_id)
937{
938 sprintf(dest, (dev_id == -1) ? "FEC" : "FEC%i", dev_id);
939}
940
941static int fec_alloc_descs(struct fec_priv *fec)
942{
943 unsigned int size;
944 int i;
945 uint8_t *data;
946 ulong addr;
947
948
949 size = roundup(2 * sizeof(struct fec_bd), ARCH_DMA_MINALIGN);
950 fec->tbd_base = memalign(ARCH_DMA_MINALIGN, size);
951 if (!fec->tbd_base)
952 goto err_tx;
953
954
955 size = roundup(FEC_RBD_NUM * sizeof(struct fec_bd), ARCH_DMA_MINALIGN);
956 fec->rbd_base = memalign(ARCH_DMA_MINALIGN, size);
957 if (!fec->rbd_base)
958 goto err_rx;
959
960 memset(fec->rbd_base, 0, size);
961
962
963
964
965 size = roundup(FEC_MAX_PKT_SIZE, FEC_DMA_RX_MINALIGN);
966 for (i = 0; i < FEC_RBD_NUM; i++) {
967 data = memalign(FEC_DMA_RX_MINALIGN, size);
968 if (!data) {
969 printf("%s: error allocating rxbuf %d\n", __func__, i);
970 goto err_ring;
971 }
972
973 memset(data, 0, size);
974
975 addr = (ulong)data;
976 fec->rbd_base[i].data_pointer = (uint32_t)addr;
977 fec->rbd_base[i].status = FEC_RBD_EMPTY;
978 fec->rbd_base[i].data_length = 0;
979
980 flush_dcache_range(addr, addr + size);
981 }
982
983
984 fec->rbd_base[i - 1].status = FEC_RBD_WRAP | FEC_RBD_EMPTY;
985
986 fec->rbd_index = 0;
987 fec->tbd_index = 0;
988
989 return 0;
990
991err_ring:
992 for (; i >= 0; i--) {
993 addr = fec->rbd_base[i].data_pointer;
994 free((void *)addr);
995 }
996 free(fec->rbd_base);
997err_rx:
998 free(fec->tbd_base);
999err_tx:
1000 return -ENOMEM;
1001}
1002
1003static void fec_free_descs(struct fec_priv *fec)
1004{
1005 int i;
1006 ulong addr;
1007
1008 for (i = 0; i < FEC_RBD_NUM; i++) {
1009 addr = fec->rbd_base[i].data_pointer;
1010 free((void *)addr);
1011 }
1012 free(fec->rbd_base);
1013 free(fec->tbd_base);
1014}
1015
1016struct mii_dev *fec_get_miibus(ulong base_addr, int dev_id)
1017{
1018 struct ethernet_regs *eth = (struct ethernet_regs *)base_addr;
1019 struct mii_dev *bus;
1020 int ret;
1021
1022 bus = mdio_alloc();
1023 if (!bus) {
1024 printf("mdio_alloc failed\n");
1025 return NULL;
1026 }
1027 bus->read = fec_phy_read;
1028 bus->write = fec_phy_write;
1029 bus->priv = eth;
1030 fec_set_dev_name(bus->name, dev_id);
1031
1032 ret = mdio_register(bus);
1033 if (ret) {
1034 printf("mdio_register failed\n");
1035 free(bus);
1036 return NULL;
1037 }
1038 fec_mii_setspeed(eth);
1039 return bus;
1040}
1041
1042#ifndef CONFIG_DM_ETH
1043#ifdef CONFIG_PHYLIB
1044int fec_probe(bd_t *bd, int dev_id, uint32_t base_addr,
1045 struct mii_dev *bus, struct phy_device *phydev)
1046#else
1047static int fec_probe(bd_t *bd, int dev_id, uint32_t base_addr,
1048 struct mii_dev *bus, int phy_id)
1049#endif
1050{
1051 struct eth_device *edev;
1052 struct fec_priv *fec;
1053 unsigned char ethaddr[6];
1054 char mac[16];
1055 uint32_t start;
1056 int ret = 0;
1057
1058
1059 edev = (struct eth_device *)malloc(sizeof(struct eth_device));
1060 if (!edev) {
1061 puts("fec_mxc: not enough malloc memory for eth_device\n");
1062 ret = -ENOMEM;
1063 goto err1;
1064 }
1065
1066 fec = (struct fec_priv *)malloc(sizeof(struct fec_priv));
1067 if (!fec) {
1068 puts("fec_mxc: not enough malloc memory for fec_priv\n");
1069 ret = -ENOMEM;
1070 goto err2;
1071 }
1072
1073 memset(edev, 0, sizeof(*edev));
1074 memset(fec, 0, sizeof(*fec));
1075
1076 ret = fec_alloc_descs(fec);
1077 if (ret)
1078 goto err3;
1079
1080 edev->priv = fec;
1081 edev->init = fec_init;
1082 edev->send = fec_send;
1083 edev->recv = fec_recv;
1084 edev->halt = fec_halt;
1085 edev->write_hwaddr = fec_set_hwaddr;
1086
1087 fec->eth = (struct ethernet_regs *)(ulong)base_addr;
1088 fec->bd = bd;
1089
1090 fec->xcv_type = CONFIG_FEC_XCV_TYPE;
1091
1092
1093 writel(readl(&fec->eth->ecntrl) | FEC_ECNTRL_RESET, &fec->eth->ecntrl);
1094 start = get_timer(0);
1095 while (readl(&fec->eth->ecntrl) & FEC_ECNTRL_RESET) {
1096 if (get_timer(start) > (CONFIG_SYS_HZ * 5)) {
1097 printf("FEC MXC: Timeout resetting chip\n");
1098 goto err4;
1099 }
1100 udelay(10);
1101 }
1102
1103 fec_reg_setup(fec);
1104 fec_set_dev_name(edev->name, dev_id);
1105 fec->dev_id = (dev_id == -1) ? 0 : dev_id;
1106 fec->bus = bus;
1107 fec_mii_setspeed(bus->priv);
1108#ifdef CONFIG_PHYLIB
1109 fec->phydev = phydev;
1110 phy_connect_dev(phydev, edev);
1111
1112 phy_config(phydev);
1113#else
1114 fec->phy_id = phy_id;
1115#endif
1116 eth_register(edev);
1117
1118 edev->index = fec->dev_id;
1119
1120 if (fec_get_hwaddr(fec->dev_id, ethaddr) == 0) {
1121 debug("got MAC%d address from fuse: %pM\n", fec->dev_id, ethaddr);
1122 memcpy(edev->enetaddr, ethaddr, 6);
1123 if (fec->dev_id)
1124 sprintf(mac, "eth%daddr", fec->dev_id);
1125 else
1126 strcpy(mac, "ethaddr");
1127 if (!env_get(mac))
1128 eth_env_set_enetaddr(mac, ethaddr);
1129 }
1130 return ret;
1131err4:
1132 fec_free_descs(fec);
1133err3:
1134 free(fec);
1135err2:
1136 free(edev);
1137err1:
1138 return ret;
1139}
1140
1141int fecmxc_initialize_multi(bd_t *bd, int dev_id, int phy_id, uint32_t addr)
1142{
1143 uint32_t base_mii;
1144 struct mii_dev *bus = NULL;
1145#ifdef CONFIG_PHYLIB
1146 struct phy_device *phydev = NULL;
1147#endif
1148 int ret;
1149
1150#ifdef CONFIG_FEC_MXC_MDIO_BASE
1151
1152
1153
1154
1155 base_mii = CONFIG_FEC_MXC_MDIO_BASE;
1156#else
1157 base_mii = addr;
1158#endif
1159 debug("eth_init: fec_probe(bd, %i, %i) @ %08x\n", dev_id, phy_id, addr);
1160 bus = fec_get_miibus(base_mii, dev_id);
1161 if (!bus)
1162 return -ENOMEM;
1163#ifdef CONFIG_PHYLIB
1164 phydev = phy_find_by_mask(bus, 1 << phy_id, PHY_INTERFACE_MODE_RGMII);
1165 if (!phydev) {
1166 mdio_unregister(bus);
1167 free(bus);
1168 return -ENOMEM;
1169 }
1170 ret = fec_probe(bd, dev_id, addr, bus, phydev);
1171#else
1172 ret = fec_probe(bd, dev_id, addr, bus, phy_id);
1173#endif
1174 if (ret) {
1175#ifdef CONFIG_PHYLIB
1176 free(phydev);
1177#endif
1178 mdio_unregister(bus);
1179 free(bus);
1180 }
1181 return ret;
1182}
1183
1184#ifdef CONFIG_FEC_MXC_PHYADDR
1185int fecmxc_initialize(bd_t *bd)
1186{
1187 return fecmxc_initialize_multi(bd, -1, CONFIG_FEC_MXC_PHYADDR,
1188 IMX_FEC_BASE);
1189}
1190#endif
1191
1192#ifndef CONFIG_PHYLIB
1193int fecmxc_register_mii_postcall(struct eth_device *dev, int (*cb)(int))
1194{
1195 struct fec_priv *fec = (struct fec_priv *)dev->priv;
1196 fec->mii_postcall = cb;
1197 return 0;
1198}
1199#endif
1200
1201#else
1202
1203static int fecmxc_read_rom_hwaddr(struct udevice *dev)
1204{
1205 struct fec_priv *priv = dev_get_priv(dev);
1206 struct eth_pdata *pdata = dev_get_platdata(dev);
1207
1208 return fec_get_hwaddr(priv->dev_id, pdata->enetaddr);
1209}
1210
1211static int fecmxc_free_pkt(struct udevice *dev, uchar *packet, int length)
1212{
1213 if (packet)
1214 free(packet);
1215
1216 return 0;
1217}
1218
1219static const struct eth_ops fecmxc_ops = {
1220 .start = fecmxc_init,
1221 .send = fecmxc_send,
1222 .recv = fecmxc_recv,
1223 .free_pkt = fecmxc_free_pkt,
1224 .stop = fecmxc_halt,
1225 .write_hwaddr = fecmxc_set_hwaddr,
1226 .read_rom_hwaddr = fecmxc_read_rom_hwaddr,
1227};
1228
1229static int fec_phy_init(struct fec_priv *priv, struct udevice *dev)
1230{
1231 struct phy_device *phydev;
1232 int mask = 0xffffffff;
1233
1234#ifdef CONFIG_FEC_MXC_PHYADDR
1235 mask = 1 << CONFIG_FEC_MXC_PHYADDR;
1236#endif
1237
1238 phydev = phy_find_by_mask(priv->bus, mask, priv->interface);
1239 if (!phydev)
1240 return -ENODEV;
1241
1242 phy_connect_dev(phydev, dev);
1243
1244 priv->phydev = phydev;
1245 phy_config(phydev);
1246
1247 return 0;
1248}
1249
1250#ifdef CONFIG_DM_GPIO
1251
1252static void fec_gpio_reset(struct fec_priv *priv)
1253{
1254 debug("fec_gpio_reset: fec_gpio_reset(dev)\n");
1255 if (dm_gpio_is_valid(&priv->phy_reset_gpio)) {
1256 dm_gpio_set_value(&priv->phy_reset_gpio, 1);
1257 udelay(priv->reset_delay);
1258 dm_gpio_set_value(&priv->phy_reset_gpio, 0);
1259 }
1260}
1261#endif
1262
1263static int fecmxc_probe(struct udevice *dev)
1264{
1265 struct eth_pdata *pdata = dev_get_platdata(dev);
1266 struct fec_priv *priv = dev_get_priv(dev);
1267 struct mii_dev *bus = NULL;
1268 uint32_t start;
1269 int ret;
1270
1271 ret = fec_alloc_descs(priv);
1272 if (ret)
1273 return ret;
1274
1275#ifdef CONFIG_DM_GPIO
1276 fec_gpio_reset(priv);
1277#endif
1278
1279 writel(readl(&priv->eth->ecntrl) | FEC_ECNTRL_RESET,
1280 &priv->eth->ecntrl);
1281 start = get_timer(0);
1282 while (readl(&priv->eth->ecntrl) & FEC_ECNTRL_RESET) {
1283 if (get_timer(start) > (CONFIG_SYS_HZ * 5)) {
1284 printf("FEC MXC: Timeout reseting chip\n");
1285 goto err_timeout;
1286 }
1287 udelay(10);
1288 }
1289
1290 fec_reg_setup(priv);
1291
1292 priv->dev_id = dev->seq;
1293#ifdef CONFIG_FEC_MXC_MDIO_BASE
1294 bus = fec_get_miibus((ulong)CONFIG_FEC_MXC_MDIO_BASE, dev->seq);
1295#else
1296 bus = fec_get_miibus((ulong)priv->eth, dev->seq);
1297#endif
1298 if (!bus) {
1299 ret = -ENOMEM;
1300 goto err_mii;
1301 }
1302
1303 priv->bus = bus;
1304 priv->xcv_type = CONFIG_FEC_XCV_TYPE;
1305 priv->interface = pdata->phy_interface;
1306 ret = fec_phy_init(priv, dev);
1307 if (ret)
1308 goto err_phy;
1309
1310 return 0;
1311
1312err_phy:
1313 mdio_unregister(bus);
1314 free(bus);
1315err_mii:
1316err_timeout:
1317 fec_free_descs(priv);
1318 return ret;
1319}
1320
1321static int fecmxc_remove(struct udevice *dev)
1322{
1323 struct fec_priv *priv = dev_get_priv(dev);
1324
1325 free(priv->phydev);
1326 fec_free_descs(priv);
1327 mdio_unregister(priv->bus);
1328 mdio_free(priv->bus);
1329
1330 return 0;
1331}
1332
1333static int fecmxc_ofdata_to_platdata(struct udevice *dev)
1334{
1335 int ret = 0;
1336 struct eth_pdata *pdata = dev_get_platdata(dev);
1337 struct fec_priv *priv = dev_get_priv(dev);
1338 const char *phy_mode;
1339
1340 pdata->iobase = (phys_addr_t)devfdt_get_addr(dev);
1341 priv->eth = (struct ethernet_regs *)pdata->iobase;
1342
1343 pdata->phy_interface = -1;
1344 phy_mode = fdt_getprop(gd->fdt_blob, dev_of_offset(dev), "phy-mode",
1345 NULL);
1346 if (phy_mode)
1347 pdata->phy_interface = phy_get_interface_by_name(phy_mode);
1348 if (pdata->phy_interface == -1) {
1349 debug("%s: Invalid PHY interface '%s'\n", __func__, phy_mode);
1350 return -EINVAL;
1351 }
1352
1353#ifdef CONFIG_DM_GPIO
1354 ret = gpio_request_by_name(dev, "phy-reset-gpios", 0,
1355 &priv->phy_reset_gpio, GPIOD_IS_OUT);
1356 if (ret == 0) {
1357 ret = dev_read_u32_array(dev, "phy-reset-duration",
1358 &priv->reset_delay, 1);
1359 } else if (ret == -ENOENT) {
1360 priv->reset_delay = 1000;
1361 ret = 0;
1362 }
1363
1364 if (priv->reset_delay > 1000) {
1365 printf("FEX MXC: gpio reset timeout should be less the 1000\n");
1366 priv->reset_delay = 1000;
1367 }
1368#endif
1369
1370 return ret;
1371}
1372
1373static const struct udevice_id fecmxc_ids[] = {
1374 { .compatible = "fsl,imx6q-fec" },
1375 { .compatible = "fsl,imx6sl-fec" },
1376 { .compatible = "fsl,imx6sx-fec" },
1377 { .compatible = "fsl,imx6ul-fec" },
1378 { .compatible = "fsl,imx53-fec" },
1379 { }
1380};
1381
1382U_BOOT_DRIVER(fecmxc_gem) = {
1383 .name = "fecmxc",
1384 .id = UCLASS_ETH,
1385 .of_match = fecmxc_ids,
1386 .ofdata_to_platdata = fecmxc_ofdata_to_platdata,
1387 .probe = fecmxc_probe,
1388 .remove = fecmxc_remove,
1389 .ops = &fecmxc_ops,
1390 .priv_auto_alloc_size = sizeof(struct fec_priv),
1391 .platdata_auto_alloc_size = sizeof(struct eth_pdata),
1392};
1393#endif
1394