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6#include <common.h>
7#include <malloc.h>
8#include <asm/fsl_serdes.h>
9
10DECLARE_GLOBAL_DATA_PTR;
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25
26#include <pci.h>
27#include <asm/io.h>
28#include <asm/fsl_pci.h>
29
30#ifndef CONFIG_SYS_PCI_MEMORY_BUS
31#define CONFIG_SYS_PCI_MEMORY_BUS 0
32#endif
33
34#ifndef CONFIG_SYS_PCI_MEMORY_PHYS
35#define CONFIG_SYS_PCI_MEMORY_PHYS 0
36#endif
37
38#if defined(CONFIG_SYS_PCI_64BIT) && !defined(CONFIG_SYS_PCI64_MEMORY_BUS)
39#define CONFIG_SYS_PCI64_MEMORY_BUS (64ull*1024*1024*1024)
40#endif
41
42
43
44
45
46static void set_inbound_window(volatile pit_t *pi,
47 struct pci_region *r,
48 u64 size)
49{
50 u32 sz = (__ilog2_u64(size) - 1);
51#ifdef CONFIG_SYS_FSL_ERRATUM_A005434
52 u32 flag = 0;
53#else
54 u32 flag = PIWAR_LOCAL;
55#endif
56
57 flag |= PIWAR_EN | PIWAR_READ_SNOOP | PIWAR_WRITE_SNOOP;
58
59 out_be32(&pi->pitar, r->phys_start >> 12);
60 out_be32(&pi->piwbar, r->bus_start >> 12);
61#ifdef CONFIG_SYS_PCI_64BIT
62 out_be32(&pi->piwbear, r->bus_start >> 44);
63#else
64 out_be32(&pi->piwbear, 0);
65#endif
66 if (r->flags & PCI_REGION_PREFETCH)
67 flag |= PIWAR_PF;
68 out_be32(&pi->piwar, flag | sz);
69}
70
71int fsl_setup_hose(struct pci_controller *hose, unsigned long addr)
72{
73 volatile ccsr_fsl_pci_t *pci = (ccsr_fsl_pci_t *) addr;
74
75
76 memset(hose, 0, sizeof(struct pci_controller));
77
78 pci_setup_indirect(hose, (u32)&pci->cfg_addr, (u32)&pci->cfg_data);
79
80 return fsl_is_pci_agent(hose);
81}
82
83static int fsl_pci_setup_inbound_windows(struct pci_controller *hose,
84 u64 out_lo, u8 pcie_cap,
85 volatile pit_t *pi)
86{
87 struct pci_region *r = hose->regions + hose->region_count;
88 u64 sz = min((u64)gd->ram_size, (1ull << 32));
89
90 phys_addr_t phys_start = CONFIG_SYS_PCI_MEMORY_PHYS;
91 pci_addr_t bus_start = CONFIG_SYS_PCI_MEMORY_BUS;
92 pci_size_t pci_sz;
93
94
95 if (bus_start > out_lo) {
96 printf ("no space for inbound mapping of memory\n");
97 return 0;
98 }
99
100
101 if ((bus_start + sz) > out_lo) {
102 sz = out_lo - bus_start;
103 debug ("limiting size to %llx\n", sz);
104 }
105
106 pci_sz = 1ull << __ilog2_u64(sz);
107
108
109
110
111 if ((pcie_cap == PCI_CAP_ID_EXP) && (pci_sz < sz)) {
112 debug ("R0 bus_start: %llx phys_start: %llx size: %llx\n",
113 (u64)bus_start, (u64)phys_start, (u64)sz);
114 pci_set_region(r, bus_start, phys_start, sz,
115 PCI_REGION_MEM | PCI_REGION_SYS_MEMORY |
116 PCI_REGION_PREFETCH);
117
118
119
120
121
122 if (pci_sz != sz)
123 sz = 2ull << __ilog2_u64(sz);
124
125 set_inbound_window(pi--, r++, sz);
126 sz = 0;
127 } else {
128 debug ("R0 bus_start: %llx phys_start: %llx size: %llx\n",
129 (u64)bus_start, (u64)phys_start, (u64)pci_sz);
130 pci_set_region(r, bus_start, phys_start, pci_sz,
131 PCI_REGION_MEM | PCI_REGION_SYS_MEMORY |
132 PCI_REGION_PREFETCH);
133 set_inbound_window(pi--, r++, pci_sz);
134
135 sz -= pci_sz;
136 bus_start += pci_sz;
137 phys_start += pci_sz;
138
139 pci_sz = 1ull << __ilog2_u64(sz);
140 if (sz) {
141 debug ("R1 bus_start: %llx phys_start: %llx size: %llx\n",
142 (u64)bus_start, (u64)phys_start, (u64)pci_sz);
143 pci_set_region(r, bus_start, phys_start, pci_sz,
144 PCI_REGION_MEM | PCI_REGION_SYS_MEMORY |
145 PCI_REGION_PREFETCH);
146 set_inbound_window(pi--, r++, pci_sz);
147 sz -= pci_sz;
148 bus_start += pci_sz;
149 phys_start += pci_sz;
150 }
151 }
152
153#if defined(CONFIG_PHYS_64BIT) && defined(CONFIG_SYS_PCI_64BIT)
154
155
156
157
158 pci_sz = 1ull << __ilog2_u64(gd->ram_size);
159
160 if (gd->ram_size > pci_sz)
161 pci_sz = 1ull << (__ilog2_u64(gd->ram_size) + 1);
162 debug ("R64 bus_start: %llx phys_start: %llx size: %llx\n",
163 (u64)CONFIG_SYS_PCI64_MEMORY_BUS,
164 (u64)CONFIG_SYS_PCI_MEMORY_PHYS,
165 (u64)pci_sz);
166 pci_set_region(r,
167 CONFIG_SYS_PCI64_MEMORY_BUS,
168 CONFIG_SYS_PCI_MEMORY_PHYS,
169 pci_sz,
170 PCI_REGION_MEM | PCI_REGION_SYS_MEMORY |
171 PCI_REGION_PREFETCH);
172 set_inbound_window(pi--, r++, pci_sz);
173#else
174 pci_sz = 1ull << __ilog2_u64(sz);
175 if (sz) {
176 debug ("R2 bus_start: %llx phys_start: %llx size: %llx\n",
177 (u64)bus_start, (u64)phys_start, (u64)pci_sz);
178 pci_set_region(r, bus_start, phys_start, pci_sz,
179 PCI_REGION_MEM | PCI_REGION_SYS_MEMORY |
180 PCI_REGION_PREFETCH);
181 sz -= pci_sz;
182 bus_start += pci_sz;
183 phys_start += pci_sz;
184 set_inbound_window(pi--, r++, pci_sz);
185 }
186#endif
187
188#ifdef CONFIG_PHYS_64BIT
189 if (sz && (((u64)gd->ram_size) < (1ull << 32)))
190 printf("Was not able to map all of memory via "
191 "inbound windows -- %lld remaining\n", sz);
192#endif
193
194 hose->region_count = r - hose->regions;
195
196 return 1;
197}
198
199#ifdef CONFIG_SRIO_PCIE_BOOT_MASTER
200static void fsl_pcie_boot_master(pit_t *pi)
201{
202
203 debug("PCIEBOOT - MASTER: Inbound window for slave's image; "
204 "Local = 0x%llx, Bus = 0x%llx, Size = 0x%x\n",
205 (u64)CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_PHYS,
206 (u64)CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_BUS1,
207 CONFIG_SRIO_PCIE_BOOT_IMAGE_SIZE);
208 struct pci_region r_inbound;
209 u32 sz_inbound = __ilog2_u64(CONFIG_SRIO_PCIE_BOOT_IMAGE_SIZE)
210 - 1;
211 pci_set_region(&r_inbound,
212 CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_BUS1,
213 CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_PHYS,
214 sz_inbound,
215 PCI_REGION_MEM | PCI_REGION_SYS_MEMORY);
216
217 set_inbound_window(pi--, &r_inbound,
218 CONFIG_SRIO_PCIE_BOOT_IMAGE_SIZE);
219
220
221 debug("PCIEBOOT - MASTER: Inbound window for slave's image; "
222 "Local = 0x%llx, Bus = 0x%llx, Size = 0x%x\n",
223 (u64)CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_PHYS,
224 (u64)CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_BUS2,
225 CONFIG_SRIO_PCIE_BOOT_IMAGE_SIZE);
226 pci_set_region(&r_inbound,
227 CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_BUS2,
228 CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_PHYS,
229 sz_inbound,
230 PCI_REGION_MEM | PCI_REGION_SYS_MEMORY);
231
232 set_inbound_window(pi--, &r_inbound,
233 CONFIG_SRIO_PCIE_BOOT_IMAGE_SIZE);
234
235
236 debug("PCIEBOOT - MASTER: Inbound window for slave's "
237 "ucode and ENV; "
238 "Local = 0x%llx, Bus = 0x%llx, Size = 0x%x\n",
239 (u64)CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_MEM_PHYS,
240 (u64)CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_MEM_BUS,
241 CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_SIZE);
242 sz_inbound = __ilog2_u64(CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_SIZE)
243 - 1;
244 pci_set_region(&r_inbound,
245 CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_MEM_BUS,
246 CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_MEM_PHYS,
247 sz_inbound,
248 PCI_REGION_MEM | PCI_REGION_SYS_MEMORY);
249
250 set_inbound_window(pi--, &r_inbound,
251 CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_SIZE);
252}
253
254static void fsl_pcie_boot_master_release_slave(int port)
255{
256 unsigned long release_addr;
257
258
259 switch (port) {
260 case 1:
261 release_addr = CONFIG_SYS_PCIE1_MEM_VIRT
262 + CONFIG_SRIO_PCIE_BOOT_BRR_OFFSET;
263 break;
264#ifdef CONFIG_SYS_PCIE2_MEM_VIRT
265 case 2:
266 release_addr = CONFIG_SYS_PCIE2_MEM_VIRT
267 + CONFIG_SRIO_PCIE_BOOT_BRR_OFFSET;
268 break;
269#endif
270#ifdef CONFIG_SYS_PCIE3_MEM_VIRT
271 case 3:
272 release_addr = CONFIG_SYS_PCIE3_MEM_VIRT
273 + CONFIG_SRIO_PCIE_BOOT_BRR_OFFSET;
274 break;
275#endif
276 default:
277 release_addr = 0;
278 break;
279 }
280 if (release_addr != 0) {
281 out_be32((void *)release_addr,
282 CONFIG_SRIO_PCIE_BOOT_RELEASE_MASK);
283 debug("PCIEBOOT - MASTER: "
284 "Release slave successfully! Now the slave should start up!\n");
285 } else {
286 debug("PCIEBOOT - MASTER: "
287 "Release slave failed!\n");
288 }
289}
290#endif
291
292void fsl_pci_init(struct pci_controller *hose, struct fsl_pci_info *pci_info)
293{
294 u32 cfg_addr = (u32)&((ccsr_fsl_pci_t *)pci_info->regs)->cfg_addr;
295 u32 cfg_data = (u32)&((ccsr_fsl_pci_t *)pci_info->regs)->cfg_data;
296 u16 temp16;
297 u32 temp32;
298 u32 block_rev;
299 int enabled, r, inbound = 0;
300 u16 ltssm;
301 u8 temp8, pcie_cap;
302 int pcie_cap_pos;
303 int pci_dcr;
304 int pci_dsr;
305 int pci_lsr;
306
307#if defined(CONFIG_FSL_PCIE_DISABLE_ASPM)
308 int pci_lcr;
309#endif
310
311 volatile ccsr_fsl_pci_t *pci = (ccsr_fsl_pci_t *)cfg_addr;
312 struct pci_region *reg = hose->regions + hose->region_count;
313 pci_dev_t dev = PCI_BDF(hose->first_busno, 0, 0);
314
315
316 volatile pot_t *po = &pci->pot[1];
317 volatile pit_t *pi;
318
319 u64 out_hi = 0, out_lo = -1ULL;
320 u32 pcicsrbar, pcicsrbar_sz;
321
322 pci_setup_indirect(hose, cfg_addr, cfg_data);
323
324#ifdef PEX_CCB_DIV
325
326 pci_hose_write_config_dword(hose, dev, 0x440,
327 ((gd->bus_clk / 1000000) *
328 (16 / PEX_CCB_DIV)) / 333);
329#endif
330 block_rev = in_be32(&pci->block_rev1);
331 if (PEX_IP_BLK_REV_2_2 <= block_rev) {
332 pi = &pci->pit[2];
333 } else {
334 pi = &pci->pit[3];
335 }
336
337
338 for (r = 0; r < hose->region_count; r++) {
339 unsigned long flags = hose->regions[r].flags;
340 u32 sz = (__ilog2_u64((u64)hose->regions[r].size) - 1);
341
342 flags &= PCI_REGION_SYS_MEMORY|PCI_REGION_TYPE;
343 if (flags != PCI_REGION_SYS_MEMORY) {
344 u64 start = hose->regions[r].bus_start;
345 u64 end = start + hose->regions[r].size;
346
347 out_be32(&po->powbar, hose->regions[r].phys_start >> 12);
348 out_be32(&po->potar, start >> 12);
349#ifdef CONFIG_SYS_PCI_64BIT
350 out_be32(&po->potear, start >> 44);
351#else
352 out_be32(&po->potear, 0);
353#endif
354 if (hose->regions[r].flags & PCI_REGION_IO) {
355 out_be32(&po->powar, POWAR_EN | sz |
356 POWAR_IO_READ | POWAR_IO_WRITE);
357 } else {
358 out_be32(&po->powar, POWAR_EN | sz |
359 POWAR_MEM_READ | POWAR_MEM_WRITE);
360 out_lo = min(start, out_lo);
361 out_hi = max(end, out_hi);
362 }
363 po++;
364 }
365 }
366 debug("Outbound memory range: %llx:%llx\n", out_lo, out_hi);
367
368
369 pci_hose_write_config_dword(hose, dev, PCI_BASE_ADDRESS_0, 0xffffffff);
370 pci_hose_read_config_dword (hose, dev, PCI_BASE_ADDRESS_0, &pcicsrbar_sz);
371 pcicsrbar_sz = ~pcicsrbar_sz + 1;
372
373 if (out_hi < (0x100000000ull - pcicsrbar_sz) ||
374 (out_lo > 0x100000000ull))
375 pcicsrbar = 0x100000000ull - pcicsrbar_sz;
376 else
377 pcicsrbar = (out_lo - pcicsrbar_sz) & -pcicsrbar_sz;
378 pci_hose_write_config_dword(hose, dev, PCI_BASE_ADDRESS_0, pcicsrbar);
379
380 out_lo = min(out_lo, (u64)pcicsrbar);
381
382 debug("PCICSRBAR @ 0x%x\n", pcicsrbar);
383
384 pci_set_region(reg++, pcicsrbar, CONFIG_SYS_CCSRBAR_PHYS,
385 pcicsrbar_sz, PCI_REGION_SYS_MEMORY);
386 hose->region_count++;
387
388
389 pcie_cap_pos = pci_hose_find_capability(hose, dev, PCI_CAP_ID_EXP);
390 pci_dcr = pcie_cap_pos + 0x08;
391 pci_dsr = pcie_cap_pos + 0x0a;
392 pci_lsr = pcie_cap_pos + 0x12;
393
394 pci_hose_read_config_byte(hose, dev, pcie_cap_pos, &pcie_cap);
395
396#ifdef CONFIG_SRIO_PCIE_BOOT_MASTER
397
398 char *s = env_get("bootmaster");
399 char pcie[6];
400 sprintf(pcie, "PCIE%d", pci_info->pci_num);
401
402 if (s && (strcmp(s, pcie) == 0)) {
403 debug("PCIEBOOT - MASTER: Master port [ %d ] for pcie boot.\n",
404 pci_info->pci_num);
405 fsl_pcie_boot_master((pit_t *)pi);
406 } else {
407
408 inbound = fsl_pci_setup_inbound_windows(hose,
409 out_lo, pcie_cap, pi);
410 }
411#else
412
413 inbound = fsl_pci_setup_inbound_windows(hose, out_lo, pcie_cap, pi);
414#endif
415
416 for (r = 0; r < hose->region_count; r++)
417 debug("PCI reg:%d %016llx:%016llx %016llx %08lx\n", r,
418 (u64)hose->regions[r].phys_start,
419 (u64)hose->regions[r].bus_start,
420 (u64)hose->regions[r].size,
421 hose->regions[r].flags);
422
423 pci_register_hose(hose);
424 pciauto_config_init(hose);
425 hose->current_busno = hose->first_busno;
426
427 out_be32(&pci->pedr, 0xffffffff);
428 out_be32(&pci->peer, ~0x20140);
429
430
431
432
433 pci_hose_read_config_dword(hose, dev, pci_dcr, &temp32);
434 temp32 |= 0xf000e;
435 pci_hose_write_config_dword(hose, dev, pci_dcr, temp32);
436
437#if defined(CONFIG_FSL_PCIE_DISABLE_ASPM)
438 pci_lcr = pcie_cap_pos + 0x10;
439 temp32 = 0;
440 pci_hose_read_config_dword(hose, dev, pci_lcr, &temp32);
441 temp32 &= ~0x03;
442 pci_hose_write_config_dword(hose, dev, pci_lcr, temp32);
443 udelay(1);
444#endif
445 if (pcie_cap == PCI_CAP_ID_EXP) {
446 if (block_rev >= PEX_IP_BLK_REV_3_0) {
447#define PEX_CSR0_LTSSM_MASK 0xFC
448#define PEX_CSR0_LTSSM_SHIFT 2
449 ltssm = (in_be32(&pci->pex_csr0)
450 & PEX_CSR0_LTSSM_MASK) >> PEX_CSR0_LTSSM_SHIFT;
451 enabled = (ltssm == 0x11) ? 1 : 0;
452#ifdef CONFIG_FSL_PCIE_RESET
453 int i;
454
455 setbits_be32(&pci->pdb_stat, 0x08000000);
456 (void) in_be32(&pci->pdb_stat);
457 udelay(1000);
458
459 clrbits_be32(&pci->pdb_stat, 0x08000000);
460 asm("sync;isync");
461 for (i = 0; i < 100 && ltssm < PCI_LTSSM_L0; i++) {
462 pci_hose_read_config_word(hose, dev, PCI_LTSSM,
463 <ssm);
464 udelay(1000);
465 }
466#endif
467 } else {
468
469
470 pci_hose_read_config_word(hose, dev, PCI_LTSSM, <ssm);
471 enabled = ltssm >= PCI_LTSSM_L0;
472
473#ifdef CONFIG_FSL_PCIE_RESET
474 if (ltssm == 1) {
475 int i;
476 debug("....PCIe link error. " "LTSSM=0x%02x.", ltssm);
477
478 setbits_be32(&pci->pdb_stat, 0x08000000);
479 (void) in_be32(&pci->pdb_stat);
480 udelay(100);
481 debug(" Asserting PCIe reset @%p = %x\n",
482 &pci->pdb_stat, in_be32(&pci->pdb_stat));
483
484 clrbits_be32(&pci->pdb_stat, 0x08000000);
485 asm("sync;isync");
486 for (i=0; i<100 && ltssm < PCI_LTSSM_L0; i++) {
487 pci_hose_read_config_word(hose, dev, PCI_LTSSM,
488 <ssm);
489 udelay(1000);
490 debug("....PCIe link error. "
491 "LTSSM=0x%02x.\n", ltssm);
492 }
493 enabled = ltssm >= PCI_LTSSM_L0;
494
495
496
497
498 pci_hose_write_config_dword(hose, dev,
499 PCI_BASE_ADDRESS_0, pcicsrbar);
500 }
501#endif
502 }
503
504#ifdef CONFIG_SYS_P4080_ERRATUM_PCIE_A003
505 if (enabled == 0) {
506 serdes_corenet_t *srds_regs = (void *)CONFIG_SYS_FSL_CORENET_SERDES_ADDR;
507 temp32 = in_be32(&srds_regs->srdspccr0);
508
509 if ((temp32 >> 28) == 3) {
510 int i;
511
512 out_be32(&srds_regs->srdspccr0, 2 << 28);
513 setbits_be32(&pci->pdb_stat, 0x08000000);
514 in_be32(&pci->pdb_stat);
515 udelay(100);
516 clrbits_be32(&pci->pdb_stat, 0x08000000);
517 asm("sync;isync");
518 for (i=0; i < 100 && ltssm < PCI_LTSSM_L0; i++) {
519 pci_hose_read_config_word(hose, dev, PCI_LTSSM, <ssm);
520 udelay(1000);
521 }
522 enabled = ltssm >= PCI_LTSSM_L0;
523 }
524 }
525#endif
526 if (!enabled) {
527
528
529
530
531 if (fsl_is_pci_agent(hose))
532 printf("undetermined, regs @ 0x%lx\n", pci_info->regs);
533 else
534 printf("no link, regs @ 0x%lx\n", pci_info->regs);
535 hose->last_busno = hose->first_busno;
536 return;
537 }
538
539 out_be32(&pci->pme_msg_det, 0xffffffff);
540 out_be32(&pci->pme_msg_int_en, 0xffffffff);
541
542
543 pci_hose_read_config_word(hose, dev, pci_lsr, &temp16);
544 printf("x%d gen%d, regs @ 0x%lx\n", (temp16 & 0x3f0) >> 4,
545 (temp16 & 0xf), pci_info->regs);
546
547 hose->current_busno++;
548 pciauto_prescan_setup_bridge(hose, dev, hose->current_busno);
549 }
550
551#ifdef CONFIG_SYS_FSL_ERRATUM_A007815
552
553
554
555 clrbits_be32(&pci->dbi_ro_wr_en, 0x01);
556#endif
557
558
559
560
561
562 pciauto_setup_device(hose, dev, 0, hose->pci_mem,
563 hose->pci_prefetch, hose->pci_io);
564
565 if (inbound) {
566 pci_hose_read_config_word(hose, dev, PCI_COMMAND, &temp16);
567 pci_hose_write_config_word(hose, dev, PCI_COMMAND,
568 temp16 | PCI_COMMAND_MEMORY);
569 }
570
571#ifndef CONFIG_PCI_NOSCAN
572 if (!fsl_is_pci_agent(hose)) {
573 debug(" Scanning PCI bus %02x\n",
574 hose->current_busno);
575 hose->last_busno = pci_hose_scan_bus(hose, hose->current_busno);
576 } else {
577 debug(" Not scanning PCI bus %02x. PI=%x\n",
578 hose->current_busno, temp8);
579 hose->last_busno = hose->current_busno;
580 }
581
582
583
584
585 if (pcie_cap == PCI_CAP_ID_EXP) {
586 pciauto_postscan_setup_bridge(hose, dev, hose->last_busno);
587 }
588#else
589 hose->last_busno = hose->current_busno;
590#endif
591
592
593 if (pcie_cap == PCI_CAP_ID_EXP)
594 out_be32(&pci->pme_msg_det, 0xffffffff);
595 out_be32(&pci->pedr, 0xffffffff);
596
597 pci_hose_read_config_word(hose, dev, pci_dsr, &temp16);
598 if (temp16) {
599 pci_hose_write_config_word(hose, dev, pci_dsr, 0xffff);
600 }
601
602 pci_hose_read_config_word (hose, dev, PCI_SEC_STATUS, &temp16);
603 if (temp16) {
604 pci_hose_write_config_word(hose, dev, PCI_SEC_STATUS, 0xffff);
605 }
606}
607
608int fsl_is_pci_agent(struct pci_controller *hose)
609{
610 int pcie_cap_pos;
611 u8 pcie_cap;
612 pci_dev_t dev = PCI_BDF(hose->first_busno, 0, 0);
613
614 pcie_cap_pos = pci_hose_find_capability(hose, dev, PCI_CAP_ID_EXP);
615 pci_hose_read_config_byte(hose, dev, pcie_cap_pos, &pcie_cap);
616 if (pcie_cap == PCI_CAP_ID_EXP) {
617 u8 header_type;
618
619 pci_hose_read_config_byte(hose, dev, PCI_HEADER_TYPE,
620 &header_type);
621 return (header_type & 0x7f) == PCI_HEADER_TYPE_NORMAL;
622 } else {
623 u8 prog_if;
624
625 pci_hose_read_config_byte(hose, dev, PCI_CLASS_PROG, &prog_if);
626
627
628
629
630 return (prog_if == FSL_PROG_IF_AGENT);
631 }
632}
633
634int fsl_pci_init_port(struct fsl_pci_info *pci_info,
635 struct pci_controller *hose, int busno)
636{
637 volatile ccsr_fsl_pci_t *pci;
638 struct pci_region *r;
639 pci_dev_t dev = PCI_BDF(busno,0,0);
640 int pcie_cap_pos;
641 u8 pcie_cap;
642
643 pci = (ccsr_fsl_pci_t *) pci_info->regs;
644
645
646
647
648 if (in_be32(&pci->pme_msg_det)) {
649 out_be32(&pci->pme_msg_det, 0xffffffff);
650 debug (" with errors. Clearing. Now 0x%08x",
651 pci->pme_msg_det);
652 }
653
654 r = hose->regions + hose->region_count;
655
656
657 pci_set_region(r++,
658 pci_info->mem_bus,
659 pci_info->mem_phys,
660 pci_info->mem_size,
661 PCI_REGION_MEM);
662
663
664 pci_set_region(r++,
665 pci_info->io_bus,
666 pci_info->io_phys,
667 pci_info->io_size,
668 PCI_REGION_IO);
669
670 hose->region_count = r - hose->regions;
671 hose->first_busno = busno;
672
673 fsl_pci_init(hose, pci_info);
674
675 if (fsl_is_pci_agent(hose)) {
676 fsl_pci_config_unlock(hose);
677 hose->last_busno = hose->first_busno;
678#ifdef CONFIG_SRIO_PCIE_BOOT_MASTER
679 } else {
680
681 char *s = env_get("bootmaster");
682 char pcie[6];
683 sprintf(pcie, "PCIE%d", pci_info->pci_num);
684
685 if (s && (strcmp(s, pcie) == 0))
686 fsl_pcie_boot_master_release_slave(pci_info->pci_num);
687#endif
688 }
689
690 pcie_cap_pos = pci_hose_find_capability(hose, dev, PCI_CAP_ID_EXP);
691 pci_hose_read_config_byte(hose, dev, pcie_cap_pos, &pcie_cap);
692 printf("PCI%s%x: Bus %02x - %02x\n", pcie_cap == PCI_CAP_ID_EXP ?
693 "e" : "", pci_info->pci_num,
694 hose->first_busno, hose->last_busno);
695 return(hose->last_busno + 1);
696}
697
698
699void fsl_pci_config_unlock(struct pci_controller *hose)
700{
701 pci_dev_t dev = PCI_BDF(hose->first_busno,0,0);
702 int pcie_cap_pos;
703 u8 pcie_cap;
704 u16 pbfr;
705
706 if (!fsl_is_pci_agent(hose))
707 return;
708
709 pcie_cap_pos = pci_hose_find_capability(hose, dev, PCI_CAP_ID_EXP);
710 pci_hose_read_config_byte(hose, dev, pcie_cap_pos, &pcie_cap);
711 if (pcie_cap != 0x0) {
712 ccsr_fsl_pci_t *pci = (ccsr_fsl_pci_t *)hose->cfg_addr;
713 u32 block_rev = in_be32(&pci->block_rev1);
714
715 if (block_rev >= PEX_IP_BLK_REV_3_0)
716 setbits_be32(&pci->config, FSL_PCIE_V3_CFG_RDY);
717 else
718 pci_hose_write_config_byte(hose, dev,
719 FSL_PCIE_CFG_RDY, 0x1);
720 } else {
721
722 pci_hose_read_config_word(hose, dev, FSL_PCI_PBFR, &pbfr);
723 pbfr &= ~0x20;
724 pci_hose_write_config_word(hose, dev, FSL_PCI_PBFR, pbfr);
725 }
726}
727
728#if defined(CONFIG_PCIE1) || defined(CONFIG_PCIE2) || \
729 defined(CONFIG_PCIE3) || defined(CONFIG_PCIE4)
730int fsl_configure_pcie(struct fsl_pci_info *info,
731 struct pci_controller *hose,
732 const char *connected, int busno)
733{
734 int is_endpoint;
735
736 set_next_law(info->mem_phys, law_size_bits(info->mem_size), info->law);
737 set_next_law(info->io_phys, law_size_bits(info->io_size), info->law);
738
739 is_endpoint = fsl_setup_hose(hose, info->regs);
740 printf("PCIe%u: %s", info->pci_num,
741 is_endpoint ? "Endpoint" : "Root Complex");
742 if (connected)
743 printf(" of %s", connected);
744 puts(", ");
745
746 return fsl_pci_init_port(info, hose, busno);
747}
748
749#if defined(CONFIG_FSL_CORENET)
750#ifdef CONFIG_SYS_FSL_QORIQ_CHASSIS2
751 #define _DEVDISR_PCIE1 FSL_CORENET_DEVDISR3_PCIE1
752 #define _DEVDISR_PCIE2 FSL_CORENET_DEVDISR3_PCIE2
753 #define _DEVDISR_PCIE3 FSL_CORENET_DEVDISR3_PCIE3
754 #define _DEVDISR_PCIE4 FSL_CORENET_DEVDISR3_PCIE4
755#else
756 #define _DEVDISR_PCIE1 FSL_CORENET_DEVDISR_PCIE1
757 #define _DEVDISR_PCIE2 FSL_CORENET_DEVDISR_PCIE2
758 #define _DEVDISR_PCIE3 FSL_CORENET_DEVDISR_PCIE3
759 #define _DEVDISR_PCIE4 FSL_CORENET_DEVDISR_PCIE4
760#endif
761 #define CONFIG_SYS_MPC8xxx_GUTS_ADDR CONFIG_SYS_MPC85xx_GUTS_ADDR
762#elif defined(CONFIG_MPC85xx)
763 #define _DEVDISR_PCIE1 MPC85xx_DEVDISR_PCIE
764 #define _DEVDISR_PCIE2 MPC85xx_DEVDISR_PCIE2
765 #define _DEVDISR_PCIE3 MPC85xx_DEVDISR_PCIE3
766 #define _DEVDISR_PCIE4 0
767 #define CONFIG_SYS_MPC8xxx_GUTS_ADDR CONFIG_SYS_MPC85xx_GUTS_ADDR
768#elif defined(CONFIG_MPC86xx)
769 #define _DEVDISR_PCIE1 MPC86xx_DEVDISR_PCIE1
770 #define _DEVDISR_PCIE2 MPC86xx_DEVDISR_PCIE2
771 #define _DEVDISR_PCIE3 0
772 #define _DEVDISR_PCIE4 0
773 #define CONFIG_SYS_MPC8xxx_GUTS_ADDR \
774 (&((immap_t *)CONFIG_SYS_IMMR)->im_gur)
775#else
776#error "No defines for DEVDISR_PCIE"
777#endif
778
779
780static const char *__board_serdes_name(enum srds_prtcl device)
781{
782 switch (device) {
783#ifdef CONFIG_SYS_PCIE1_NAME
784 case PCIE1:
785 return CONFIG_SYS_PCIE1_NAME;
786#endif
787#ifdef CONFIG_SYS_PCIE2_NAME
788 case PCIE2:
789 return CONFIG_SYS_PCIE2_NAME;
790#endif
791#ifdef CONFIG_SYS_PCIE3_NAME
792 case PCIE3:
793 return CONFIG_SYS_PCIE3_NAME;
794#endif
795#ifdef CONFIG_SYS_PCIE4_NAME
796 case PCIE4:
797 return CONFIG_SYS_PCIE4_NAME;
798#endif
799 default:
800 return NULL;
801 }
802
803 return NULL;
804}
805
806__attribute__((weak, alias("__board_serdes_name"))) const char *
807board_serdes_name(enum srds_prtcl device);
808
809static u32 devdisr_mask[] = {
810 _DEVDISR_PCIE1,
811 _DEVDISR_PCIE2,
812 _DEVDISR_PCIE3,
813 _DEVDISR_PCIE4,
814};
815
816int fsl_pcie_init_ctrl(int busno, u32 devdisr, enum srds_prtcl dev,
817 struct fsl_pci_info *pci_info)
818{
819 struct pci_controller *hose;
820 int num = dev - PCIE1;
821
822 hose = calloc(1, sizeof(struct pci_controller));
823 if (!hose)
824 return busno;
825
826 if (is_serdes_configured(dev) && !(devdisr & devdisr_mask[num])) {
827 busno = fsl_configure_pcie(pci_info, hose,
828 board_serdes_name(dev), busno);
829 } else {
830 printf("PCIe%d: disabled\n", num + 1);
831 }
832
833 return busno;
834}
835
836int fsl_pcie_init_board(int busno)
837{
838 struct fsl_pci_info pci_info;
839 ccsr_gur_t *gur = (void *)CONFIG_SYS_MPC8xxx_GUTS_ADDR;
840 u32 devdisr;
841 u32 *addr;
842
843#ifdef CONFIG_SYS_FSL_QORIQ_CHASSIS2
844 addr = &gur->devdisr3;
845#else
846 addr = &gur->devdisr;
847#endif
848 devdisr = in_be32(addr);
849
850#ifdef CONFIG_PCIE1
851 SET_STD_PCIE_INFO(pci_info, 1);
852 busno = fsl_pcie_init_ctrl(busno, devdisr, PCIE1, &pci_info);
853#else
854 setbits_be32(addr, _DEVDISR_PCIE1);
855#endif
856
857#ifdef CONFIG_PCIE2
858 SET_STD_PCIE_INFO(pci_info, 2);
859 busno = fsl_pcie_init_ctrl(busno, devdisr, PCIE2, &pci_info);
860#else
861 setbits_be32(addr, _DEVDISR_PCIE2);
862#endif
863
864#ifdef CONFIG_PCIE3
865 SET_STD_PCIE_INFO(pci_info, 3);
866 busno = fsl_pcie_init_ctrl(busno, devdisr, PCIE3, &pci_info);
867#else
868 setbits_be32(addr, _DEVDISR_PCIE3);
869#endif
870
871#ifdef CONFIG_PCIE4
872 SET_STD_PCIE_INFO(pci_info, 4);
873 busno = fsl_pcie_init_ctrl(busno, devdisr, PCIE4, &pci_info);
874#else
875 setbits_be32(addr, _DEVDISR_PCIE4);
876#endif
877
878 return busno;
879}
880#else
881int fsl_pcie_init_ctrl(int busno, u32 devdisr, enum srds_prtcl dev,
882 struct fsl_pci_info *pci_info)
883{
884 return busno;
885}
886
887int fsl_pcie_init_board(int busno)
888{
889 return busno;
890}
891#endif
892
893#ifdef CONFIG_OF_BOARD_SETUP
894#include <linux/libfdt.h>
895#include <fdt_support.h>
896
897void ft_fsl_pci_setup(void *blob, const char *pci_compat,
898 unsigned long ctrl_addr)
899{
900 int off;
901 u32 bus_range[2];
902 phys_addr_t p_ctrl_addr = (phys_addr_t)ctrl_addr;
903 struct pci_controller *hose;
904
905 hose = find_hose_by_cfg_addr((void *)(ctrl_addr));
906
907
908 p_ctrl_addr = (phys_addr_t)ctrl_addr - CONFIG_SYS_CCSRBAR;
909 p_ctrl_addr += CONFIG_SYS_CCSRBAR_PHYS;
910
911 off = fdt_node_offset_by_compat_reg(blob, pci_compat, p_ctrl_addr);
912
913 if (off < 0)
914 return;
915
916
917 if ((hose == NULL) || (hose->cfg_addr == NULL)) {
918 fdt_del_node(blob, off);
919 } else {
920 bus_range[0] = 0;
921 bus_range[1] = hose->last_busno - hose->first_busno;
922 fdt_setprop(blob, off, "bus-range", &bus_range[0], 2*4);
923 fdt_pci_dma_ranges(blob, off, hose);
924 }
925}
926#endif
927
