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6#include <common.h>
7#include <dm.h>
8#include <errno.h>
9#include <i2c.h>
10#include <edid.h>
11#include <video_bridge.h>
12#include "../anx98xx-edp.h"
13
14#define DP_MAX_LINK_RATE 0x001
15#define DP_MAX_LANE_COUNT 0x002
16#define DP_MAX_LANE_COUNT_MASK 0x1f
17
18struct anx6345_priv {
19 u8 edid[EDID_SIZE];
20};
21
22static int anx6345_write(struct udevice *dev, unsigned int addr_off,
23 unsigned char reg_addr, unsigned char value)
24{
25 uint8_t buf[2];
26 struct i2c_msg msg;
27 int ret;
28
29 msg.addr = addr_off;
30 msg.flags = 0;
31 buf[0] = reg_addr;
32 buf[1] = value;
33 msg.buf = buf;
34 msg.len = 2;
35 ret = dm_i2c_xfer(dev, &msg, 1);
36 if (ret) {
37 debug("%s: write failed, reg=%#x, value=%#x, ret=%d\n",
38 __func__, reg_addr, value, ret);
39 return ret;
40 }
41
42 return 0;
43}
44
45static int anx6345_read(struct udevice *dev, unsigned int addr_off,
46 unsigned char reg_addr, unsigned char *value)
47{
48 uint8_t addr, val;
49 struct i2c_msg msg[2];
50 int ret;
51
52 msg[0].addr = addr_off;
53 msg[0].flags = 0;
54 addr = reg_addr;
55 msg[0].buf = &addr;
56 msg[0].len = 1;
57 msg[1].addr = addr_off;
58 msg[1].flags = I2C_M_RD;
59 msg[1].buf = &val;
60 msg[1].len = 1;
61 ret = dm_i2c_xfer(dev, msg, 2);
62 if (ret) {
63 debug("%s: read failed, reg=%.2x, value=%p, ret=%d\n",
64 __func__, (int)reg_addr, value, ret);
65 return ret;
66 }
67 *value = val;
68
69 return 0;
70}
71
72static int anx6345_write_r0(struct udevice *dev, unsigned char reg_addr,
73 unsigned char value)
74{
75 struct dm_i2c_chip *chip = dev_get_parent_platdata(dev);
76
77 return anx6345_write(dev, chip->chip_addr, reg_addr, value);
78}
79
80static int anx6345_read_r0(struct udevice *dev, unsigned char reg_addr,
81 unsigned char *value)
82{
83 struct dm_i2c_chip *chip = dev_get_parent_platdata(dev);
84
85 return anx6345_read(dev, chip->chip_addr, reg_addr, value);
86}
87
88static int anx6345_write_r1(struct udevice *dev, unsigned char reg_addr,
89 unsigned char value)
90{
91 struct dm_i2c_chip *chip = dev_get_parent_platdata(dev);
92
93 return anx6345_write(dev, chip->chip_addr + 1, reg_addr, value);
94}
95
96static int anx6345_read_r1(struct udevice *dev, unsigned char reg_addr,
97 unsigned char *value)
98{
99 struct dm_i2c_chip *chip = dev_get_parent_platdata(dev);
100
101 return anx6345_read(dev, chip->chip_addr + 1, reg_addr, value);
102}
103
104static int anx6345_set_backlight(struct udevice *dev, int percent)
105{
106 return -ENOSYS;
107}
108
109static int anx6345_aux_wait(struct udevice *dev)
110{
111 int ret = -ETIMEDOUT;
112 u8 v;
113 int retries = 1000;
114
115 do {
116 anx6345_read_r0(dev, ANX9804_DP_AUX_CH_CTL_2, &v);
117 if (!(v & ANX9804_AUX_EN)) {
118 ret = 0;
119 break;
120 }
121 udelay(100);
122 } while (retries--);
123
124 if (ret) {
125 debug("%s: timed out waiting for AUX_EN to clear\n", __func__);
126 return ret;
127 }
128
129 ret = -ETIMEDOUT;
130 retries = 1000;
131 do {
132 anx6345_read_r1(dev, ANX9804_DP_INT_STA, &v);
133 if (v & ANX9804_RPLY_RECEIV) {
134 ret = 0;
135 break;
136 }
137 udelay(100);
138 } while (retries--);
139
140 if (ret) {
141 debug("%s: timed out waiting to receive reply\n", __func__);
142 return ret;
143 }
144
145
146 anx6345_write_r1(dev, ANX9804_DP_INT_STA, v);
147
148 anx6345_read_r0(dev, ANX9804_AUX_CH_STA, &v);
149 if ((v & ANX9804_AUX_STATUS_MASK) != 0) {
150 debug("AUX status: %d\n", v & ANX9804_AUX_STATUS_MASK);
151 ret = -EIO;
152 }
153
154 return ret;
155}
156
157static void anx6345_aux_addr(struct udevice *dev, u32 addr)
158{
159 u8 val;
160
161 val = addr & 0xff;
162 anx6345_write_r0(dev, ANX9804_DP_AUX_ADDR_7_0, val);
163 val = (addr >> 8) & 0xff;
164 anx6345_write_r0(dev, ANX9804_DP_AUX_ADDR_15_8, val);
165 val = (addr >> 16) & 0x0f;
166 anx6345_write_r0(dev, ANX9804_DP_AUX_ADDR_19_16, val);
167}
168
169static int anx6345_aux_transfer(struct udevice *dev, u8 req,
170 u32 addr, u8 *buf, size_t len)
171{
172 int i, ret;
173 u8 ctrl1 = req;
174 u8 ctrl2 = ANX9804_AUX_EN;
175
176 if (len > 16)
177 return -E2BIG;
178
179 if (len)
180 ctrl1 |= ANX9804_AUX_LENGTH(len);
181 else
182 ctrl2 |= ANX9804_ADDR_ONLY;
183
184 if (len && !(req & ANX9804_AUX_TX_COMM_READ)) {
185 for (i = 0; i < len; i++)
186 anx6345_write_r0(dev, ANX9804_BUF_DATA_0 + i, buf[i]);
187 }
188
189 anx6345_aux_addr(dev, addr);
190 anx6345_write_r0(dev, ANX9804_DP_AUX_CH_CTL_1, ctrl1);
191 anx6345_write_r0(dev, ANX9804_DP_AUX_CH_CTL_2, ctrl2);
192 ret = anx6345_aux_wait(dev);
193 if (ret) {
194 debug("AUX transaction timed out\n");
195 return ret;
196 }
197
198 if (len && (req & ANX9804_AUX_TX_COMM_READ)) {
199 for (i = 0; i < len; i++)
200 anx6345_read_r0(dev, ANX9804_BUF_DATA_0 + i, &buf[i]);
201 }
202
203 return 0;
204}
205
206static int anx6345_read_aux_i2c(struct udevice *dev, u8 chip_addr,
207 u8 offset, size_t count, u8 *buf)
208{
209 int i, ret;
210 size_t cur_cnt;
211 u8 cur_offset;
212
213 for (i = 0; i < count; i += 16) {
214 cur_cnt = (count - i) > 16 ? 16 : count - i;
215 cur_offset = offset + i;
216 ret = anx6345_aux_transfer(dev, ANX9804_AUX_TX_COMM_MOT,
217 chip_addr, &cur_offset, 1);
218 if (ret) {
219 debug("%s: failed to set i2c offset: %d\n",
220 __func__, ret);
221 return ret;
222 }
223 ret = anx6345_aux_transfer(dev, ANX9804_AUX_TX_COMM_READ,
224 chip_addr, buf + i, cur_cnt);
225 if (ret) {
226 debug("%s: failed to read from i2c device: %d\n",
227 __func__, ret);
228 return ret;
229 }
230 }
231
232 return 0;
233}
234
235static int anx6345_read_dpcd(struct udevice *dev, u32 reg, u8 *val)
236{
237 int ret;
238
239 ret = anx6345_aux_transfer(dev,
240 ANX9804_AUX_TX_COMM_READ |
241 ANX9804_AUX_TX_COMM_DP_TRANSACTION,
242 reg, val, 1);
243 if (ret) {
244 debug("Failed to read DPCD\n");
245 return ret;
246 }
247
248 return 0;
249}
250
251static int anx6345_read_edid(struct udevice *dev, u8 *buf, int size)
252{
253 struct anx6345_priv *priv = dev_get_priv(dev);
254
255 if (size > EDID_SIZE)
256 size = EDID_SIZE;
257 memcpy(buf, priv->edid, size);
258
259 return size;
260}
261
262static int anx6345_attach(struct udevice *dev)
263{
264
265 return 0;
266}
267
268static int anx6345_enable(struct udevice *dev)
269{
270 u8 chipid, colordepth, lanes, data_rate, c;
271 int ret, i, bpp;
272 struct display_timing timing;
273 struct anx6345_priv *priv = dev_get_priv(dev);
274
275
276 ret = video_bridge_set_active(dev, true);
277 if (ret)
278 return ret;
279
280
281 anx6345_write_r1(dev, ANX9804_RST_CTRL_REG, 1);
282 mdelay(100);
283 anx6345_write_r1(dev, ANX9804_RST_CTRL_REG, 0);
284
285
286 anx6345_write_r1(dev, ANX9804_POWERD_CTRL_REG, 0);
287
288 ret = anx6345_read_r1(dev, ANX9804_DEV_IDH_REG, &chipid);
289 if (ret)
290 debug("%s: read id failed: %d\n", __func__, ret);
291
292 switch (chipid) {
293 case 0x63:
294 debug("ANX63xx detected.\n");
295 break;
296 default:
297 debug("Error anx6345 chipid mismatch: %.2x\n", (int)chipid);
298 return -ENODEV;
299 }
300
301 for (i = 0; i < 100; i++) {
302 anx6345_read_r0(dev, ANX9804_SYS_CTRL2_REG, &c);
303 anx6345_write_r0(dev, ANX9804_SYS_CTRL2_REG, c);
304 anx6345_read_r0(dev, ANX9804_SYS_CTRL2_REG, &c);
305 if ((c & ANX9804_SYS_CTRL2_CHA_STA) == 0)
306 break;
307
308 mdelay(5);
309 }
310 if (i == 100)
311 debug("Error anx6345 clock is not stable\n");
312
313
314 anx6345_write_r0(dev, ANX9804_PLL_CTRL_REG, 0x00);
315 anx6345_write_r1(dev, ANX9804_ANALOG_DEBUG_REG1, 0x70);
316 anx6345_write_r0(dev, ANX9804_LINK_DEBUG_REG, 0x30);
317
318
319 anx6345_write_r0(dev, ANX9804_SYS_CTRL3_REG,
320 ANX9804_SYS_CTRL3_F_HPD | ANX9804_SYS_CTRL3_HPD_CTRL);
321
322
323 anx6345_write_r0(dev, ANX9804_ANALOG_POWER_DOWN_REG, 0x00);
324 anx6345_write_r0(dev, ANX9804_TRAINING_LANE0_SET_REG, 0x00);
325 anx6345_write_r0(dev, ANX9804_TRAINING_LANE1_SET_REG, 0x00);
326 anx6345_write_r0(dev, ANX9804_TRAINING_LANE2_SET_REG, 0x00);
327 anx6345_write_r0(dev, ANX9804_TRAINING_LANE3_SET_REG, 0x00);
328
329
330 anx6345_write_r1(dev, ANX9804_RST_CTRL2_REG,
331 ANX9804_RST_CTRL2_AUX);
332 anx6345_write_r1(dev, ANX9804_RST_CTRL2_REG, 0);
333
334
335 anx6345_write_r1(dev, ANX9804_POWERD_CTRL_REG, ANX9804_POWERD_AUDIO);
336 anx6345_write_r0(dev, ANX9804_HDCP_CONTROL_0_REG, 0x00);
337 anx6345_write_r0(dev, 0xa7, 0x00);
338
339 anx6345_read_aux_i2c(dev, 0x50, 0x0, EDID_SIZE, priv->edid);
340 if (edid_get_timing(priv->edid, EDID_SIZE, &timing, &bpp) != 0) {
341 debug("Failed to parse EDID\n");
342 return -EIO;
343 }
344 debug("%s: panel found: %dx%d, bpp %d\n", __func__,
345 timing.hactive.typ, timing.vactive.typ, bpp);
346 if (bpp == 6)
347 colordepth = 0x00;
348 else
349 colordepth = 0x10;
350 anx6345_write_r1(dev, ANX9804_VID_CTRL2_REG, colordepth);
351
352 if (anx6345_read_dpcd(dev, DP_MAX_LINK_RATE, &data_rate)) {
353 debug("%s: Failed to DP_MAX_LINK_RATE\n", __func__);
354 return -EIO;
355 }
356 debug("%s: data_rate: %d\n", __func__, (int)data_rate);
357 if (anx6345_read_dpcd(dev, DP_MAX_LANE_COUNT, &lanes)) {
358 debug("%s: Failed to read DP_MAX_LANE_COUNT\n", __func__);
359 return -EIO;
360 }
361 lanes &= DP_MAX_LANE_COUNT_MASK;
362 debug("%s: lanes: %d\n", __func__, (int)lanes);
363
364
365 anx6345_write_r0(dev, ANX9804_LINK_BW_SET_REG, data_rate);
366 anx6345_write_r0(dev, ANX9804_LANE_COUNT_SET_REG, lanes);
367
368
369 anx6345_write_r0(dev, ANX9804_LINK_TRAINING_CTRL_REG,
370 ANX9804_LINK_TRAINING_CTRL_EN);
371 mdelay(5);
372 for (i = 0; i < 100; i++) {
373 anx6345_read_r0(dev, ANX9804_LINK_TRAINING_CTRL_REG, &c);
374 if ((chipid == 0x63) && (c & 0x80) == 0)
375 break;
376
377 mdelay(5);
378 }
379 if (i == 100) {
380 debug("Error anx6345 link training timeout\n");
381 return -ENODEV;
382 }
383
384
385 anx6345_write_r1(dev, ANX9804_VID_CTRL1_REG,
386 ANX9804_VID_CTRL1_VID_EN | ANX9804_VID_CTRL1_EDGE);
387
388 anx6345_write_r0(dev, ANX9804_SYS_CTRL3_REG,
389 ANX9804_SYS_CTRL3_F_HPD |
390 ANX9804_SYS_CTRL3_HPD_CTRL |
391 ANX9804_SYS_CTRL3_F_VALID |
392 ANX9804_SYS_CTRL3_VALID_CTRL);
393
394 return 0;
395}
396
397static int anx6345_probe(struct udevice *dev)
398{
399 if (device_get_uclass_id(dev->parent) != UCLASS_I2C)
400 return -EPROTONOSUPPORT;
401
402 return anx6345_enable(dev);
403}
404
405struct video_bridge_ops anx6345_ops = {
406 .attach = anx6345_attach,
407 .set_backlight = anx6345_set_backlight,
408 .read_edid = anx6345_read_edid,
409};
410
411static const struct udevice_id anx6345_ids[] = {
412 { .compatible = "analogix,anx6345", },
413 { }
414};
415
416U_BOOT_DRIVER(analogix_anx6345) = {
417 .name = "analogix_anx6345",
418 .id = UCLASS_VIDEO_BRIDGE,
419 .of_match = anx6345_ids,
420 .probe = anx6345_probe,
421 .ops = &anx6345_ops,
422 .priv_auto_alloc_size = sizeof(struct anx6345_priv),
423};
424
