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8#ifndef __CONFIG_H
9#define __CONFIG_H
10
11
12
13
14#define CONFIG_E300 1
15#define CONFIG_MPC830x 1
16#define CONFIG_MPC8308 1
17
18#ifdef CONFIG_MMC
19#define CONFIG_SYS_FSL_ESDHC_ADDR CONFIG_SYS_MPC83xx_ESDHC_ADDR
20#define CONFIG_SYS_FSL_ESDHC_USE_PIO
21#endif
22
23
24
25
26
27
28
29#define CONFIG_TSEC1
30#define CONFIG_VSC7385_ENET
31
32
33
34
35#define CONFIG_83XX_CLKIN 33333333
36#define CONFIG_SYS_CLK_FREQ CONFIG_83XX_CLKIN
37
38
39
40
41
42
43
44#define CONFIG_SYS_HRCW_LOW (\
45 HRCWL_LCL_BUS_TO_SCB_CLK_1X1 |\
46 HRCWL_DDR_TO_SCB_CLK_2X1 |\
47 HRCWL_SVCOD_DIV_2 |\
48 HRCWL_CSB_TO_CLKIN_4X1 |\
49 HRCWL_CORE_TO_CSB_3X1)
50
51
52
53
54
55
56
57#define CONFIG_SYS_HRCW_HIGH (\
58 HRCWH_PCI_HOST |\
59 HRCWH_PCI1_ARBITER_ENABLE |\
60 HRCWH_CORE_ENABLE |\
61 HRCWH_FROM_0X00000100 |\
62 HRCWH_BOOTSEQ_DISABLE |\
63 HRCWH_SW_WATCHDOG_DISABLE |\
64 HRCWH_ROM_LOC_LOCAL_16BIT |\
65 HRCWH_RL_EXT_LEGACY |\
66 HRCWH_TSEC1M_IN_RGMII |\
67 HRCWH_TSEC2M_IN_RGMII |\
68 HRCWH_BIG_ENDIAN)
69
70
71
72
73#define CONFIG_SYS_SICRH (\
74 SICRH_ESDHC_A_SD |\
75 SICRH_ESDHC_B_SD |\
76 SICRH_ESDHC_C_SD |\
77 SICRH_GPIO_A_TSEC2 |\
78 SICRH_GPIO_B_TSEC2_GTX_CLK125 |\
79 SICRH_IEEE1588_A_GPIO |\
80 SICRH_USB |\
81 SICRH_GTM_GPIO |\
82 SICRH_IEEE1588_B_GPIO |\
83 SICRH_ETSEC2_CRS |\
84 SICRH_GPIOSEL_1 |\
85 SICRH_TMROBI_V3P3 |\
86 SICRH_TSOBI1_V2P5 |\
87 SICRH_TSOBI2_V2P5)
88#define CONFIG_SYS_SICRL (\
89 SICRL_SPI_PF0 |\
90 SICRL_UART_PF0 |\
91 SICRL_IRQ_PF0 |\
92 SICRL_I2C2_PF0 |\
93 SICRL_ETSEC1_GTX_CLK125)
94
95
96
97
98#define CONFIG_SYS_IMMR 0xE0000000
99
100
101
102
103#define CONFIG_FSL_SERDES
104#define CONFIG_FSL_SERDES1 0xe3000
105
106
107
108
109#define CONFIG_SYS_ACR_PIPE_DEP 3
110#define CONFIG_SYS_ACR_RPTCNT 3
111#define CONFIG_SYS_SPCR_TSECEP 3
112
113
114
115
116#define CONFIG_SYS_DDR_BASE 0x00000000
117#define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_BASE
118#define CONFIG_SYS_DDR_SDRAM_BASE CONFIG_SYS_DDR_BASE
119#define CONFIG_SYS_DDR_SDRAM_CLK_CNTL DDR_SDRAM_CLK_CNTL_CLK_ADJUST_05
120#define CONFIG_SYS_DDRCDR_VALUE (DDRCDR_EN \
121 | DDRCDR_PZ_LOZ \
122 | DDRCDR_NZ_LOZ \
123 | DDRCDR_ODT \
124 | DDRCDR_Q_DRN)
125
126
127
128
129
130
131#define CONFIG_SYS_DDR_SIZE 128
132
133#define CONFIG_SYS_DDR_CS0_BNDS 0x00000007
134#define CONFIG_SYS_DDR_CS0_CONFIG (CSCONFIG_EN \
135 | CSCONFIG_ODT_RD_NEVER \
136 | CSCONFIG_ODT_WR_ONLY_CURRENT \
137 | CSCONFIG_ROW_BIT_13 | CSCONFIG_COL_BIT_10)
138
139#define CONFIG_SYS_DDR_TIMING_3 0x00000000
140#define CONFIG_SYS_DDR_TIMING_0 ((0 << TIMING_CFG0_RWT_SHIFT) \
141 | (0 << TIMING_CFG0_WRT_SHIFT) \
142 | (0 << TIMING_CFG0_RRT_SHIFT) \
143 | (0 << TIMING_CFG0_WWT_SHIFT) \
144 | (2 << TIMING_CFG0_ACT_PD_EXIT_SHIFT) \
145 | (2 << TIMING_CFG0_PRE_PD_EXIT_SHIFT) \
146 | (8 << TIMING_CFG0_ODT_PD_EXIT_SHIFT) \
147 | (2 << TIMING_CFG0_MRS_CYC_SHIFT))
148
149#define CONFIG_SYS_DDR_TIMING_1 ((2 << TIMING_CFG1_PRETOACT_SHIFT) \
150 | (7 << TIMING_CFG1_ACTTOPRE_SHIFT) \
151 | (2 << TIMING_CFG1_ACTTORW_SHIFT) \
152 | (5 << TIMING_CFG1_CASLAT_SHIFT) \
153 | (6 << TIMING_CFG1_REFREC_SHIFT) \
154 | (2 << TIMING_CFG1_WRREC_SHIFT) \
155 | (2 << TIMING_CFG1_ACTTOACT_SHIFT) \
156 | (2 << TIMING_CFG1_WRTORD_SHIFT))
157
158#define CONFIG_SYS_DDR_TIMING_2 ((1 << TIMING_CFG2_ADD_LAT_SHIFT) \
159 | (4 << TIMING_CFG2_CPO_SHIFT) \
160 | (2 << TIMING_CFG2_WR_LAT_DELAY_SHIFT) \
161 | (2 << TIMING_CFG2_RD_TO_PRE_SHIFT) \
162 | (2 << TIMING_CFG2_WR_DATA_DELAY_SHIFT) \
163 | (3 << TIMING_CFG2_CKE_PLS_SHIFT) \
164 | (5 << TIMING_CFG2_FOUR_ACT_SHIFT))
165
166#define CONFIG_SYS_DDR_INTERVAL ((0x0360 << SDRAM_INTERVAL_REFINT_SHIFT) \
167 | (0x0100 << SDRAM_INTERVAL_BSTOPRE_SHIFT))
168
169#define CONFIG_SYS_DDR_SDRAM_CFG (SDRAM_CFG_SREN \
170 | SDRAM_CFG_SDRAM_TYPE_DDR2 \
171 | SDRAM_CFG_DBW_32)
172
173
174#define CONFIG_SYS_DDR_SDRAM_CFG2 0x00401000
175#define CONFIG_SYS_DDR_MODE ((0x0448 << SDRAM_MODE_ESD_SHIFT) \
176 | (0x0232 << SDRAM_MODE_SD_SHIFT))
177
178#define CONFIG_SYS_DDR_MODE2 0x00000000
179
180
181
182
183#define CONFIG_SYS_MEMTEST_START 0x00001000
184#define CONFIG_SYS_MEMTEST_END 0x07f00000
185
186
187
188
189#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE
190
191#define CONFIG_SYS_MONITOR_LEN (512 * 1024)
192#define CONFIG_SYS_MALLOC_LEN (512 * 1024)
193
194
195
196
197#define CONFIG_SYS_INIT_RAM_LOCK 1
198#define CONFIG_SYS_INIT_RAM_ADDR 0xE6000000
199#define CONFIG_SYS_INIT_RAM_SIZE 0x1000
200#define CONFIG_SYS_GBL_DATA_OFFSET \
201 (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
202
203
204
205
206#define CONFIG_SYS_LCRR_DBYP LCRR_DBYP
207#define CONFIG_SYS_LCRR_CLKDIV LCRR_CLKDIV_2
208#define CONFIG_SYS_LBC_LBCR 0x00040000
209
210
211
212
213#define CONFIG_SYS_FLASH_CFI
214#define CONFIG_FLASH_CFI_DRIVER
215#define CONFIG_SYS_FLASH_CFI_WIDTH FLASH_CFI_16BIT
216
217#define CONFIG_SYS_FLASH_BASE 0xFE000000
218#define CONFIG_SYS_FLASH_SIZE 8
219#define CONFIG_SYS_FLASH_PROTECTION 1
220
221
222#define CONFIG_SYS_LBLAWBAR0_PRELIM CONFIG_SYS_FLASH_BASE
223#define CONFIG_SYS_LBLAWAR0_PRELIM (LBLAWAR_EN | LBLAWAR_8MB)
224
225#define CONFIG_SYS_BR0_PRELIM (CONFIG_SYS_FLASH_BASE \
226 | BR_PS_16 \
227 | BR_MS_GPCM \
228 | BR_V)
229#define CONFIG_SYS_OR0_PRELIM (MEG_TO_AM(CONFIG_SYS_FLASH_SIZE) \
230 | OR_UPM_XAM \
231 | OR_GPCM_CSNT \
232 | OR_GPCM_ACS_DIV2 \
233 | OR_GPCM_XACS \
234 | OR_GPCM_SCY_15 \
235 | OR_GPCM_TRLX_SET \
236 | OR_GPCM_EHTR_SET)
237
238#define CONFIG_SYS_MAX_FLASH_BANKS 1
239
240#define CONFIG_SYS_MAX_FLASH_SECT 135
241
242#define CONFIG_SYS_FLASH_ERASE_TOUT 60000
243#define CONFIG_SYS_FLASH_WRITE_TOUT 500
244
245
246
247
248#define CONFIG_SYS_NAND_BASE 0xE0600000
249#define CONFIG_SYS_NAND_WINDOW_SIZE (32 * 1024)
250#define CONFIG_SYS_BR1_PRELIM (CONFIG_SYS_NAND_BASE \
251 | BR_DECC_CHK_GEN \
252 | BR_PS_8 \
253 | BR_MS_FCM \
254 | BR_V)
255#define CONFIG_SYS_OR1_PRELIM (P2SZ_TO_AM(CONFIG_SYS_NAND_WINDOW_SIZE) \
256 | OR_FCM_CSCT \
257 | OR_FCM_CST \
258 | OR_FCM_CHT \
259 | OR_FCM_SCY_1 \
260 | OR_FCM_TRLX \
261 | OR_FCM_EHTR)
262
263
264#define CONFIG_SYS_LBLAWBAR1_PRELIM CONFIG_SYS_NAND_BASE
265#define CONFIG_SYS_LBLAWAR1_PRELIM (LBLAWAR_EN | LBLAWAR_32KB)
266
267#ifdef CONFIG_VSC7385_ENET
268#define CONFIG_TSEC2
269
270#define CONFIG_SYS_VSC7385_BASE 0xF0000000
271#define CONFIG_SYS_VSC7385_SIZE (128 * 1024)
272#define CONFIG_SYS_BR2_PRELIM (CONFIG_SYS_VSC7385_BASE \
273 | BR_PS_8 \
274 | BR_MS_GPCM \
275 | BR_V)
276
277#define CONFIG_SYS_OR2_PRELIM (P2SZ_TO_AM(CONFIG_SYS_VSC7385_SIZE) \
278 | OR_GPCM_CSNT \
279 | OR_GPCM_XACS \
280 | OR_GPCM_SCY_15 \
281 | OR_GPCM_SETA \
282 | OR_GPCM_TRLX_SET \
283 | OR_GPCM_EHTR_SET)
284
285
286#define CONFIG_SYS_LBLAWBAR2_PRELIM CONFIG_SYS_VSC7385_BASE
287
288#define CONFIG_SYS_LBLAWAR2_PRELIM (LBLAWAR_EN | LBLAWAR_128KB)
289
290#define CONFIG_VSC7385_IMAGE 0xFE7FE000
291#define CONFIG_VSC7385_IMAGE_SIZE 8192
292#endif
293
294
295
296#define CONFIG_SYS_NS16550_SERIAL
297#define CONFIG_SYS_NS16550_REG_SIZE 1
298#define CONFIG_SYS_NS16550_CLK get_bus_freq(0)
299
300#define CONFIG_SYS_BAUDRATE_TABLE \
301 {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200}
302
303#define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_IMMR + 0x4500)
304#define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_IMMR + 0x4600)
305
306
307#define CONFIG_SYS_I2C
308#define CONFIG_SYS_I2C_FSL
309#define CONFIG_SYS_FSL_I2C_SPEED 400000
310#define CONFIG_SYS_FSL_I2C_SLAVE 0x7F
311#define CONFIG_SYS_FSL_I2C_OFFSET 0x3000
312#define CONFIG_SYS_FSL_I2C2_SPEED 400000
313#define CONFIG_SYS_FSL_I2C2_SLAVE 0x7F
314#define CONFIG_SYS_FSL_I2C2_OFFSET 0x3100
315#define CONFIG_SYS_I2C_NOPROBES { {0, 0x51} }
316
317
318
319
320
321
322
323#ifdef CONFIG_MPC8XXX_SPI
324#define CONFIG_USE_SPIFLASH
325#endif
326
327
328
329
330#define CONFIG_SYS_I2C_PCF8574A_ADDR 0x39
331
332
333
334
335#define CONFIG_RTC_DS1337
336#define CONFIG_SYS_I2C_RTC_ADDR 0x68
337
338
339
340
341
342#define CONFIG_SYS_PCIE1_BASE 0xA0000000
343#define CONFIG_SYS_PCIE1_MEM_BASE 0xA0000000
344#define CONFIG_SYS_PCIE1_MEM_PHYS 0xA0000000
345#define CONFIG_SYS_PCIE1_MEM_SIZE 0x10000000
346#define CONFIG_SYS_PCIE1_CFG_BASE 0xB0000000
347#define CONFIG_SYS_PCIE1_CFG_SIZE 0x01000000
348#define CONFIG_SYS_PCIE1_IO_BASE 0x00000000
349#define CONFIG_SYS_PCIE1_IO_PHYS 0xB1000000
350#define CONFIG_SYS_PCIE1_IO_SIZE 0x00800000
351
352
353#define CONFIG_SYS_SCCR_PCIEXP1CM 1
354
355#define CONFIG_PCI_INDIRECT_BRIDGE
356#define CONFIG_PCIE
357
358#define CONFIG_SYS_PCI_SUBSYS_VENDORID 0x1957
359#define CONFIG_83XX_GENERIC_PCIE_REGISTER_HOSES 1
360
361
362
363
364#define CONFIG_SYS_TSEC1_OFFSET 0x24000
365#define CONFIG_SYS_TSEC1 (CONFIG_SYS_IMMR+CONFIG_SYS_TSEC1_OFFSET)
366#define CONFIG_SYS_TSEC2_OFFSET 0x25000
367#define CONFIG_SYS_TSEC2 (CONFIG_SYS_IMMR+CONFIG_SYS_TSEC2_OFFSET)
368
369
370
371
372#define CONFIG_TSEC1_NAME "eTSEC0"
373#define CONFIG_TSEC2_NAME "eTSEC1"
374#define TSEC1_PHY_ADDR 2
375#define TSEC2_PHY_ADDR 1
376#define TSEC1_PHYIDX 0
377#define TSEC2_PHYIDX 0
378#define TSEC1_FLAGS TSEC_GIGABIT
379#define TSEC2_FLAGS TSEC_GIGABIT
380
381
382#define CONFIG_ETHPRIME "eTSEC0"
383
384
385
386
387#define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE + \
388 CONFIG_SYS_MONITOR_LEN)
389#define CONFIG_ENV_SECT_SIZE 0x10000
390#define CONFIG_ENV_SIZE 0x2000
391#define CONFIG_ENV_ADDR_REDUND (CONFIG_ENV_ADDR + CONFIG_ENV_SECT_SIZE)
392#define CONFIG_ENV_SIZE_REDUND CONFIG_ENV_SIZE
393
394#define CONFIG_LOADS_ECHO 1
395#define CONFIG_SYS_LOADS_BAUD_CHANGE 1
396
397
398
399
400#define CONFIG_BOOTP_BOOTFILESIZE
401
402
403
404
405
406
407
408
409#define CONFIG_SYS_LOAD_ADDR 0x2000000
410
411#define CONFIG_SYS_CBSIZE 1024
412
413
414#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE
415
416
417
418
419
420
421#define CONFIG_SYS_BOOTMAPSZ (256 << 20)
422#define CONFIG_SYS_BOOTM_LEN (64 << 20)
423
424
425
426
427#define CONFIG_SYS_HID0_INIT 0x000000000
428#define CONFIG_SYS_HID0_FINAL (HID0_ENABLE_MACHINE_CHECK | \
429 HID0_ENABLE_INSTRUCTION_CACHE | \
430 HID0_ENABLE_DYNAMIC_POWER_MANAGMENT)
431#define CONFIG_SYS_HID2 HID2_HBE
432
433
434
435
436
437
438#define CONFIG_SYS_IBAT0L (CONFIG_SYS_SDRAM_BASE | BATL_PP_RW | \
439 BATL_MEMCOHERENCE)
440#define CONFIG_SYS_IBAT0U (CONFIG_SYS_SDRAM_BASE | BATU_BL_128M | \
441 BATU_VS | BATU_VP)
442#define CONFIG_SYS_DBAT0L CONFIG_SYS_IBAT0L
443#define CONFIG_SYS_DBAT0U CONFIG_SYS_IBAT0U
444
445
446#define CONFIG_SYS_IBAT1L (CONFIG_SYS_IMMR | BATL_PP_RW | \
447 BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE)
448#define CONFIG_SYS_IBAT1U (CONFIG_SYS_IMMR | BATU_BL_8M | BATU_VS | \
449 BATU_VP)
450#define CONFIG_SYS_DBAT1L CONFIG_SYS_IBAT1L
451#define CONFIG_SYS_DBAT1U CONFIG_SYS_IBAT1U
452
453
454#define CONFIG_SYS_IBAT2L (CONFIG_SYS_FLASH_BASE | BATL_PP_RW | \
455 BATL_MEMCOHERENCE)
456#define CONFIG_SYS_IBAT2U (CONFIG_SYS_FLASH_BASE | BATU_BL_8M | \
457 BATU_VS | BATU_VP)
458#define CONFIG_SYS_DBAT2L (CONFIG_SYS_FLASH_BASE | BATL_PP_RW | \
459 BATL_CACHEINHIBIT | \
460 BATL_GUARDEDSTORAGE)
461#define CONFIG_SYS_DBAT2U CONFIG_SYS_IBAT2U
462
463
464#define CONFIG_SYS_IBAT3L (CONFIG_SYS_INIT_RAM_ADDR | BATL_PP_RW)
465#define CONFIG_SYS_IBAT3U (CONFIG_SYS_INIT_RAM_ADDR | BATU_BL_128K | \
466 BATU_VS | BATU_VP)
467#define CONFIG_SYS_DBAT3L CONFIG_SYS_IBAT3L
468#define CONFIG_SYS_DBAT3U CONFIG_SYS_IBAT3U
469
470
471
472
473
474#define CONFIG_ENV_OVERWRITE
475
476#if defined(CONFIG_TSEC_ENET)
477#define CONFIG_HAS_ETH0
478#define CONFIG_HAS_ETH1
479#endif
480
481#define CONFIG_LOADADDR 800000
482
483
484#define CONFIG_EXTRA_ENV_SETTINGS \
485 "netdev=eth0\0" \
486 "consoledev=ttyS0\0" \
487 "nfsargs=setenv bootargs root=/dev/nfs rw " \
488 "nfsroot=${serverip}:${rootpath}\0" \
489 "ramargs=setenv bootargs root=/dev/ram rw\0" \
490 "addip=setenv bootargs ${bootargs} " \
491 "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}" \
492 ":${hostname}:${netdev}:off panic=1\0" \
493 "addtty=setenv bootargs ${bootargs}" \
494 " console=${consoledev},${baudrate}\0" \
495 "addmtd=setenv bootargs ${bootargs} ${mtdparts}\0" \
496 "addmisc=setenv bootargs ${bootargs}\0" \
497 "kernel_addr=FE080000\0" \
498 "fdt_addr=FE280000\0" \
499 "ramdisk_addr=FE290000\0" \
500 "u-boot=mpc8308rdb/u-boot.bin\0" \
501 "kernel_addr_r=1000000\0" \
502 "fdt_addr_r=C00000\0" \
503 "hostname=mpc8308rdb\0" \
504 "bootfile=mpc8308rdb/uImage\0" \
505 "fdtfile=mpc8308rdb/mpc8308rdb.dtb\0" \
506 "rootpath=/opt/eldk-4.2/ppc_6xx\0" \
507 "flash_self=run ramargs addip addtty addmtd addmisc;" \
508 "bootm ${kernel_addr} ${ramdisk_addr} ${fdt_addr}\0" \
509 "flash_nfs=run nfsargs addip addtty addmtd addmisc;" \
510 "bootm ${kernel_addr} - ${fdt_addr}\0" \
511 "net_nfs=tftp ${kernel_addr_r} ${bootfile};" \
512 "tftp ${fdt_addr_r} ${fdtfile};" \
513 "run nfsargs addip addtty addmtd addmisc;" \
514 "bootm ${kernel_addr_r} - ${fdt_addr_r}\0" \
515 "bootcmd=run flash_self\0" \
516 "load=tftp ${loadaddr} ${u-boot}\0" \
517 "update=protect off " __stringify(CONFIG_SYS_MONITOR_BASE) \
518 " +${filesize};era " __stringify(CONFIG_SYS_MONITOR_BASE)\
519 " +${filesize};cp.b ${fileaddr} " \
520 __stringify(CONFIG_SYS_MONITOR_BASE) " ${filesize}\0" \
521 "upd=run load update\0" \
522
523#endif
524