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10#ifndef __CONFIG_H
11#define __CONFIG_H
12
13#include "../board/freescale/common/ics307_clk.h"
14
15#ifdef CONFIG_SDCARD
16#define CONFIG_RAMBOOT_SDCARD 1
17#define CONFIG_RESET_VECTOR_ADDRESS 0xf8fffffc
18#endif
19
20#ifdef CONFIG_SPIFLASH
21#define CONFIG_RAMBOOT_SPIFLASH 1
22#define CONFIG_RESET_VECTOR_ADDRESS 0xf8fffffc
23#endif
24
25#ifndef CONFIG_RESET_VECTOR_ADDRESS
26#define CONFIG_RESET_VECTOR_ADDRESS 0xeffffffc
27#endif
28
29#ifndef CONFIG_SYS_MONITOR_BASE
30#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE
31#endif
32
33#define CONFIG_PCI1 1
34#define CONFIG_PCIE1 1
35#define CONFIG_PCIE2 1
36#define CONFIG_PCIE3 1
37#define CONFIG_FSL_PCI_INIT 1
38#define CONFIG_PCI_INDIRECT_BRIDGE 1
39#define CONFIG_FSL_PCIE_RESET 1
40#define CONFIG_SYS_PCI_64BIT 1
41
42
43#define CONFIG_ENV_OVERWRITE
44
45#define CONFIG_SYS_CLK_FREQ get_board_sys_clk()
46#define CONFIG_DDR_CLK_FREQ get_board_ddr_clk()
47#define CONFIG_ICS307_REFCLK_HZ 33333000
48
49
50
51
52#define CONFIG_L2_CACHE
53#define CONFIG_BTB
54
55#define CONFIG_ENABLE_36BIT_PHYS 1
56
57#ifdef CONFIG_PHYS_64BIT
58#define CONFIG_ADDR_MAP 1
59#define CONFIG_SYS_NUM_ADDR_MAP 16
60#endif
61
62#define CONFIG_SYS_MEMTEST_START 0x00010000
63#define CONFIG_SYS_MEMTEST_END 0x1f000000
64
65
66
67
68#define CONFIG_SYS_INIT_L2_ADDR 0xf8f80000
69#ifdef CONFIG_PHYS_64BIT
70#define CONFIG_SYS_INIT_L2_ADDR_PHYS 0xff8f80000ull
71#else
72#define CONFIG_SYS_INIT_L2_ADDR_PHYS CONFIG_SYS_INIT_L2_ADDR
73#endif
74#define CONFIG_SYS_L2_SIZE (512 << 10)
75#define CONFIG_SYS_INIT_L2_END (CONFIG_SYS_INIT_L2_ADDR + CONFIG_SYS_L2_SIZE)
76
77#define CONFIG_SYS_CCSRBAR 0xffe00000
78#define CONFIG_SYS_CCSRBAR_PHYS_LOW CONFIG_SYS_CCSRBAR
79
80#if defined(CONFIG_NAND_SPL)
81#define CONFIG_SYS_CCSR_DO_NOT_RELOCATE
82#endif
83
84
85#define CONFIG_VERY_BIG_RAM
86#undef CONFIG_FSL_DDR_INTERACTIVE
87#define CONFIG_SPD_EEPROM
88#define CONFIG_DDR_SPD
89
90#define CONFIG_ECC_INIT_VIA_DDRCONTROLLER
91#define CONFIG_MEM_INIT_VALUE 0xDeadBeef
92
93#define CONFIG_SYS_DDR_SDRAM_BASE 0x00000000
94#define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE
95
96#define CONFIG_DIMM_SLOTS_PER_CTLR 1
97#define CONFIG_CHIP_SELECTS_PER_CTRL 2
98
99
100#define SPD_EEPROM_ADDRESS 0x51
101#define CONFIG_SYS_SPD_BUS_NUM 1
102
103
104#define CONFIG_SYS_SDRAM_SIZE 256
105#define CONFIG_SYS_DDR_CS0_BNDS 0x0000001F
106#define CONFIG_SYS_DDR_CS0_CONFIG 0x80010102
107#define CONFIG_SYS_DDR_TIMING_3 0x00000000
108#define CONFIG_SYS_DDR_TIMING_0 0x00260802
109#define CONFIG_SYS_DDR_TIMING_1 0x3935d322
110#define CONFIG_SYS_DDR_TIMING_2 0x14904cc8
111#define CONFIG_SYS_DDR_MODE_1 0x00480432
112#define CONFIG_SYS_DDR_MODE_2 0x00000000
113#define CONFIG_SYS_DDR_INTERVAL 0x06180100
114#define CONFIG_SYS_DDR_DATA_INIT 0xdeadbeef
115#define CONFIG_SYS_DDR_CLK_CTRL 0x03800000
116#define CONFIG_SYS_DDR_OCD_CTRL 0x00000000
117#define CONFIG_SYS_DDR_OCD_STATUS 0x00000000
118#define CONFIG_SYS_DDR_CONTROL 0xC3008000
119#define CONFIG_SYS_DDR_CONTROL2 0x04400010
120
121#define CONFIG_SYS_DDR_ERR_INT_EN 0x0000000d
122#define CONFIG_SYS_DDR_ERR_DIS 0x00000000
123#define CONFIG_SYS_DDR_SBE 0x00010000
124
125
126#ifndef CONFIG_SPD_EEPROM
127#error ("CONFIG_SPD_EEPROM is required")
128#endif
129
130#undef CONFIG_CLOCKS_IN_MHZ
131
132
133
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135
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153
154
155#define CONFIG_SYS_FLASH_BASE 0xe0000000
156#ifdef CONFIG_PHYS_64BIT
157#define CONFIG_SYS_FLASH_BASE_PHYS 0xfe0000000ull
158#else
159#define CONFIG_SYS_FLASH_BASE_PHYS CONFIG_SYS_FLASH_BASE
160#endif
161
162#define CONFIG_FLASH_BR_PRELIM \
163 (BR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS + 0x8000000) | BR_PS_16 | BR_V)
164#define CONFIG_FLASH_OR_PRELIM 0xf8000ff7
165
166#define CONFIG_SYS_BR1_PRELIM \
167 (BR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS) \
168 | BR_PS_16 | BR_V)
169#define CONFIG_SYS_OR1_PRELIM 0xf8000ff7
170
171#define CONFIG_SYS_FLASH_BANKS_LIST { CONFIG_SYS_FLASH_BASE_PHYS + 0x8000000, \
172 CONFIG_SYS_FLASH_BASE_PHYS }
173#define CONFIG_SYS_FLASH_QUIET_TEST
174#define CONFIG_FLASH_SHOW_PROGRESS 45
175
176#define CONFIG_SYS_MAX_FLASH_BANKS 2
177#define CONFIG_SYS_MAX_FLASH_SECT 1024
178#undef CONFIG_SYS_FLASH_CHECKSUM
179#define CONFIG_SYS_FLASH_ERASE_TOUT 60000
180#define CONFIG_SYS_FLASH_WRITE_TOUT 500
181
182#if defined(CONFIG_RAMBOOT_SDCARD) || defined(CONFIG_RAMBOOT_SPIFLASH)
183#define CONFIG_SYS_RAMBOOT
184#define CONFIG_SYS_EXTRA_ENV_RELOC
185#else
186#undef CONFIG_SYS_RAMBOOT
187#endif
188
189#define CONFIG_FLASH_CFI_DRIVER
190#define CONFIG_SYS_FLASH_CFI
191#define CONFIG_SYS_FLASH_EMPTY_INFO
192#define CONFIG_SYS_FLASH_AMD_CHECK_DQ7
193
194#define CONFIG_HWCONFIG
195#define CONFIG_FSL_PIXIS 1
196#define PIXIS_BASE 0xffdf0000
197#ifdef CONFIG_PHYS_64BIT
198#define PIXIS_BASE_PHYS 0xfffdf0000ull
199#else
200#define PIXIS_BASE_PHYS PIXIS_BASE
201#endif
202
203#define CONFIG_SYS_BR3_PRELIM (BR_PHYS_ADDR(PIXIS_BASE_PHYS) | BR_PS_8 | BR_V)
204#define CONFIG_SYS_OR3_PRELIM 0xffffeff7
205
206#define PIXIS_ID 0x0
207#define PIXIS_VER 0x1
208#define PIXIS_PVER 0x2
209#define PIXIS_CSR 0x3
210#define PIXIS_RST 0x4
211#define PIXIS_PWR 0x5
212#define PIXIS_AUX 0x6
213#define PIXIS_SPD 0x7
214#define PIXIS_AUX2 0x8
215#define PIXIS_VCTL 0x10
216#define PIXIS_VSTAT 0x11
217#define PIXIS_VCFGEN0 0x12
218#define PIXIS_VCFGEN1 0x13
219#define PIXIS_VCORE0 0x14
220#define PIXIS_VBOOT 0x16
221#define PIXIS_VBOOT_LBMAP 0xe0
222#define PIXIS_VBOOT_LBMAP_NOR0 0x00
223#define PIXIS_VBOOT_LBMAP_NOR1 0x01
224#define PIXIS_VBOOT_LBMAP_NOR2 0x02
225#define PIXIS_VBOOT_LBMAP_NOR3 0x03
226#define PIXIS_VBOOT_LBMAP_PJET 0x04
227#define PIXIS_VBOOT_LBMAP_NAND 0x05
228#define PIXIS_VSPEED0 0x17
229#define PIXIS_VSPEED1 0x18
230#define PIXIS_VSPEED2 0x19
231#define PIXIS_VSYSCLK0 0x1A
232#define PIXIS_VSYSCLK1 0x1B
233#define PIXIS_VSYSCLK2 0x1C
234#define PIXIS_VDDRCLK0 0x1D
235#define PIXIS_VDDRCLK1 0x1E
236#define PIXIS_VDDRCLK2 0x1F
237#define PIXIS_VWATCH 0x24
238#define PIXIS_LED 0x25
239
240#define PIXIS_SPD_SYSCLK 0x7
241
242
243#define PIXIS_VCLKH 0x19
244#define PIXIS_VCLKL 0x1A
245#define CONFIG_SYS_PIXIS_VBOOT_MASK 0x4e
246
247#define CONFIG_SYS_INIT_RAM_LOCK 1
248#define CONFIG_SYS_INIT_RAM_ADDR 0xffd00000
249#define CONFIG_SYS_INIT_RAM_SIZE 0x00004000
250
251#define CONFIG_SYS_GBL_DATA_OFFSET \
252 (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
253#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
254
255#define CONFIG_SYS_MONITOR_LEN (256 * 1024)
256#define CONFIG_SYS_MALLOC_LEN (1024 * 1024)
257
258#ifndef CONFIG_NAND_SPL
259#define CONFIG_SYS_NAND_BASE 0xffa00000
260#ifdef CONFIG_PHYS_64BIT
261#define CONFIG_SYS_NAND_BASE_PHYS 0xfffa00000ull
262#else
263#define CONFIG_SYS_NAND_BASE_PHYS CONFIG_SYS_NAND_BASE
264#endif
265#else
266#define CONFIG_SYS_NAND_BASE 0xfff00000
267#ifdef CONFIG_PHYS_64BIT
268#define CONFIG_SYS_NAND_BASE_PHYS 0xffff00000ull
269#else
270#define CONFIG_SYS_NAND_BASE_PHYS CONFIG_SYS_NAND_BASE
271#endif
272#endif
273#define CONFIG_SYS_NAND_BASE_LIST { CONFIG_SYS_NAND_BASE,\
274 CONFIG_SYS_NAND_BASE + 0x40000, \
275 CONFIG_SYS_NAND_BASE + 0x80000, \
276 CONFIG_SYS_NAND_BASE + 0xC0000}
277#define CONFIG_SYS_MAX_NAND_DEVICE 4
278#define CONFIG_NAND_FSL_ELBC 1
279#define CONFIG_SYS_NAND_BLOCK_SIZE (128 * 1024)
280
281
282#define CONFIG_SYS_NAND_SPL_SIZE 0x1000
283#define CONFIG_SYS_NAND_U_BOOT_SIZE ((768 << 10) - 0x2000)
284#define CONFIG_SYS_NAND_U_BOOT_DST (CONFIG_SYS_INIT_L2_ADDR)
285#define CONFIG_SYS_NAND_U_BOOT_START \
286 (CONFIG_SYS_INIT_L2_ADDR + CONFIG_SYS_NAND_SPL_SIZE)
287#define CONFIG_SYS_NAND_U_BOOT_OFFS (0)
288#define CONFIG_SYS_NAND_U_BOOT_RELOC (CONFIG_SYS_INIT_L2_END - 0x2000)
289#define CONFIG_SYS_NAND_U_BOOT_RELOC_SP ((CONFIG_SYS_INIT_L2_END - 1) & ~0xF)
290
291
292#define CONFIG_SYS_NAND_BR_PRELIM \
293 (BR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS) \
294 | (2<<BR_DECC_SHIFT) \
295 | BR_PS_8 \
296 | BR_MS_FCM \
297 | BR_V)
298#define CONFIG_SYS_NAND_OR_PRELIM (0xFFFC0000 \
299 | OR_FCM_PGS \
300 | OR_FCM_CSCT \
301 | OR_FCM_CST \
302 | OR_FCM_CHT \
303 | OR_FCM_SCY_1 \
304 | OR_FCM_TRLX \
305 | OR_FCM_EHTR)
306
307#define CONFIG_SYS_BR0_PRELIM CONFIG_FLASH_BR_PRELIM
308#define CONFIG_SYS_OR0_PRELIM CONFIG_FLASH_OR_PRELIM
309#define CONFIG_SYS_BR2_PRELIM CONFIG_SYS_NAND_BR_PRELIM
310#define CONFIG_SYS_OR2_PRELIM CONFIG_SYS_NAND_OR_PRELIM
311
312#define CONFIG_SYS_BR4_PRELIM \
313 (BR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS + 0x40000) \
314 | (2<<BR_DECC_SHIFT) \
315 | BR_PS_8 \
316 | BR_MS_FCM \
317 | BR_V)
318#define CONFIG_SYS_OR4_PRELIM CONFIG_SYS_NAND_OR_PRELIM
319#define CONFIG_SYS_BR5_PRELIM \
320 (BR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS + 0x80000) \
321 | (2<<BR_DECC_SHIFT) \
322 | BR_PS_8 \
323 | BR_MS_FCM \
324 | BR_V)
325#define CONFIG_SYS_OR5_PRELIM CONFIG_SYS_NAND_OR_PRELIM
326
327#define CONFIG_SYS_BR6_PRELIM \
328 (BR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS + 0xc0000) \
329 | (2<<BR_DECC_SHIFT) \
330 | BR_PS_8 \
331 | BR_MS_FCM \
332 | BR_V)
333#define CONFIG_SYS_OR6_PRELIM CONFIG_SYS_NAND_OR_PRELIM
334
335
336
337
338
339#define CONFIG_SYS_NS16550_SERIAL
340#define CONFIG_SYS_NS16550_REG_SIZE 1
341#define CONFIG_SYS_NS16550_CLK get_bus_freq(0)
342#ifdef CONFIG_NAND_SPL
343#define CONFIG_NS16550_MIN_FUNCTIONS
344#endif
345
346#define CONFIG_SYS_BAUDRATE_TABLE \
347 {300, 600, 1200, 2400, 4800, 9600, 19200, 38400,115200}
348
349#define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_CCSRBAR + 0x4500)
350#define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_CCSRBAR + 0x4600)
351
352
353
354
355#define CONFIG_SYS_I2C
356#define CONFIG_SYS_I2C_FSL
357#define CONFIG_SYS_FSL_I2C_SPEED 400000
358#define CONFIG_SYS_FSL_I2C_SLAVE 0x7F
359#define CONFIG_SYS_FSL_I2C_OFFSET 0x3000
360#define CONFIG_SYS_FSL_I2C2_SPEED 400000
361#define CONFIG_SYS_FSL_I2C2_SLAVE 0x7F
362#define CONFIG_SYS_FSL_I2C2_OFFSET 0x3100
363#define CONFIG_SYS_I2C_NOPROBES { {0, 0x29} }
364
365
366
367
368#define CONFIG_ID_EEPROM
369#ifdef CONFIG_ID_EEPROM
370#define CONFIG_SYS_I2C_EEPROM_NXID
371#endif
372#define CONFIG_SYS_I2C_EEPROM_ADDR 0x57
373#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1
374#define CONFIG_SYS_EEPROM_BUS_NUM 1
375
376
377
378
379#define CONFIG_HARD_SPI
380
381#if defined(CONFIG_SPI_FLASH)
382#define CONFIG_SF_DEFAULT_SPEED 10000000
383#define CONFIG_SF_DEFAULT_MODE 0
384#endif
385
386
387
388
389
390
391#define CONFIG_SYS_PCI1_MEM_VIRT 0x80000000
392#ifdef CONFIG_PHYS_64BIT
393#define CONFIG_SYS_PCI1_MEM_BUS 0xf0000000
394#define CONFIG_SYS_PCI1_MEM_PHYS 0xc00000000ull
395#else
396#define CONFIG_SYS_PCI1_MEM_BUS 0x80000000
397#define CONFIG_SYS_PCI1_MEM_PHYS 0x80000000
398#endif
399#define CONFIG_SYS_PCI1_MEM_SIZE 0x10000000
400#define CONFIG_SYS_PCI1_IO_VIRT 0xffc00000
401#define CONFIG_SYS_PCI1_IO_BUS 0x00000000
402#ifdef CONFIG_PHYS_64BIT
403#define CONFIG_SYS_PCI1_IO_PHYS 0xfffc00000ull
404#else
405#define CONFIG_SYS_PCI1_IO_PHYS 0xffc00000
406#endif
407#define CONFIG_SYS_PCI1_IO_SIZE 0x00010000
408
409
410#define CONFIG_SYS_PCIE1_NAME "Slot 1"
411#define CONFIG_SYS_PCIE1_MEM_VIRT 0x90000000
412#ifdef CONFIG_PHYS_64BIT
413#define CONFIG_SYS_PCIE1_MEM_BUS 0xf8000000
414#define CONFIG_SYS_PCIE1_MEM_PHYS 0xc10000000ull
415#else
416#define CONFIG_SYS_PCIE1_MEM_BUS 0x90000000
417#define CONFIG_SYS_PCIE1_MEM_PHYS 0x90000000
418#endif
419#define CONFIG_SYS_PCIE1_MEM_SIZE 0x08000000
420#define CONFIG_SYS_PCIE1_IO_VIRT 0xffc10000
421#define CONFIG_SYS_PCIE1_IO_BUS 0x00000000
422#ifdef CONFIG_PHYS_64BIT
423#define CONFIG_SYS_PCIE1_IO_PHYS 0xfffc10000ull
424#else
425#define CONFIG_SYS_PCIE1_IO_PHYS 0xffc10000
426#endif
427#define CONFIG_SYS_PCIE1_IO_SIZE 0x00010000
428
429
430#define CONFIG_SYS_PCIE2_NAME "Slot 2"
431#define CONFIG_SYS_PCIE2_MEM_VIRT 0x98000000
432#ifdef CONFIG_PHYS_64BIT
433#define CONFIG_SYS_PCIE2_MEM_BUS 0xf8000000
434#define CONFIG_SYS_PCIE2_MEM_PHYS 0xc18000000ull
435#else
436#define CONFIG_SYS_PCIE2_MEM_BUS 0x98000000
437#define CONFIG_SYS_PCIE2_MEM_PHYS 0x98000000
438#endif
439#define CONFIG_SYS_PCIE2_MEM_SIZE 0x08000000
440#define CONFIG_SYS_PCIE2_IO_VIRT 0xffc20000
441#define CONFIG_SYS_PCIE2_IO_BUS 0x00000000
442#ifdef CONFIG_PHYS_64BIT
443#define CONFIG_SYS_PCIE2_IO_PHYS 0xfffc20000ull
444#else
445#define CONFIG_SYS_PCIE2_IO_PHYS 0xffc20000
446#endif
447#define CONFIG_SYS_PCIE2_IO_SIZE 0x00010000
448
449
450#define CONFIG_SYS_PCIE3_NAME "Slot 3"
451#define CONFIG_SYS_PCIE3_MEM_VIRT 0xa0000000
452#ifdef CONFIG_PHYS_64BIT
453#define CONFIG_SYS_PCIE3_MEM_BUS 0xe0000000
454#define CONFIG_SYS_PCIE3_MEM_PHYS 0xc20000000ull
455#else
456#define CONFIG_SYS_PCIE3_MEM_BUS 0xa0000000
457#define CONFIG_SYS_PCIE3_MEM_PHYS 0xa0000000
458#endif
459#define CONFIG_SYS_PCIE3_MEM_SIZE 0x20000000
460#define CONFIG_SYS_PCIE3_IO_VIRT 0xffc30000
461#define CONFIG_SYS_PCIE3_IO_BUS 0x00000000
462#ifdef CONFIG_PHYS_64BIT
463#define CONFIG_SYS_PCIE3_IO_PHYS 0xfffc30000ull
464#else
465#define CONFIG_SYS_PCIE3_IO_PHYS 0xffc30000
466#endif
467#define CONFIG_SYS_PCIE3_IO_SIZE 0x00010000
468
469#if defined(CONFIG_PCI)
470
471#define VIDEO_IO_OFFSET CONFIG_SYS_PCIE3_IO_VIRT
472
473
474
475
476
477
478#if defined(CONFIG_VIDEO)
479#define CONFIG_BIOSEMU
480#define CONFIG_ATI_RADEON_FB
481#define CONFIG_VIDEO_LOGO
482#define CONFIG_SYS_ISA_IO_BASE_ADDRESS CONFIG_SYS_PCIE3_IO_VIRT
483#endif
484
485#undef CONFIG_EEPRO100
486#undef CONFIG_TULIP
487
488#ifndef CONFIG_PCI_PNP
489 #define PCI_ENET0_IOADDR CONFIG_SYS_PCI1_IO_BUS
490 #define PCI_ENET0_MEMADDR CONFIG_SYS_PCI1_IO_BUS
491 #define PCI_IDSEL_NUMBER 0x11
492#endif
493
494#define CONFIG_PCI_SCAN_SHOW
495
496#endif
497
498
499#define CONFIG_SYS_SATA_MAX_DEVICE 2
500#define CONFIG_SATA1
501#define CONFIG_SYS_SATA1 CONFIG_SYS_MPC85xx_SATA1_ADDR
502#define CONFIG_SYS_SATA1_FLAGS FLAGS_DMA
503#define CONFIG_SATA2
504#define CONFIG_SYS_SATA2 CONFIG_SYS_MPC85xx_SATA2_ADDR
505#define CONFIG_SYS_SATA2_FLAGS FLAGS_DMA
506
507#ifdef CONFIG_FSL_SATA
508#define CONFIG_LBA48
509#endif
510
511#if defined(CONFIG_TSEC_ENET)
512
513#define CONFIG_MII_DEFAULT_TSEC 1
514#define CONFIG_TSEC1 1
515#define CONFIG_TSEC1_NAME "eTSEC1"
516#define CONFIG_TSEC3 1
517#define CONFIG_TSEC3_NAME "eTSEC3"
518
519#define CONFIG_FSL_SGMII_RISER 1
520#define SGMII_RISER_PHY_OFFSET 0x1c
521
522#define TSEC1_PHY_ADDR 1
523#define TSEC3_PHY_ADDR 0
524
525#define TSEC1_FLAGS (TSEC_GIGABIT | TSEC_REDUCED)
526#define TSEC3_FLAGS (TSEC_GIGABIT | TSEC_REDUCED)
527
528#define TSEC1_PHYIDX 0
529#define TSEC3_PHYIDX 0
530
531#define CONFIG_ETHPRIME "eTSEC1"
532
533#endif
534
535
536
537
538
539#if defined(CONFIG_SYS_RAMBOOT)
540#if defined(CONFIG_RAMBOOT_SPIFLASH)
541#define CONFIG_ENV_SPI_BUS 0
542#define CONFIG_ENV_SPI_CS 0
543#define CONFIG_ENV_SPI_MAX_HZ 10000000
544#define CONFIG_ENV_SPI_MODE 0
545#define CONFIG_ENV_SIZE 0x2000
546#define CONFIG_ENV_OFFSET 0xF0000
547#define CONFIG_ENV_SECT_SIZE 0x10000
548#elif defined(CONFIG_RAMBOOT_SDCARD)
549#define CONFIG_FSL_FIXED_MMC_LOCATION
550#define CONFIG_ENV_SIZE 0x2000
551#define CONFIG_SYS_MMC_ENV_DEV 0
552#else
553 #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - 0x1000)
554 #define CONFIG_ENV_SIZE 0x2000
555#endif
556#else
557 #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - CONFIG_ENV_SECT_SIZE)
558 #define CONFIG_ENV_SIZE 0x2000
559 #define CONFIG_ENV_SECT_SIZE 0x20000
560#endif
561
562#define CONFIG_LOADS_ECHO 1
563#define CONFIG_SYS_LOADS_BAUD_CHANGE 1
564
565#undef CONFIG_WATCHDOG
566
567#ifdef CONFIG_MMC
568#define CONFIG_SYS_FSL_ESDHC_ADDR CONFIG_SYS_MPC85xx_ESDHC_ADDR
569#endif
570
571
572
573
574#define CONFIG_HAS_FSL_MPH_USB
575#ifdef CONFIG_HAS_FSL_MPH_USB
576#ifdef CONFIG_USB_EHCI_HCD
577#define CONFIG_EHCI_HCD_INIT_AFTER_RESET
578#define CONFIG_USB_EHCI_FSL
579#endif
580#endif
581
582
583
584
585#define CONFIG_SYS_LOAD_ADDR 0x2000000
586
587
588
589
590
591
592#define CONFIG_SYS_BOOTMAPSZ (64 << 20)
593#define CONFIG_SYS_BOOTM_LEN (64 << 20)
594
595#if defined(CONFIG_CMD_KGDB)
596#define CONFIG_KGDB_BAUDRATE 230400
597#endif
598
599
600
601
602
603
604#if defined(CONFIG_TSEC_ENET)
605#define CONFIG_HAS_ETH0
606#define CONFIG_HAS_ETH1
607#define CONFIG_HAS_ETH2
608#define CONFIG_HAS_ETH3
609#endif
610
611#define CONFIG_IPADDR 192.168.1.254
612
613#define CONFIG_HOSTNAME "unknown"
614#define CONFIG_ROOTPATH "/opt/nfsroot"
615#define CONFIG_BOOTFILE "uImage"
616#define CONFIG_UBOOTPATH u-boot.bin
617
618#define CONFIG_SERVERIP 192.168.1.1
619#define CONFIG_GATEWAYIP 192.168.1.1
620#define CONFIG_NETMASK 255.255.255.0
621
622
623#define CONFIG_LOADADDR 1000000
624
625#define CONFIG_EXTRA_ENV_SETTINGS \
626"netdev=eth0\0" \
627"uboot=" __stringify(CONFIG_UBOOTPATH) "\0" \
628"tftpflash=tftpboot $loadaddr $uboot; " \
629 "protect off " __stringify(CONFIG_SYS_TEXT_BASE) \
630 " +$filesize; " \
631 "erase " __stringify(CONFIG_SYS_TEXT_BASE) \
632 " +$filesize; " \
633 "cp.b $loadaddr " __stringify(CONFIG_SYS_TEXT_BASE) \
634 " $filesize; " \
635 "protect on " __stringify(CONFIG_SYS_TEXT_BASE) \
636 " +$filesize; " \
637 "cmp.b $loadaddr " __stringify(CONFIG_SYS_TEXT_BASE) \
638 " $filesize\0" \
639"consoledev=ttyS0\0" \
640"ramdiskaddr=2000000\0" \
641"ramdiskfile=8536ds/ramdisk.uboot\0" \
642"fdtaddr=1e00000\0" \
643"fdtfile=8536ds/mpc8536ds.dtb\0" \
644"bdev=sda3\0" \
645"hwconfig=usb1:dr_mode=host,phy_type=ulpi\0"
646
647#define CONFIG_HDBOOT \
648 "setenv bootargs root=/dev/$bdev rw " \
649 "console=$consoledev,$baudrate $othbootargs;" \
650 "tftp $loadaddr $bootfile;" \
651 "tftp $fdtaddr $fdtfile;" \
652 "bootm $loadaddr - $fdtaddr"
653
654#define CONFIG_NFSBOOTCOMMAND \
655 "setenv bootargs root=/dev/nfs rw " \
656 "nfsroot=$serverip:$rootpath " \
657 "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \
658 "console=$consoledev,$baudrate $othbootargs;" \
659 "tftp $loadaddr $bootfile;" \
660 "tftp $fdtaddr $fdtfile;" \
661 "bootm $loadaddr - $fdtaddr"
662
663#define CONFIG_RAMBOOTCOMMAND \
664 "setenv bootargs root=/dev/ram rw " \
665 "console=$consoledev,$baudrate $othbootargs;" \
666 "tftp $ramdiskaddr $ramdiskfile;" \
667 "tftp $loadaddr $bootfile;" \
668 "tftp $fdtaddr $fdtfile;" \
669 "bootm $loadaddr $ramdiskaddr $fdtaddr"
670
671#define CONFIG_BOOTCOMMAND CONFIG_HDBOOT
672
673#endif
674