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10#ifndef __T1024RDB_H
11#define __T1024RDB_H
12
13
14#define CONFIG_SYS_BOOK3E_HV
15#define CONFIG_ENABLE_36BIT_PHYS
16
17#ifdef CONFIG_PHYS_64BIT
18#define CONFIG_ADDR_MAP 1
19#define CONFIG_SYS_NUM_ADDR_MAP 64
20#endif
21
22#define CONFIG_SYS_FSL_CPC
23#define CONFIG_SYS_NUM_CPC CONFIG_SYS_NUM_DDR_CTLRS
24
25#define CONFIG_ENV_OVERWRITE
26
27
28#ifdef CONFIG_ARCH_T1024
29#define CONFIG_DEEP_SLEEP
30#endif
31
32#ifdef CONFIG_RAMBOOT_PBL
33#define CONFIG_SYS_FSL_PBL_PBI board/freescale/t102xrdb/t1024_pbi.cfg
34#define CONFIG_SPL_FLUSH_IMAGE
35#define CONFIG_SPL_TEXT_BASE 0xFFFD8000
36#define CONFIG_SPL_PAD_TO 0x40000
37#define CONFIG_SPL_MAX_SIZE 0x28000
38#define RESET_VECTOR_OFFSET 0x27FFC
39#define BOOT_PAGE_OFFSET 0x27000
40#ifdef CONFIG_SPL_BUILD
41#define CONFIG_SPL_SKIP_RELOCATE
42#define CONFIG_SPL_COMMON_INIT_DDR
43#define CONFIG_SYS_CCSR_DO_NOT_RELOCATE
44#endif
45
46#ifdef CONFIG_NAND
47#define CONFIG_SYS_NAND_U_BOOT_SIZE (768 << 10)
48#define CONFIG_SYS_NAND_U_BOOT_DST 0x30000000
49#define CONFIG_SYS_NAND_U_BOOT_START 0x30000000
50#define CONFIG_SYS_NAND_U_BOOT_OFFS (256 << 10)
51#define CONFIG_SYS_LDSCRIPT "arch/powerpc/cpu/mpc85xx/u-boot-nand.lds"
52#if defined(CONFIG_TARGET_T1024RDB)
53#define CONFIG_SYS_FSL_PBL_RCW board/freescale/t102xrdb/t1024_nand_rcw.cfg
54#elif defined(CONFIG_TARGET_T1023RDB)
55#define CONFIG_SYS_FSL_PBL_RCW board/freescale/t102xrdb/t1023_nand_rcw.cfg
56#endif
57#define CONFIG_SPL_NAND_BOOT
58#endif
59
60#ifdef CONFIG_SPIFLASH
61#define CONFIG_RESET_VECTOR_ADDRESS 0x30000FFC
62#define CONFIG_SPL_SPI_FLASH_MINIMAL
63#define CONFIG_SYS_SPI_FLASH_U_BOOT_SIZE (768 << 10)
64#define CONFIG_SYS_SPI_FLASH_U_BOOT_DST (0x30000000)
65#define CONFIG_SYS_SPI_FLASH_U_BOOT_START (0x30000000)
66#define CONFIG_SYS_SPI_FLASH_U_BOOT_OFFS (256 << 10)
67#define CONFIG_SYS_LDSCRIPT "arch/powerpc/cpu/mpc85xx/u-boot.lds"
68#ifndef CONFIG_SPL_BUILD
69#define CONFIG_SYS_MPC85XX_NO_RESETVEC
70#endif
71#if defined(CONFIG_TARGET_T1024RDB)
72#define CONFIG_SYS_FSL_PBL_RCW board/freescale/t102xrdb/t1024_spi_rcw.cfg
73#elif defined(CONFIG_TARGET_T1023RDB)
74#define CONFIG_SYS_FSL_PBL_RCW board/freescale/t102xrdb/t1023_spi_rcw.cfg
75#endif
76#define CONFIG_SPL_SPI_BOOT
77#endif
78
79#ifdef CONFIG_SDCARD
80#define CONFIG_RESET_VECTOR_ADDRESS 0x30000FFC
81#define CONFIG_SYS_MMC_U_BOOT_SIZE (768 << 10)
82#define CONFIG_SYS_MMC_U_BOOT_DST (0x30000000)
83#define CONFIG_SYS_MMC_U_BOOT_START (0x30000000)
84#define CONFIG_SYS_MMC_U_BOOT_OFFS (260 << 10)
85#define CONFIG_SYS_LDSCRIPT "arch/powerpc/cpu/mpc85xx/u-boot.lds"
86#ifndef CONFIG_SPL_BUILD
87#define CONFIG_SYS_MPC85XX_NO_RESETVEC
88#endif
89#if defined(CONFIG_TARGET_T1024RDB)
90#define CONFIG_SYS_FSL_PBL_RCW board/freescale/t102xrdb/t1024_sd_rcw.cfg
91#elif defined(CONFIG_TARGET_T1023RDB)
92#define CONFIG_SYS_FSL_PBL_RCW board/freescale/t102xrdb/t1023_sd_rcw.cfg
93#endif
94#define CONFIG_SPL_MMC_BOOT
95#endif
96
97#endif
98
99#ifndef CONFIG_RESET_VECTOR_ADDRESS
100#define CONFIG_RESET_VECTOR_ADDRESS 0xeffffffc
101#endif
102
103#ifdef CONFIG_MTD_NOR_FLASH
104#define CONFIG_FLASH_CFI_DRIVER
105#define CONFIG_SYS_FLASH_CFI
106#define CONFIG_SYS_FLASH_USE_BUFFER_WRITE
107#endif
108
109
110#define CONFIG_SRIO_PCIE_BOOT_MASTER
111
112
113
114
115#define CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_BUS1 0xfff00000ull
116#define CONFIG_SRIO_PCIE_BOOT_IMAGE_SIZE 0x100000
117#ifdef CONFIG_PHYS_64BIT
118#define CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_PHYS 0xfef200000ull
119#define CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_BUS2 0x3fff00000ull
120#else
121#define CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_PHYS 0xef200000
122#define CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_BUS2 0xfff00000
123#endif
124
125
126
127
128#ifdef CONFIG_PHYS_64BIT
129#define CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_MEM_PHYS 0xfef100000ull
130#define CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_MEM_BUS 0x3ffe00000ull
131#else
132#define CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_MEM_PHYS 0xef100000
133#define CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_MEM_BUS 0xffe00000
134#endif
135#define CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_SIZE 0x40000
136
137#define CONFIG_SRIO_PCIE_BOOT_BRR_OFFSET 0xe00e4
138#define CONFIG_SRIO_PCIE_BOOT_RELEASE_MASK 0x00000001
139
140
141#ifdef CONFIG_SRIO_PCIE_BOOT_SLAVE
142#define CONFIG_SYS_SRIO_PCIE_BOOT_UCODE_ENV_ADDR 0xFFE00000
143#define CONFIG_SYS_SRIO_PCIE_BOOT_UCODE_ENV_ADDR_PHYS \
144 (0x300000000ull | CONFIG_SYS_SRIO_PCIE_BOOT_UCODE_ENV_ADDR)
145
146#define CONFIG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR (CONFIG_SYS_TEXT_BASE & 0xfff00000)
147#define CONFIG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR_PHYS \
148 (0x300000000ull | CONFIG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR)
149#define CONFIG_RESET_VECTOR_ADDRESS 0xfffffffc
150#endif
151
152#if defined(CONFIG_SPIFLASH)
153#define CONFIG_SYS_EXTRA_ENV_RELOC
154#define CONFIG_ENV_SPI_BUS 0
155#define CONFIG_ENV_SPI_CS 0
156#define CONFIG_ENV_SPI_MAX_HZ 10000000
157#define CONFIG_ENV_SPI_MODE 0
158#define CONFIG_ENV_SIZE 0x2000
159#define CONFIG_ENV_OFFSET 0x100000
160#if defined(CONFIG_TARGET_T1024RDB)
161#define CONFIG_ENV_SECT_SIZE 0x10000
162#elif defined(CONFIG_TARGET_T1023RDB)
163#define CONFIG_ENV_SECT_SIZE 0x40000
164#endif
165#elif defined(CONFIG_SDCARD)
166#define CONFIG_SYS_EXTRA_ENV_RELOC
167#define CONFIG_SYS_MMC_ENV_DEV 0
168#define CONFIG_ENV_SIZE 0x2000
169#define CONFIG_ENV_OFFSET (512 * 0x800)
170#elif defined(CONFIG_NAND)
171#define CONFIG_SYS_EXTRA_ENV_RELOC
172#define CONFIG_ENV_SIZE 0x2000
173#if defined(CONFIG_TARGET_T1024RDB)
174#define CONFIG_ENV_OFFSET (2 * CONFIG_SYS_NAND_BLOCK_SIZE)
175#elif defined(CONFIG_TARGET_T1023RDB)
176#define CONFIG_ENV_OFFSET (10 * CONFIG_SYS_NAND_BLOCK_SIZE)
177#endif
178#elif defined(CONFIG_SRIO_PCIE_BOOT_SLAVE)
179#define CONFIG_ENV_ADDR 0xffe20000
180#define CONFIG_ENV_SIZE 0x2000
181#elif defined(CONFIG_ENV_IS_NOWHERE)
182#define CONFIG_ENV_SIZE 0x2000
183#else
184#define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - CONFIG_ENV_SECT_SIZE)
185#define CONFIG_ENV_SIZE 0x2000
186#define CONFIG_ENV_SECT_SIZE 0x20000
187#endif
188
189#ifndef __ASSEMBLY__
190unsigned long get_board_sys_clk(void);
191unsigned long get_board_ddr_clk(void);
192#endif
193
194#define CONFIG_SYS_CLK_FREQ 100000000
195#define CONFIG_DDR_CLK_FREQ 100000000
196
197
198
199
200#define CONFIG_SYS_CACHE_STASHING
201#define CONFIG_BACKSIDE_L2_CACHE
202#define CONFIG_SYS_INIT_L2CSR0 L2CSR0_L2E
203#define CONFIG_BTB
204#define CONFIG_DDR_ECC
205#ifdef CONFIG_DDR_ECC
206#define CONFIG_ECC_INIT_VIA_DDRCONTROLLER
207#define CONFIG_MEM_INIT_VALUE 0xdeadbeef
208#endif
209
210#define CONFIG_SYS_MEMTEST_START 0x00200000
211#define CONFIG_SYS_MEMTEST_END 0x00400000
212
213
214
215
216#define CONFIG_SYS_INIT_L3_ADDR 0xFFFC0000
217#define CONFIG_SYS_L3_SIZE (256 << 10)
218#define CONFIG_SPL_GD_ADDR (CONFIG_SYS_INIT_L3_ADDR + 32 * 1024)
219#ifdef CONFIG_RAMBOOT_PBL
220#define CONFIG_ENV_ADDR (CONFIG_SPL_GD_ADDR + 4 * 1024)
221#endif
222#define CONFIG_SPL_RELOC_MALLOC_ADDR (CONFIG_SPL_GD_ADDR + 12 * 1024)
223#define CONFIG_SPL_RELOC_MALLOC_SIZE (30 << 10)
224#define CONFIG_SPL_RELOC_STACK (CONFIG_SPL_GD_ADDR + 64 * 1024)
225
226#ifdef CONFIG_PHYS_64BIT
227#define CONFIG_SYS_DCSRBAR 0xf0000000
228#define CONFIG_SYS_DCSRBAR_PHYS 0xf00000000ull
229#endif
230
231
232#define CONFIG_ID_EEPROM
233#define CONFIG_SYS_I2C_EEPROM_NXID
234#define CONFIG_SYS_EEPROM_BUS_NUM 0
235#define CONFIG_SYS_I2C_EEPROM_ADDR 0x50
236#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 2
237#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 3
238#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 5
239
240
241
242
243#define CONFIG_VERY_BIG_RAM
244#define CONFIG_SYS_DDR_SDRAM_BASE 0x00000000
245#define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE
246#define CONFIG_DIMM_SLOTS_PER_CTLR 1
247#define CONFIG_CHIP_SELECTS_PER_CTRL (4 * CONFIG_DIMM_SLOTS_PER_CTLR)
248#define CONFIG_FSL_DDR_INTERACTIVE
249#if defined(CONFIG_TARGET_T1024RDB)
250#define CONFIG_DDR_SPD
251#define CONFIG_SYS_SPD_BUS_NUM 0
252#define SPD_EEPROM_ADDRESS 0x51
253#define CONFIG_SYS_SDRAM_SIZE 4096
254#elif defined(CONFIG_TARGET_T1023RDB)
255#define CONFIG_SYS_DDR_RAW_TIMING
256#define CONFIG_SYS_SDRAM_SIZE 2048
257#endif
258
259
260
261
262#define CONFIG_SYS_FLASH_BASE 0xe8000000
263#ifdef CONFIG_PHYS_64BIT
264#define CONFIG_SYS_FLASH_BASE_PHYS (0xf00000000ull | CONFIG_SYS_FLASH_BASE)
265#else
266#define CONFIG_SYS_FLASH_BASE_PHYS CONFIG_SYS_FLASH_BASE
267#endif
268
269#define CONFIG_SYS_NOR0_CSPR_EXT (0xf)
270#define CONFIG_SYS_NOR0_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS) | \
271 CSPR_PORT_SIZE_16 | \
272 CSPR_MSEL_NOR | \
273 CSPR_V)
274#define CONFIG_SYS_NOR_AMASK IFC_AMASK(128*1024*1024)
275
276
277#if defined(CONFIG_TARGET_T1024RDB)
278#define CONFIG_SYS_NOR_CSOR CSOR_NAND_TRHZ_80
279#elif defined(CONFIG_TARGET_T1023RDB)
280#define CONFIG_SYS_NOR_CSOR (CSOR_NOR_ADM_SHIFT(0) | \
281 CSOR_NAND_TRHZ_80 | CSOR_NOR_ADM_SHFT_MODE_EN)
282#endif
283#define CONFIG_SYS_NOR_FTIM0 (FTIM0_NOR_TACSE(0x4) | \
284 FTIM0_NOR_TEADC(0x5) | \
285 FTIM0_NOR_TEAHC(0x5))
286#define CONFIG_SYS_NOR_FTIM1 (FTIM1_NOR_TACO(0x35) | \
287 FTIM1_NOR_TRAD_NOR(0x1A) |\
288 FTIM1_NOR_TSEQRAD_NOR(0x13))
289#define CONFIG_SYS_NOR_FTIM2 (FTIM2_NOR_TCS(0x4) | \
290 FTIM2_NOR_TCH(0x4) | \
291 FTIM2_NOR_TWPH(0x0E) | \
292 FTIM2_NOR_TWP(0x1c))
293#define CONFIG_SYS_NOR_FTIM3 0x0
294
295#define CONFIG_SYS_FLASH_QUIET_TEST
296#define CONFIG_FLASH_SHOW_PROGRESS 45
297
298#define CONFIG_SYS_MAX_FLASH_BANKS 1
299#define CONFIG_SYS_MAX_FLASH_SECT 1024
300#define CONFIG_SYS_FLASH_ERASE_TOUT 60000
301#define CONFIG_SYS_FLASH_WRITE_TOUT 500
302
303#define CONFIG_SYS_FLASH_EMPTY_INFO
304#define CONFIG_SYS_FLASH_BANKS_LIST {CONFIG_SYS_FLASH_BASE_PHYS}
305
306#ifdef CONFIG_TARGET_T1024RDB
307
308#define CONFIG_SYS_CPLD_BASE 0xffdf0000
309#define CONFIG_SYS_CPLD_BASE_PHYS (0xf00000000ull | CONFIG_SYS_CPLD_BASE)
310#define CONFIG_SYS_CSPR2_EXT (0xf)
311#define CONFIG_SYS_CSPR2 (CSPR_PHYS_ADDR(CONFIG_SYS_CPLD_BASE) \
312 | CSPR_PORT_SIZE_8 \
313 | CSPR_MSEL_GPCM \
314 | CSPR_V)
315#define CONFIG_SYS_AMASK2 IFC_AMASK(64*1024)
316#define CONFIG_SYS_CSOR2 0x0
317
318
319#define CONFIG_SYS_CS2_FTIM0 (FTIM0_GPCM_TACSE(0x0e) | \
320 FTIM0_GPCM_TEADC(0x0e) | \
321 FTIM0_GPCM_TEAHC(0x0e))
322#define CONFIG_SYS_CS2_FTIM1 (FTIM1_GPCM_TACO(0x0e) | \
323 FTIM1_GPCM_TRAD(0x1f))
324#define CONFIG_SYS_CS2_FTIM2 (FTIM2_GPCM_TCS(0x0e) | \
325 FTIM2_GPCM_TCH(0x8) | \
326 FTIM2_GPCM_TWP(0x1f))
327#define CONFIG_SYS_CS2_FTIM3 0x0
328#endif
329
330
331#define CONFIG_NAND_FSL_IFC
332#define CONFIG_SYS_NAND_BASE 0xff800000
333#ifdef CONFIG_PHYS_64BIT
334#define CONFIG_SYS_NAND_BASE_PHYS (0xf00000000ull | CONFIG_SYS_NAND_BASE)
335#else
336#define CONFIG_SYS_NAND_BASE_PHYS CONFIG_SYS_NAND_BASE
337#endif
338#define CONFIG_SYS_NAND_CSPR_EXT (0xf)
339#define CONFIG_SYS_NAND_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS) \
340 | CSPR_PORT_SIZE_8 \
341 | CSPR_MSEL_NAND \
342 | CSPR_V)
343#define CONFIG_SYS_NAND_AMASK IFC_AMASK(64*1024)
344
345#if defined(CONFIG_TARGET_T1024RDB)
346#define CONFIG_SYS_NAND_CSOR (CSOR_NAND_ECC_ENC_EN \
347 | CSOR_NAND_ECC_DEC_EN \
348 | CSOR_NAND_ECC_MODE_4 \
349 | CSOR_NAND_RAL_3 \
350 | CSOR_NAND_PGS_4K \
351 | CSOR_NAND_SPRZ_224 \
352 | CSOR_NAND_PB(64))
353#define CONFIG_SYS_NAND_BLOCK_SIZE (512 * 1024)
354#elif defined(CONFIG_TARGET_T1023RDB)
355#define CONFIG_SYS_NAND_CSOR (CSOR_NAND_ECC_ENC_EN \
356 | CSOR_NAND_ECC_DEC_EN \
357 | CSOR_NAND_ECC_MODE_4 \
358 | CSOR_NAND_RAL_3 \
359 | CSOR_NAND_PGS_2K \
360 | CSOR_NAND_SPRZ_128 \
361 | CSOR_NAND_PB(64))
362#define CONFIG_SYS_NAND_BLOCK_SIZE (128 * 1024)
363#endif
364
365#define CONFIG_SYS_NAND_ONFI_DETECTION
366
367#define CONFIG_SYS_NAND_FTIM0 (FTIM0_NAND_TCCST(0x07) | \
368 FTIM0_NAND_TWP(0x18) | \
369 FTIM0_NAND_TWCHT(0x07) | \
370 FTIM0_NAND_TWH(0x0a))
371#define CONFIG_SYS_NAND_FTIM1 (FTIM1_NAND_TADLE(0x32) | \
372 FTIM1_NAND_TWBE(0x39) | \
373 FTIM1_NAND_TRR(0x0e) | \
374 FTIM1_NAND_TRP(0x18))
375#define CONFIG_SYS_NAND_FTIM2 (FTIM2_NAND_TRAD(0x0f) | \
376 FTIM2_NAND_TREH(0x0a) | \
377 FTIM2_NAND_TWHRE(0x1e))
378#define CONFIG_SYS_NAND_FTIM3 0x0
379
380#define CONFIG_SYS_NAND_DDR_LAW 11
381#define CONFIG_SYS_NAND_BASE_LIST { CONFIG_SYS_NAND_BASE }
382#define CONFIG_SYS_MAX_NAND_DEVICE 1
383
384#if defined(CONFIG_NAND)
385#define CONFIG_SYS_CSPR0_EXT CONFIG_SYS_NAND_CSPR_EXT
386#define CONFIG_SYS_CSPR0 CONFIG_SYS_NAND_CSPR
387#define CONFIG_SYS_AMASK0 CONFIG_SYS_NAND_AMASK
388#define CONFIG_SYS_CSOR0 CONFIG_SYS_NAND_CSOR
389#define CONFIG_SYS_CS0_FTIM0 CONFIG_SYS_NAND_FTIM0
390#define CONFIG_SYS_CS0_FTIM1 CONFIG_SYS_NAND_FTIM1
391#define CONFIG_SYS_CS0_FTIM2 CONFIG_SYS_NAND_FTIM2
392#define CONFIG_SYS_CS0_FTIM3 CONFIG_SYS_NAND_FTIM3
393#define CONFIG_SYS_CSPR1_EXT CONFIG_SYS_NOR0_CSPR_EXT
394#define CONFIG_SYS_CSPR1 CONFIG_SYS_NOR0_CSPR
395#define CONFIG_SYS_AMASK1 CONFIG_SYS_NOR_AMASK
396#define CONFIG_SYS_CSOR1 CONFIG_SYS_NOR_CSOR
397#define CONFIG_SYS_CS1_FTIM0 CONFIG_SYS_NOR_FTIM0
398#define CONFIG_SYS_CS1_FTIM1 CONFIG_SYS_NOR_FTIM1
399#define CONFIG_SYS_CS1_FTIM2 CONFIG_SYS_NOR_FTIM2
400#define CONFIG_SYS_CS1_FTIM3 CONFIG_SYS_NOR_FTIM3
401#else
402#define CONFIG_SYS_CSPR0_EXT CONFIG_SYS_NOR0_CSPR_EXT
403#define CONFIG_SYS_CSPR0 CONFIG_SYS_NOR0_CSPR
404#define CONFIG_SYS_AMASK0 CONFIG_SYS_NOR_AMASK
405#define CONFIG_SYS_CSOR0 CONFIG_SYS_NOR_CSOR
406#define CONFIG_SYS_CS0_FTIM0 CONFIG_SYS_NOR_FTIM0
407#define CONFIG_SYS_CS0_FTIM1 CONFIG_SYS_NOR_FTIM1
408#define CONFIG_SYS_CS0_FTIM2 CONFIG_SYS_NOR_FTIM2
409#define CONFIG_SYS_CS0_FTIM3 CONFIG_SYS_NOR_FTIM3
410#define CONFIG_SYS_CSPR1_EXT CONFIG_SYS_NAND_CSPR_EXT
411#define CONFIG_SYS_CSPR1 CONFIG_SYS_NAND_CSPR
412#define CONFIG_SYS_AMASK1 CONFIG_SYS_NAND_AMASK
413#define CONFIG_SYS_CSOR1 CONFIG_SYS_NAND_CSOR
414#define CONFIG_SYS_CS1_FTIM0 CONFIG_SYS_NAND_FTIM0
415#define CONFIG_SYS_CS1_FTIM1 CONFIG_SYS_NAND_FTIM1
416#define CONFIG_SYS_CS1_FTIM2 CONFIG_SYS_NAND_FTIM2
417#define CONFIG_SYS_CS1_FTIM3 CONFIG_SYS_NAND_FTIM3
418#endif
419
420#ifdef CONFIG_SPL_BUILD
421#define CONFIG_SYS_MONITOR_BASE CONFIG_SPL_TEXT_BASE
422#else
423#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE
424#endif
425
426#if defined(CONFIG_RAMBOOT_PBL)
427#define CONFIG_SYS_RAMBOOT
428#endif
429
430#define CONFIG_HWCONFIG
431
432
433#define CONFIG_L1_INIT_RAM
434#define CONFIG_SYS_INIT_RAM_LOCK
435#define CONFIG_SYS_INIT_RAM_ADDR 0xfdd00000
436#ifdef CONFIG_PHYS_64BIT
437#define CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH 0xf
438#define CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW 0xfe03c000
439
440#define CONFIG_SYS_INIT_RAM_ADDR_PHYS \
441 ((CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH * 1ull << 32) | \
442 CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW)
443#else
444#define CONFIG_SYS_INIT_RAM_ADDR_PHYS 0xfe03c000
445#define CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH 0
446#define CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW CONFIG_SYS_INIT_RAM_ADDR_PHYS
447#endif
448#define CONFIG_SYS_INIT_RAM_SIZE 0x00004000
449
450#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - \
451 GENERATED_GBL_DATA_SIZE)
452#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
453
454#define CONFIG_SYS_MONITOR_LEN (768 * 1024)
455#define CONFIG_SYS_MALLOC_LEN (10 * 1024 * 1024)
456
457
458#define CONFIG_SYS_NS16550_SERIAL
459#define CONFIG_SYS_NS16550_REG_SIZE 1
460#define CONFIG_SYS_NS16550_CLK (get_bus_freq(0)/2)
461
462#define CONFIG_SYS_BAUDRATE_TABLE \
463 {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200}
464
465#define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_CCSRBAR+0x11C500)
466#define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_CCSRBAR+0x11C600)
467#define CONFIG_SYS_NS16550_COM3 (CONFIG_SYS_CCSRBAR+0x11D500)
468#define CONFIG_SYS_NS16550_COM4 (CONFIG_SYS_CCSRBAR+0x11D600)
469
470
471#undef CONFIG_FSL_DIU_FB
472#ifdef CONFIG_FSL_DIU_FB
473#define CONFIG_SYS_DIU_ADDR (CONFIG_SYS_CCSRBAR + 0x180000)
474#define CONFIG_VIDEO_LOGO
475#define CONFIG_VIDEO_BMP_LOGO
476#define CONFIG_CFI_FLASH_USE_WEAK_ACCESSORS
477
478
479
480
481#undef CONFIG_SYS_FLASH_EMPTY_INFO
482#endif
483
484
485#define CONFIG_SYS_I2C
486#define CONFIG_SYS_I2C_FSL
487#define CONFIG_SYS_FSL_I2C_SPEED 50000
488#define CONFIG_SYS_FSL_I2C_SLAVE 0x7F
489#define CONFIG_SYS_FSL_I2C2_SPEED 50000
490#define CONFIG_SYS_FSL_I2C2_SLAVE 0x7F
491#define CONFIG_SYS_FSL_I2C_OFFSET 0x118000
492#define CONFIG_SYS_FSL_I2C2_OFFSET 0x118100
493
494#define I2C_PCA6408_BUS_NUM 1
495#define I2C_PCA6408_ADDR 0x20
496
497
498#define I2C_MUX_CH_DEFAULT 0x8
499
500
501
502
503#define RTC
504#define CONFIG_RTC_DS1337 1
505#define CONFIG_SYS_I2C_RTC_ADDR 0x68
506
507
508
509
510#define CONFIG_SPI_FLASH_BAR
511#define CONFIG_SF_DEFAULT_SPEED 10000000
512#define CONFIG_SF_DEFAULT_MODE 0
513
514
515
516
517
518#define CONFIG_PCIE1
519#define CONFIG_PCIE2
520#define CONFIG_PCIE3
521#ifdef CONFIG_ARCH_T1040
522#define CONFIG_PCIE4
523#endif
524#define CONFIG_FSL_PCI_INIT
525#define CONFIG_SYS_PCI_64BIT
526#define CONFIG_PCI_INDIRECT_BRIDGE
527
528#ifdef CONFIG_PCI
529
530#ifdef CONFIG_PCIE1
531#define CONFIG_SYS_PCIE1_MEM_VIRT 0x80000000
532#ifdef CONFIG_PHYS_64BIT
533#define CONFIG_SYS_PCIE1_MEM_BUS 0xe0000000
534#define CONFIG_SYS_PCIE1_MEM_PHYS 0xc00000000ull
535#else
536#define CONFIG_SYS_PCIE1_MEM_BUS 0x80000000
537#define CONFIG_SYS_PCIE1_MEM_PHYS 0x80000000
538#endif
539#define CONFIG_SYS_PCIE1_MEM_SIZE 0x10000000
540#define CONFIG_SYS_PCIE1_IO_VIRT 0xf8000000
541#define CONFIG_SYS_PCIE1_IO_BUS 0x00000000
542#ifdef CONFIG_PHYS_64BIT
543#define CONFIG_SYS_PCIE1_IO_PHYS 0xff8000000ull
544#else
545#define CONFIG_SYS_PCIE1_IO_PHYS 0xf8000000
546#endif
547#define CONFIG_SYS_PCIE1_IO_SIZE 0x00010000
548#endif
549
550
551#ifdef CONFIG_PCIE2
552#define CONFIG_SYS_PCIE2_MEM_VIRT 0x90000000
553#ifdef CONFIG_PHYS_64BIT
554#define CONFIG_SYS_PCIE2_MEM_BUS 0xe0000000
555#define CONFIG_SYS_PCIE2_MEM_PHYS 0xc10000000ull
556#else
557#define CONFIG_SYS_PCIE2_MEM_BUS 0x90000000
558#define CONFIG_SYS_PCIE2_MEM_PHYS 0x90000000
559#endif
560#define CONFIG_SYS_PCIE2_MEM_SIZE 0x10000000
561#define CONFIG_SYS_PCIE2_IO_VIRT 0xf8010000
562#define CONFIG_SYS_PCIE2_IO_BUS 0x00000000
563#ifdef CONFIG_PHYS_64BIT
564#define CONFIG_SYS_PCIE2_IO_PHYS 0xff8010000ull
565#else
566#define CONFIG_SYS_PCIE2_IO_PHYS 0xf8010000
567#endif
568#define CONFIG_SYS_PCIE2_IO_SIZE 0x00010000
569#endif
570
571
572#ifdef CONFIG_PCIE3
573#define CONFIG_SYS_PCIE3_MEM_VIRT 0xa0000000
574#ifdef CONFIG_PHYS_64BIT
575#define CONFIG_SYS_PCIE3_MEM_BUS 0xe0000000
576#define CONFIG_SYS_PCIE3_MEM_PHYS 0xc20000000ull
577#else
578#define CONFIG_SYS_PCIE3_MEM_BUS 0xa0000000
579#define CONFIG_SYS_PCIE3_MEM_PHYS 0xa0000000
580#endif
581#define CONFIG_SYS_PCIE3_MEM_SIZE 0x10000000
582#define CONFIG_SYS_PCIE3_IO_VIRT 0xf8020000
583#define CONFIG_SYS_PCIE3_IO_BUS 0x00000000
584#ifdef CONFIG_PHYS_64BIT
585#define CONFIG_SYS_PCIE3_IO_PHYS 0xff8020000ull
586#else
587#define CONFIG_SYS_PCIE3_IO_PHYS 0xf8020000
588#endif
589#define CONFIG_SYS_PCIE3_IO_SIZE 0x00010000
590#endif
591
592
593#ifdef CONFIG_PCIE4
594#define CONFIG_SYS_PCIE4_MEM_VIRT 0xb0000000
595#ifdef CONFIG_PHYS_64BIT
596#define CONFIG_SYS_PCIE4_MEM_BUS 0xe0000000
597#define CONFIG_SYS_PCIE4_MEM_PHYS 0xc30000000ull
598#else
599#define CONFIG_SYS_PCIE4_MEM_BUS 0xb0000000
600#define CONFIG_SYS_PCIE4_MEM_PHYS 0xb0000000
601#endif
602#define CONFIG_SYS_PCIE4_MEM_SIZE 0x10000000
603#define CONFIG_SYS_PCIE4_IO_VIRT 0xf8030000
604#define CONFIG_SYS_PCIE4_IO_BUS 0x00000000
605#ifdef CONFIG_PHYS_64BIT
606#define CONFIG_SYS_PCIE4_IO_PHYS 0xff8030000ull
607#else
608#define CONFIG_SYS_PCIE4_IO_PHYS 0xf8030000
609#endif
610#define CONFIG_SYS_PCIE4_IO_SIZE 0x00010000
611#endif
612
613#define CONFIG_PCI_SCAN_SHOW
614#endif
615
616
617
618
619#define CONFIG_HAS_FSL_DR_USB
620
621#ifdef CONFIG_HAS_FSL_DR_USB
622#define CONFIG_USB_EHCI_FSL
623#define CONFIG_EHCI_HCD_INIT_AFTER_RESET
624#endif
625
626
627
628
629#ifdef CONFIG_MMC
630#define CONFIG_SYS_FSL_ESDHC_ADDR CONFIG_SYS_MPC85xx_ESDHC_ADDR
631#endif
632
633
634#ifndef CONFIG_NOBQFMAN
635#define CONFIG_SYS_BMAN_NUM_PORTALS 10
636#define CONFIG_SYS_BMAN_MEM_BASE 0xf4000000
637#ifdef CONFIG_PHYS_64BIT
638#define CONFIG_SYS_BMAN_MEM_PHYS 0xff4000000ull
639#else
640#define CONFIG_SYS_BMAN_MEM_PHYS CONFIG_SYS_BMAN_MEM_BASE
641#endif
642#define CONFIG_SYS_BMAN_MEM_SIZE 0x02000000
643#define CONFIG_SYS_BMAN_SP_CENA_SIZE 0x4000
644#define CONFIG_SYS_BMAN_SP_CINH_SIZE 0x1000
645#define CONFIG_SYS_BMAN_CENA_BASE CONFIG_SYS_BMAN_MEM_BASE
646#define CONFIG_SYS_BMAN_CENA_SIZE (CONFIG_SYS_BMAN_MEM_SIZE >> 1)
647#define CONFIG_SYS_BMAN_CINH_BASE (CONFIG_SYS_BMAN_MEM_BASE + \
648 CONFIG_SYS_BMAN_CENA_SIZE)
649#define CONFIG_SYS_BMAN_CINH_SIZE (CONFIG_SYS_BMAN_MEM_SIZE >> 1)
650#define CONFIG_SYS_BMAN_SWP_ISDR_REG 0xE08
651#define CONFIG_SYS_QMAN_NUM_PORTALS 10
652#define CONFIG_SYS_QMAN_MEM_BASE 0xf6000000
653#ifdef CONFIG_PHYS_64BIT
654#define CONFIG_SYS_QMAN_MEM_PHYS 0xff6000000ull
655#else
656#define CONFIG_SYS_QMAN_MEM_PHYS CONFIG_SYS_QMAN_MEM_BASE
657#endif
658#define CONFIG_SYS_QMAN_MEM_SIZE 0x02000000
659#define CONFIG_SYS_QMAN_SP_CENA_SIZE 0x4000
660#define CONFIG_SYS_QMAN_SP_CINH_SIZE 0x1000
661#define CONFIG_SYS_QMAN_CENA_BASE CONFIG_SYS_QMAN_MEM_BASE
662#define CONFIG_SYS_QMAN_CENA_SIZE (CONFIG_SYS_QMAN_MEM_SIZE >> 1)
663#define CONFIG_SYS_QMAN_CINH_BASE (CONFIG_SYS_QMAN_MEM_BASE + \
664 CONFIG_SYS_QMAN_CENA_SIZE)
665#define CONFIG_SYS_QMAN_CINH_SIZE (CONFIG_SYS_QMAN_MEM_SIZE >> 1)
666#define CONFIG_SYS_QMAN_SWP_ISDR_REG 0xE08
667
668#define CONFIG_SYS_DPAA_FMAN
669
670#ifdef CONFIG_TARGET_T1024RDB
671#define CONFIG_QE
672#define CONFIG_U_QE
673#endif
674
675#if defined(CONFIG_SPIFLASH)
676
677
678
679
680#define CONFIG_SYS_QE_FW_IN_SPIFLASH
681#define CONFIG_SYS_FMAN_FW_ADDR 0x110000
682#define CONFIG_SYS_QE_FW_ADDR 0x130000
683#elif defined(CONFIG_SDCARD)
684
685
686
687
688
689#define CONFIG_SYS_QE_FMAN_FW_IN_MMC
690#define CONFIG_SYS_FMAN_FW_ADDR (512 * 0x820)
691#define CONFIG_SYS_QE_FW_ADDR (512 * 0x920)
692#elif defined(CONFIG_NAND)
693#define CONFIG_SYS_QE_FMAN_FW_IN_NAND
694#if defined(CONFIG_TARGET_T1024RDB)
695#define CONFIG_SYS_FMAN_FW_ADDR (3 * CONFIG_SYS_NAND_BLOCK_SIZE)
696#define CONFIG_SYS_QE_FW_ADDR (4 * CONFIG_SYS_NAND_BLOCK_SIZE)
697#elif defined(CONFIG_TARGET_T1023RDB)
698#define CONFIG_SYS_FMAN_FW_ADDR (11 * CONFIG_SYS_NAND_BLOCK_SIZE)
699#define CONFIG_SYS_QE_FW_ADDR (12 * CONFIG_SYS_NAND_BLOCK_SIZE)
700#endif
701#elif defined(CONFIG_SRIO_PCIE_BOOT_SLAVE)
702
703
704
705
706
707
708
709#define CONFIG_SYS_QE_FMAN_FW_IN_REMOTE
710#define CONFIG_SYS_FMAN_FW_ADDR 0xFFE00000
711#else
712#define CONFIG_SYS_QE_FMAN_FW_IN_NOR
713#define CONFIG_SYS_FMAN_FW_ADDR 0xEFF00000
714#define CONFIG_SYS_QE_FW_ADDR 0xEFE00000
715#endif
716#define CONFIG_SYS_QE_FMAN_FW_LENGTH 0x10000
717#define CONFIG_SYS_FDT_PAD (0x3000 + CONFIG_SYS_QE_FMAN_FW_LENGTH)
718#endif
719
720#ifdef CONFIG_SYS_DPAA_FMAN
721#define CONFIG_FMAN_ENET
722#define CONFIG_PHYLIB_10G
723#define CONFIG_PHY_REALTEK
724#define CONFIG_PHY_AQUANTIA
725#if defined(CONFIG_TARGET_T1024RDB)
726#define RGMII_PHY1_ADDR 0x2
727#define RGMII_PHY2_ADDR 0x6
728#define SGMII_AQR_PHY_ADDR 0x2
729#define FM1_10GEC1_PHY_ADDR 0x1
730#elif defined(CONFIG_TARGET_T1023RDB)
731#define RGMII_PHY1_ADDR 0x1
732#define SGMII_RTK_PHY_ADDR 0x3
733#define SGMII_AQR_PHY_ADDR 0x2
734#endif
735#endif
736
737#ifdef CONFIG_FMAN_ENET
738#define CONFIG_ETHPRIME "FM1@DTSEC4"
739#endif
740
741
742
743
744#ifdef CONFIG_MTD_NOR_FLASH
745#define CONFIG_FLASH_CFI_MTD
746#endif
747
748
749
750
751#define CONFIG_LOADS_ECHO
752#define CONFIG_SYS_LOADS_BAUD_CHANGE
753
754
755
756
757#define CONFIG_SYS_LOAD_ADDR 0x2000000
758
759
760
761
762
763
764#define CONFIG_SYS_BOOTMAPSZ (64 << 20)
765#define CONFIG_SYS_BOOTM_LEN (64 << 20)
766
767#ifdef CONFIG_CMD_KGDB
768#define CONFIG_KGDB_BAUDRATE 230400
769#endif
770
771
772
773
774#define CONFIG_ROOTPATH "/opt/nfsroot"
775#define CONFIG_BOOTFILE "uImage"
776#define CONFIG_UBOOTPATH u-boot.bin
777#define CONFIG_LOADADDR 1000000
778#define __USB_PHY_TYPE utmi
779
780#ifdef CONFIG_ARCH_T1024
781#define CONFIG_BOARDNAME t1024rdb
782#define BANK_INTLV cs0_cs1
783#else
784#define CONFIG_BOARDNAME t1023rdb
785#define BANK_INTLV null
786#endif
787
788#define CONFIG_EXTRA_ENV_SETTINGS \
789 "hwconfig=fsl_ddr:ctlr_intlv=cacheline," \
790 "bank_intlv=" __stringify(BANK_INTLV) "\0" \
791 "usb1:dr_mode=host,phy_type=" __stringify(__USB_PHY_TYPE) "\0" \
792 "ramdiskfile=" __stringify(CONFIG_BOARDNAME) "/ramdisk.uboot\0" \
793 "fdtfile=" __stringify(CONFIG_BOARDNAME) "/" \
794 __stringify(CONFIG_BOARDNAME) ".dtb\0" \
795 "uboot=" __stringify(CONFIG_UBOOTPATH) "\0" \
796 "ubootaddr=" __stringify(CONFIG_SYS_TEXT_BASE) "\0" \
797 "bootargs=root=/dev/ram rw console=ttyS0,115200\0" \
798 "netdev=eth0\0" \
799 "tftpflash=tftpboot $loadaddr $uboot && " \
800 "protect off $ubootaddr +$filesize && " \
801 "erase $ubootaddr +$filesize && " \
802 "cp.b $loadaddr $ubootaddr $filesize && " \
803 "protect on $ubootaddr +$filesize && " \
804 "cmp.b $loadaddr $ubootaddr $filesize\0" \
805 "consoledev=ttyS0\0" \
806 "ramdiskaddr=2000000\0" \
807 "fdtaddr=1e00000\0" \
808 "bdev=sda3\0"
809
810#define CONFIG_LINUX \
811 "setenv bootargs root=/dev/ram rw " \
812 "console=$consoledev,$baudrate $othbootargs;" \
813 "setenv ramdiskaddr 0x02000000;" \
814 "setenv fdtaddr 0x00c00000;" \
815 "setenv loadaddr 0x1000000;" \
816 "bootm $loadaddr $ramdiskaddr $fdtaddr"
817
818#define CONFIG_NFSBOOTCOMMAND \
819 "setenv bootargs root=/dev/nfs rw " \
820 "nfsroot=$serverip:$rootpath " \
821 "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \
822 "console=$consoledev,$baudrate $othbootargs;" \
823 "tftp $loadaddr $bootfile;" \
824 "tftp $fdtaddr $fdtfile;" \
825 "bootm $loadaddr - $fdtaddr"
826
827#define CONFIG_BOOTCOMMAND CONFIG_LINUX
828
829#include <asm/fsl_secure_boot.h>
830
831#endif
832
