1
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4
5
6#ifndef __CONFIG_H
7#define __CONFIG_H
8
9
10
11
12#include <asm/config_mpc85xx.h>
13
14#ifdef CONFIG_RAMBOOT_PBL
15
16#ifndef CONFIG_SECURE_BOOT
17#define CONFIG_SYS_FSL_PBL_PBI $(SRCTREE)/board/freescale/t104xrdb/t104x_pbi.cfg
18#else
19#define CONFIG_SYS_FSL_PBL_PBI \
20 $(SRCTREE)/board/freescale/t104xrdb/t104x_pbi_sb.cfg
21#endif
22
23#define CONFIG_SPL_FLUSH_IMAGE
24#define CONFIG_SPL_TEXT_BASE 0xFFFD8000
25#define CONFIG_SPL_PAD_TO 0x40000
26#define CONFIG_SPL_MAX_SIZE 0x28000
27#ifdef CONFIG_SPL_BUILD
28#define CONFIG_SPL_SKIP_RELOCATE
29#define CONFIG_SPL_COMMON_INIT_DDR
30#define CONFIG_SYS_CCSR_DO_NOT_RELOCATE
31#endif
32#define RESET_VECTOR_OFFSET 0x27FFC
33#define BOOT_PAGE_OFFSET 0x27000
34
35#ifdef CONFIG_NAND
36#ifdef CONFIG_SECURE_BOOT
37#define CONFIG_U_BOOT_HDR_SIZE (16 << 10)
38
39
40
41
42#define CONFIG_SYS_NAND_U_BOOT_SIZE ((768 << 10) + \
43 CONFIG_U_BOOT_HDR_SIZE)
44#else
45#define CONFIG_SYS_NAND_U_BOOT_SIZE (768 << 10)
46#endif
47#define CONFIG_SYS_NAND_U_BOOT_DST 0x30000000
48#define CONFIG_SYS_NAND_U_BOOT_START 0x30000000
49#define CONFIG_SYS_NAND_U_BOOT_OFFS (256 << 10)
50#define CONFIG_SYS_LDSCRIPT "arch/powerpc/cpu/mpc85xx/u-boot-nand.lds"
51#ifdef CONFIG_TARGET_T1040RDB
52#define CONFIG_SYS_FSL_PBL_RCW \
53$(SRCTREE)/board/freescale/t104xrdb/t1040_nand_rcw.cfg
54#endif
55#ifdef CONFIG_TARGET_T1042RDB_PI
56#define CONFIG_SYS_FSL_PBL_RCW \
57$(SRCTREE)/board/freescale/t104xrdb/t1042_pi_nand_rcw.cfg
58#endif
59#ifdef CONFIG_TARGET_T1042RDB
60#define CONFIG_SYS_FSL_PBL_RCW \
61$(SRCTREE)/board/freescale/t104xrdb/t1042_nand_rcw.cfg
62#endif
63#ifdef CONFIG_TARGET_T1040D4RDB
64#define CONFIG_SYS_FSL_PBL_RCW \
65$(SRCTREE)/board/freescale/t104xrdb/t1040d4_nand_rcw.cfg
66#endif
67#ifdef CONFIG_TARGET_T1042D4RDB
68#define CONFIG_SYS_FSL_PBL_RCW \
69$(SRCTREE)/board/freescale/t104xrdb/t1042d4_nand_rcw.cfg
70#endif
71#define CONFIG_SPL_NAND_BOOT
72#endif
73
74#ifdef CONFIG_SPIFLASH
75#define CONFIG_RESET_VECTOR_ADDRESS 0x30000FFC
76#define CONFIG_SPL_SPI_FLASH_MINIMAL
77#define CONFIG_SYS_SPI_FLASH_U_BOOT_SIZE (768 << 10)
78#define CONFIG_SYS_SPI_FLASH_U_BOOT_DST (0x30000000)
79#define CONFIG_SYS_SPI_FLASH_U_BOOT_START (0x30000000)
80#define CONFIG_SYS_SPI_FLASH_U_BOOT_OFFS (256 << 10)
81#define CONFIG_SYS_LDSCRIPT "arch/powerpc/cpu/mpc85xx/u-boot.lds"
82#ifndef CONFIG_SPL_BUILD
83#define CONFIG_SYS_MPC85XX_NO_RESETVEC
84#endif
85#ifdef CONFIG_TARGET_T1040RDB
86#define CONFIG_SYS_FSL_PBL_RCW \
87$(SRCTREE)/board/freescale/t104xrdb/t1040_spi_rcw.cfg
88#endif
89#ifdef CONFIG_TARGET_T1042RDB_PI
90#define CONFIG_SYS_FSL_PBL_RCW \
91$(SRCTREE)/board/freescale/t104xrdb/t1042_pi_spi_rcw.cfg
92#endif
93#ifdef CONFIG_TARGET_T1042RDB
94#define CONFIG_SYS_FSL_PBL_RCW \
95$(SRCTREE)/board/freescale/t104xrdb/t1042_spi_rcw.cfg
96#endif
97#ifdef CONFIG_TARGET_T1040D4RDB
98#define CONFIG_SYS_FSL_PBL_RCW \
99$(SRCTREE)/board/freescale/t104xrdb/t1040d4_spi_rcw.cfg
100#endif
101#ifdef CONFIG_TARGET_T1042D4RDB
102#define CONFIG_SYS_FSL_PBL_RCW \
103$(SRCTREE)/board/freescale/t104xrdb/t1042d4_spi_rcw.cfg
104#endif
105#define CONFIG_SPL_SPI_BOOT
106#endif
107
108#ifdef CONFIG_SDCARD
109#define CONFIG_RESET_VECTOR_ADDRESS 0x30000FFC
110#define CONFIG_SYS_MMC_U_BOOT_SIZE (768 << 10)
111#define CONFIG_SYS_MMC_U_BOOT_DST (0x30000000)
112#define CONFIG_SYS_MMC_U_BOOT_START (0x30000000)
113#define CONFIG_SYS_MMC_U_BOOT_OFFS (260 << 10)
114#define CONFIG_SYS_LDSCRIPT "arch/powerpc/cpu/mpc85xx/u-boot.lds"
115#ifndef CONFIG_SPL_BUILD
116#define CONFIG_SYS_MPC85XX_NO_RESETVEC
117#endif
118#ifdef CONFIG_TARGET_T1040RDB
119#define CONFIG_SYS_FSL_PBL_RCW \
120$(SRCTREE)/board/freescale/t104xrdb/t1040_sd_rcw.cfg
121#endif
122#ifdef CONFIG_TARGET_T1042RDB_PI
123#define CONFIG_SYS_FSL_PBL_RCW \
124$(SRCTREE)/board/freescale/t104xrdb/t1042_pi_sd_rcw.cfg
125#endif
126#ifdef CONFIG_TARGET_T1042RDB
127#define CONFIG_SYS_FSL_PBL_RCW \
128$(SRCTREE)/board/freescale/t104xrdb/t1042_sd_rcw.cfg
129#endif
130#ifdef CONFIG_TARGET_T1040D4RDB
131#define CONFIG_SYS_FSL_PBL_RCW \
132$(SRCTREE)/board/freescale/t104xrdb/t1040d4_sd_rcw.cfg
133#endif
134#ifdef CONFIG_TARGET_T1042D4RDB
135#define CONFIG_SYS_FSL_PBL_RCW \
136$(SRCTREE)/board/freescale/t104xrdb/t1042d4_sd_rcw.cfg
137#endif
138#define CONFIG_SPL_MMC_BOOT
139#endif
140
141#endif
142
143
144#define CONFIG_SYS_BOOK3E_HV
145
146
147#define CONFIG_DEEP_SLEEP
148
149#ifndef CONFIG_RESET_VECTOR_ADDRESS
150#define CONFIG_RESET_VECTOR_ADDRESS 0xeffffffc
151#endif
152
153#define CONFIG_SYS_FSL_CPC
154#define CONFIG_SYS_NUM_CPC CONFIG_SYS_NUM_DDR_CTLRS
155#define CONFIG_PCI_INDIRECT_BRIDGE
156#define CONFIG_PCIE1
157#define CONFIG_PCIE2
158#define CONFIG_PCIE3
159#define CONFIG_PCIE4
160
161#define CONFIG_FSL_PCI_INIT
162#define CONFIG_SYS_PCI_64BIT
163
164#define CONFIG_ENV_OVERWRITE
165
166#ifdef CONFIG_MTD_NOR_FLASH
167#define CONFIG_FLASH_CFI_DRIVER
168#define CONFIG_SYS_FLASH_CFI
169#define CONFIG_SYS_FLASH_USE_BUFFER_WRITE
170#endif
171
172#if defined(CONFIG_SPIFLASH)
173#define CONFIG_SYS_EXTRA_ENV_RELOC
174#define CONFIG_ENV_SIZE 0x2000
175#define CONFIG_ENV_OFFSET 0x100000
176#define CONFIG_ENV_SECT_SIZE 0x10000
177#elif defined(CONFIG_SDCARD)
178#define CONFIG_SYS_EXTRA_ENV_RELOC
179#define CONFIG_SYS_MMC_ENV_DEV 0
180#define CONFIG_ENV_SIZE 0x2000
181#define CONFIG_ENV_OFFSET (512 * 0x800)
182#elif defined(CONFIG_NAND)
183#ifdef CONFIG_SECURE_BOOT
184#define CONFIG_RAMBOOT_NAND
185#define CONFIG_BOOTSCRIPT_COPY_RAM
186#endif
187#define CONFIG_SYS_EXTRA_ENV_RELOC
188#define CONFIG_ENV_SIZE 0x2000
189#define CONFIG_ENV_OFFSET (3 * CONFIG_SYS_NAND_BLOCK_SIZE)
190#else
191#define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - CONFIG_ENV_SECT_SIZE)
192#define CONFIG_ENV_SIZE 0x2000
193#define CONFIG_ENV_SECT_SIZE 0x20000
194#endif
195
196#define CONFIG_SYS_CLK_FREQ 100000000
197#define CONFIG_DDR_CLK_FREQ 66666666
198
199
200
201
202#define CONFIG_SYS_CACHE_STASHING
203#define CONFIG_BACKSIDE_L2_CACHE
204#define CONFIG_SYS_INIT_L2CSR0 L2CSR0_L2E
205#define CONFIG_BTB
206#define CONFIG_DDR_ECC
207#ifdef CONFIG_DDR_ECC
208#define CONFIG_ECC_INIT_VIA_DDRCONTROLLER
209#define CONFIG_MEM_INIT_VALUE 0xdeadbeef
210#endif
211
212#define CONFIG_ENABLE_36BIT_PHYS
213
214#define CONFIG_ADDR_MAP
215#define CONFIG_SYS_NUM_ADDR_MAP 64
216
217#define CONFIG_SYS_MEMTEST_START 0x00200000
218#define CONFIG_SYS_MEMTEST_END 0x00400000
219
220
221
222
223#define CONFIG_SYS_INIT_L3_ADDR 0xFFFC0000
224
225
226
227
228
229#define CONFIG_SYS_INIT_L3_VADDR 0xFFFC0000
230#define CONFIG_SYS_L3_SIZE 256 << 10
231#define CONFIG_SPL_GD_ADDR (CONFIG_SYS_INIT_L3_VADDR + 32 * 1024)
232#ifdef CONFIG_RAMBOOT_PBL
233#define CONFIG_ENV_ADDR (CONFIG_SPL_GD_ADDR + 4 * 1024)
234#endif
235#define CONFIG_SPL_RELOC_MALLOC_ADDR (CONFIG_SPL_GD_ADDR + 12 * 1024)
236#define CONFIG_SPL_RELOC_MALLOC_SIZE (30 << 10)
237#define CONFIG_SPL_RELOC_STACK (CONFIG_SPL_GD_ADDR + 64 * 1024)
238
239#define CONFIG_SYS_DCSRBAR 0xf0000000
240#define CONFIG_SYS_DCSRBAR_PHYS 0xf00000000ull
241
242
243
244
245#define CONFIG_VERY_BIG_RAM
246#define CONFIG_SYS_DDR_SDRAM_BASE 0x00000000
247#define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE
248
249#define CONFIG_DIMM_SLOTS_PER_CTLR 1
250#define CONFIG_CHIP_SELECTS_PER_CTRL (2 * CONFIG_DIMM_SLOTS_PER_CTLR)
251
252#define CONFIG_DDR_SPD
253
254#define CONFIG_SYS_SPD_BUS_NUM 0
255#define SPD_EEPROM_ADDRESS 0x51
256
257#define CONFIG_SYS_SDRAM_SIZE 4096
258
259
260
261
262#define CONFIG_SYS_FLASH_BASE 0xe8000000
263#define CONFIG_SYS_FLASH_BASE_PHYS (0xf00000000ull | CONFIG_SYS_FLASH_BASE)
264
265#define CONFIG_SYS_NOR_CSPR_EXT (0xf)
266#define CONFIG_SYS_NOR_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE) | \
267 CSPR_PORT_SIZE_16 | \
268 CSPR_MSEL_NOR | \
269 CSPR_V)
270#define CONFIG_SYS_NOR_AMASK IFC_AMASK(128*1024*1024)
271
272
273
274
275#define T1040_TDM_QUIRK_CCSR_BASE 0xfe000000
276
277
278#define CONFIG_SYS_NOR_CSOR CSOR_NAND_TRHZ_80
279#define CONFIG_SYS_NOR_FTIM0 (FTIM0_NOR_TACSE(0x4) | \
280 FTIM0_NOR_TEADC(0x5) | \
281 FTIM0_NOR_TEAHC(0x5))
282#define CONFIG_SYS_NOR_FTIM1 (FTIM1_NOR_TACO(0x35) | \
283 FTIM1_NOR_TRAD_NOR(0x1A) |\
284 FTIM1_NOR_TSEQRAD_NOR(0x13))
285#define CONFIG_SYS_NOR_FTIM2 (FTIM2_NOR_TCS(0x4) | \
286 FTIM2_NOR_TCH(0x4) | \
287 FTIM2_NOR_TWPH(0x0E) | \
288 FTIM2_NOR_TWP(0x1c))
289#define CONFIG_SYS_NOR_FTIM3 0x0
290
291#define CONFIG_SYS_FLASH_QUIET_TEST
292#define CONFIG_FLASH_SHOW_PROGRESS 45
293
294#define CONFIG_SYS_MAX_FLASH_BANKS 2
295#define CONFIG_SYS_MAX_FLASH_SECT 1024
296#define CONFIG_SYS_FLASH_ERASE_TOUT 60000
297#define CONFIG_SYS_FLASH_WRITE_TOUT 500
298
299#define CONFIG_SYS_FLASH_EMPTY_INFO
300#define CONFIG_SYS_FLASH_BANKS_LIST {CONFIG_SYS_FLASH_BASE_PHYS}
301
302
303#define CPLD_LBMAP_MASK 0x3F
304#define CPLD_BANK_SEL_MASK 0x07
305#define CPLD_BANK_OVERRIDE 0x40
306#define CPLD_LBMAP_ALTBANK 0x44
307#define CPLD_LBMAP_DFLTBANK 0x40
308#define CPLD_LBMAP_RESET 0xFF
309#define CPLD_LBMAP_SHIFT 0x03
310
311#if defined(CONFIG_TARGET_T1042RDB_PI)
312#define CPLD_DIU_SEL_DFP 0x80
313#elif defined(CONFIG_TARGET_T1042D4RDB)
314#define CPLD_DIU_SEL_DFP 0xc0
315#endif
316
317#if defined(CONFIG_TARGET_T1040D4RDB)
318#define CPLD_INT_MASK_ALL 0xFF
319#define CPLD_INT_MASK_THERM 0x80
320#define CPLD_INT_MASK_DVI_DFP 0x40
321#define CPLD_INT_MASK_QSGMII1 0x20
322#define CPLD_INT_MASK_QSGMII2 0x10
323#define CPLD_INT_MASK_SGMI1 0x08
324#define CPLD_INT_MASK_SGMI2 0x04
325#define CPLD_INT_MASK_TDMR1 0x02
326#define CPLD_INT_MASK_TDMR2 0x01
327#endif
328
329#define CONFIG_SYS_CPLD_BASE 0xffdf0000
330#define CONFIG_SYS_CPLD_BASE_PHYS (0xf00000000ull | CONFIG_SYS_CPLD_BASE)
331#define CONFIG_SYS_CSPR2_EXT (0xf)
332#define CONFIG_SYS_CSPR2 (CSPR_PHYS_ADDR(CONFIG_SYS_CPLD_BASE_PHYS) \
333 | CSPR_PORT_SIZE_8 \
334 | CSPR_MSEL_GPCM \
335 | CSPR_V)
336#define CONFIG_SYS_AMASK2 IFC_AMASK(64*1024)
337#define CONFIG_SYS_CSOR2 0x0
338
339#define CONFIG_SYS_CS2_FTIM0 (FTIM0_GPCM_TACSE(0x0e) | \
340 FTIM0_GPCM_TEADC(0x0e) | \
341 FTIM0_GPCM_TEAHC(0x0e))
342#define CONFIG_SYS_CS2_FTIM1 (FTIM1_GPCM_TACO(0x0e) | \
343 FTIM1_GPCM_TRAD(0x1f))
344#define CONFIG_SYS_CS2_FTIM2 (FTIM2_GPCM_TCS(0x0e) | \
345 FTIM2_GPCM_TCH(0x8) | \
346 FTIM2_GPCM_TWP(0x1f))
347#define CONFIG_SYS_CS2_FTIM3 0x0
348
349
350#define CONFIG_NAND_FSL_IFC
351#define CONFIG_SYS_NAND_BASE 0xff800000
352#define CONFIG_SYS_NAND_BASE_PHYS (0xf00000000ull | CONFIG_SYS_NAND_BASE)
353
354#define CONFIG_SYS_NAND_CSPR_EXT (0xf)
355#define CONFIG_SYS_NAND_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS) \
356 | CSPR_PORT_SIZE_8 \
357 | CSPR_MSEL_NAND \
358 | CSPR_V)
359#define CONFIG_SYS_NAND_AMASK IFC_AMASK(64*1024)
360
361#define CONFIG_SYS_NAND_CSOR (CSOR_NAND_ECC_ENC_EN \
362 | CSOR_NAND_ECC_DEC_EN \
363 | CSOR_NAND_ECC_MODE_4 \
364 | CSOR_NAND_RAL_3 \
365 | CSOR_NAND_PGS_4K \
366 | CSOR_NAND_SPRZ_224 \
367 | CSOR_NAND_PB(64))
368
369#define CONFIG_SYS_NAND_ONFI_DETECTION
370
371
372#define CONFIG_SYS_NAND_FTIM0 (FTIM0_NAND_TCCST(0x07) | \
373 FTIM0_NAND_TWP(0x18) | \
374 FTIM0_NAND_TWCHT(0x07) | \
375 FTIM0_NAND_TWH(0x0a))
376#define CONFIG_SYS_NAND_FTIM1 (FTIM1_NAND_TADLE(0x32) | \
377 FTIM1_NAND_TWBE(0x39) | \
378 FTIM1_NAND_TRR(0x0e) | \
379 FTIM1_NAND_TRP(0x18))
380#define CONFIG_SYS_NAND_FTIM2 (FTIM2_NAND_TRAD(0x0f) | \
381 FTIM2_NAND_TREH(0x0a) | \
382 FTIM2_NAND_TWHRE(0x1e))
383#define CONFIG_SYS_NAND_FTIM3 0x0
384
385#define CONFIG_SYS_NAND_DDR_LAW 11
386#define CONFIG_SYS_NAND_BASE_LIST { CONFIG_SYS_NAND_BASE }
387#define CONFIG_SYS_MAX_NAND_DEVICE 1
388
389#define CONFIG_SYS_NAND_BLOCK_SIZE (512 * 1024)
390
391#if defined(CONFIG_NAND)
392#define CONFIG_SYS_CSPR0_EXT CONFIG_SYS_NAND_CSPR_EXT
393#define CONFIG_SYS_CSPR0 CONFIG_SYS_NAND_CSPR
394#define CONFIG_SYS_AMASK0 CONFIG_SYS_NAND_AMASK
395#define CONFIG_SYS_CSOR0 CONFIG_SYS_NAND_CSOR
396#define CONFIG_SYS_CS0_FTIM0 CONFIG_SYS_NAND_FTIM0
397#define CONFIG_SYS_CS0_FTIM1 CONFIG_SYS_NAND_FTIM1
398#define CONFIG_SYS_CS0_FTIM2 CONFIG_SYS_NAND_FTIM2
399#define CONFIG_SYS_CS0_FTIM3 CONFIG_SYS_NAND_FTIM3
400#define CONFIG_SYS_CSPR1_EXT CONFIG_SYS_NOR_CSPR_EXT
401#define CONFIG_SYS_CSPR1 CONFIG_SYS_NOR_CSPR
402#define CONFIG_SYS_AMASK1 CONFIG_SYS_NOR_AMASK
403#define CONFIG_SYS_CSOR1 CONFIG_SYS_NOR_CSOR
404#define CONFIG_SYS_CS1_FTIM0 CONFIG_SYS_NOR_FTIM0
405#define CONFIG_SYS_CS1_FTIM1 CONFIG_SYS_NOR_FTIM1
406#define CONFIG_SYS_CS1_FTIM2 CONFIG_SYS_NOR_FTIM2
407#define CONFIG_SYS_CS1_FTIM3 CONFIG_SYS_NOR_FTIM3
408#else
409#define CONFIG_SYS_CSPR0_EXT CONFIG_SYS_NOR_CSPR_EXT
410#define CONFIG_SYS_CSPR0 CONFIG_SYS_NOR_CSPR
411#define CONFIG_SYS_AMASK0 CONFIG_SYS_NOR_AMASK
412#define CONFIG_SYS_CSOR0 CONFIG_SYS_NOR_CSOR
413#define CONFIG_SYS_CS0_FTIM0 CONFIG_SYS_NOR_FTIM0
414#define CONFIG_SYS_CS0_FTIM1 CONFIG_SYS_NOR_FTIM1
415#define CONFIG_SYS_CS0_FTIM2 CONFIG_SYS_NOR_FTIM2
416#define CONFIG_SYS_CS0_FTIM3 CONFIG_SYS_NOR_FTIM3
417#define CONFIG_SYS_CSPR1_EXT CONFIG_SYS_NAND_CSPR_EXT
418#define CONFIG_SYS_CSPR1 CONFIG_SYS_NAND_CSPR
419#define CONFIG_SYS_AMASK1 CONFIG_SYS_NAND_AMASK
420#define CONFIG_SYS_CSOR1 CONFIG_SYS_NAND_CSOR
421#define CONFIG_SYS_CS1_FTIM0 CONFIG_SYS_NAND_FTIM0
422#define CONFIG_SYS_CS1_FTIM1 CONFIG_SYS_NAND_FTIM1
423#define CONFIG_SYS_CS1_FTIM2 CONFIG_SYS_NAND_FTIM2
424#define CONFIG_SYS_CS1_FTIM3 CONFIG_SYS_NAND_FTIM3
425#endif
426
427#ifdef CONFIG_SPL_BUILD
428#define CONFIG_SYS_MONITOR_BASE CONFIG_SPL_TEXT_BASE
429#else
430#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE
431#endif
432
433#if defined(CONFIG_RAMBOOT_PBL)
434#define CONFIG_SYS_RAMBOOT
435#endif
436
437#ifdef CONFIG_SYS_FSL_ERRATUM_A008044
438#if defined(CONFIG_NAND)
439#define CONFIG_A008044_WORKAROUND
440#endif
441#endif
442
443#define CONFIG_HWCONFIG
444
445
446#define CONFIG_L1_INIT_RAM
447#define CONFIG_SYS_INIT_RAM_LOCK
448#define CONFIG_SYS_INIT_RAM_ADDR 0xfdd00000
449#define CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH 0xf
450#define CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW 0xfe03c000
451
452#define CONFIG_SYS_INIT_RAM_ADDR_PHYS \
453 ((CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH * 1ull << 32) | \
454 CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW)
455#define CONFIG_SYS_INIT_RAM_SIZE 0x00004000
456
457#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - \
458 GENERATED_GBL_DATA_SIZE)
459#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
460
461#define CONFIG_SYS_MONITOR_LEN (768 * 1024)
462#define CONFIG_SYS_MALLOC_LEN (4 * 1024 * 1024)
463
464
465
466
467
468#define CONFIG_SYS_NS16550_SERIAL
469#define CONFIG_SYS_NS16550_REG_SIZE 1
470#define CONFIG_SYS_NS16550_CLK (get_bus_freq(0)/2)
471
472#define CONFIG_SYS_BAUDRATE_TABLE \
473 {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200}
474
475#define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_CCSRBAR+0x11C500)
476#define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_CCSRBAR+0x11C600)
477#define CONFIG_SYS_NS16550_COM3 (CONFIG_SYS_CCSRBAR+0x11D500)
478#define CONFIG_SYS_NS16550_COM4 (CONFIG_SYS_CCSRBAR+0x11D600)
479
480#if defined(CONFIG_TARGET_T1042RDB_PI) || defined(CONFIG_TARGET_T1042D4RDB)
481
482#define CONFIG_FSL_DIU_FB
483
484#ifdef CONFIG_FSL_DIU_FB
485#define CONFIG_FSL_DIU_CH7301
486#define CONFIG_SYS_DIU_ADDR (CONFIG_SYS_CCSRBAR + 0x180000)
487#define CONFIG_VIDEO_LOGO
488#define CONFIG_VIDEO_BMP_LOGO
489#endif
490#endif
491
492
493#define CONFIG_SYS_I2C
494#define CONFIG_SYS_I2C_FSL
495#define CONFIG_SYS_FSL_I2C_SPEED 400000
496#define CONFIG_SYS_FSL_I2C2_SPEED 400000
497#define CONFIG_SYS_FSL_I2C3_SPEED 400000
498#define CONFIG_SYS_FSL_I2C4_SPEED 400000
499#define CONFIG_SYS_FSL_I2C_SLAVE 0x7F
500#define CONFIG_SYS_FSL_I2C2_SLAVE 0x7F
501#define CONFIG_SYS_FSL_I2C3_SLAVE 0x7F
502#define CONFIG_SYS_FSL_I2C4_SLAVE 0x7F
503#define CONFIG_SYS_FSL_I2C_OFFSET 0x118000
504#define CONFIG_SYS_FSL_I2C2_OFFSET 0x118100
505#define CONFIG_SYS_FSL_I2C3_OFFSET 0x119000
506#define CONFIG_SYS_FSL_I2C4_OFFSET 0x119100
507
508
509#define I2C_MUX_PCA_ADDR 0x70
510#define I2C_MUX_CH_DEFAULT 0x8
511
512#if defined(CONFIG_TARGET_T1042RDB_PI) || \
513 defined(CONFIG_TARGET_T1040D4RDB) || \
514 defined(CONFIG_TARGET_T1042D4RDB)
515
516#define CONFIG_SYS_I2C_LDI_ADDR 0x38
517#define CONFIG_SYS_I2C_DVI_ADDR 0x75
518
519
520
521
522#define RTC
523#define CONFIG_RTC_DS1337 1
524#define CONFIG_SYS_I2C_RTC_ADDR 0x68
525
526
527#define CONFIG_HDMI_ENCODER_I2C_ADDR 0x75
528#endif
529
530
531
532
533#define CONFIG_SPI_FLASH_BAR
534#define CONFIG_SF_DEFAULT_SPEED 10000000
535#define CONFIG_SF_DEFAULT_MODE 0
536#define CONFIG_ENV_SPI_BUS 0
537#define CONFIG_ENV_SPI_CS 0
538#define CONFIG_ENV_SPI_MAX_HZ 10000000
539#define CONFIG_ENV_SPI_MODE 0
540
541
542
543
544
545
546#ifdef CONFIG_PCI
547
548#ifdef CONFIG_PCIE1
549#define CONFIG_SYS_PCIE1_MEM_VIRT 0x80000000
550#define CONFIG_SYS_PCIE1_MEM_BUS 0xe0000000
551#define CONFIG_SYS_PCIE1_MEM_PHYS 0xc00000000ull
552#define CONFIG_SYS_PCIE1_MEM_SIZE 0x10000000
553#define CONFIG_SYS_PCIE1_IO_VIRT 0xf8000000
554#define CONFIG_SYS_PCIE1_IO_BUS 0x00000000
555#define CONFIG_SYS_PCIE1_IO_PHYS 0xff8000000ull
556#define CONFIG_SYS_PCIE1_IO_SIZE 0x00010000
557#endif
558
559
560#ifdef CONFIG_PCIE2
561#define CONFIG_SYS_PCIE2_MEM_VIRT 0x90000000
562#define CONFIG_SYS_PCIE2_MEM_BUS 0xe0000000
563#define CONFIG_SYS_PCIE2_MEM_PHYS 0xc10000000ull
564#define CONFIG_SYS_PCIE2_MEM_SIZE 0x10000000
565#define CONFIG_SYS_PCIE2_IO_VIRT 0xf8010000
566#define CONFIG_SYS_PCIE2_IO_BUS 0x00000000
567#define CONFIG_SYS_PCIE2_IO_PHYS 0xff8010000ull
568#define CONFIG_SYS_PCIE2_IO_SIZE 0x00010000
569#endif
570
571
572#ifdef CONFIG_PCIE3
573#define CONFIG_SYS_PCIE3_MEM_VIRT 0xa0000000
574#define CONFIG_SYS_PCIE3_MEM_BUS 0xe0000000
575#define CONFIG_SYS_PCIE3_MEM_PHYS 0xc20000000ull
576#define CONFIG_SYS_PCIE3_MEM_SIZE 0x10000000
577#define CONFIG_SYS_PCIE3_IO_VIRT 0xf8020000
578#define CONFIG_SYS_PCIE3_IO_BUS 0x00000000
579#define CONFIG_SYS_PCIE3_IO_PHYS 0xff8020000ull
580#define CONFIG_SYS_PCIE3_IO_SIZE 0x00010000
581#endif
582
583
584#ifdef CONFIG_PCIE4
585#define CONFIG_SYS_PCIE4_MEM_VIRT 0xb0000000
586#define CONFIG_SYS_PCIE4_MEM_BUS 0xe0000000
587#define CONFIG_SYS_PCIE4_MEM_PHYS 0xc30000000ull
588#define CONFIG_SYS_PCIE4_MEM_SIZE 0x10000000
589#define CONFIG_SYS_PCIE4_IO_VIRT 0xf8030000
590#define CONFIG_SYS_PCIE4_IO_BUS 0x00000000
591#define CONFIG_SYS_PCIE4_IO_PHYS 0xff8030000ull
592#define CONFIG_SYS_PCIE4_IO_SIZE 0x00010000
593#endif
594
595#define CONFIG_PCI_SCAN_SHOW
596#endif
597
598
599#define CONFIG_FSL_SATA_V2
600#ifdef CONFIG_FSL_SATA_V2
601#define CONFIG_SYS_SATA_MAX_DEVICE 1
602#define CONFIG_SATA1
603#define CONFIG_SYS_SATA1 CONFIG_SYS_MPC85xx_SATA1_ADDR
604#define CONFIG_SYS_SATA1_FLAGS FLAGS_DMA
605
606#define CONFIG_LBA48
607#endif
608
609
610
611
612#define CONFIG_HAS_FSL_DR_USB
613
614#ifdef CONFIG_HAS_FSL_DR_USB
615#ifdef CONFIG_USB_EHCI_HCD
616#define CONFIG_USB_EHCI_FSL
617#define CONFIG_EHCI_HCD_INIT_AFTER_RESET
618#endif
619#endif
620
621#ifdef CONFIG_MMC
622#define CONFIG_SYS_FSL_ESDHC_ADDR CONFIG_SYS_MPC85xx_ESDHC_ADDR
623#endif
624
625
626#ifndef CONFIG_NOBQFMAN
627#define CONFIG_SYS_BMAN_NUM_PORTALS 10
628#define CONFIG_SYS_BMAN_MEM_BASE 0xf4000000
629#define CONFIG_SYS_BMAN_MEM_PHYS 0xff4000000ull
630#define CONFIG_SYS_BMAN_MEM_SIZE 0x02000000
631#define CONFIG_SYS_BMAN_SP_CENA_SIZE 0x4000
632#define CONFIG_SYS_BMAN_SP_CINH_SIZE 0x1000
633#define CONFIG_SYS_BMAN_CENA_BASE CONFIG_SYS_BMAN_MEM_BASE
634#define CONFIG_SYS_BMAN_CENA_SIZE (CONFIG_SYS_BMAN_MEM_SIZE >> 1)
635#define CONFIG_SYS_BMAN_CINH_BASE (CONFIG_SYS_BMAN_MEM_BASE + \
636 CONFIG_SYS_BMAN_CENA_SIZE)
637#define CONFIG_SYS_BMAN_CINH_SIZE (CONFIG_SYS_BMAN_MEM_SIZE >> 1)
638#define CONFIG_SYS_BMAN_SWP_ISDR_REG 0xE08
639#define CONFIG_SYS_QMAN_NUM_PORTALS 10
640#define CONFIG_SYS_QMAN_MEM_BASE 0xf6000000
641#define CONFIG_SYS_QMAN_MEM_PHYS 0xff6000000ull
642#define CONFIG_SYS_QMAN_MEM_SIZE 0x02000000
643#define CONFIG_SYS_QMAN_SP_CENA_SIZE 0x4000
644#define CONFIG_SYS_QMAN_SP_CINH_SIZE 0x1000
645#define CONFIG_SYS_QMAN_CENA_BASE CONFIG_SYS_QMAN_MEM_BASE
646#define CONFIG_SYS_QMAN_CENA_SIZE (CONFIG_SYS_QMAN_MEM_SIZE >> 1)
647#define CONFIG_SYS_QMAN_CINH_BASE (CONFIG_SYS_QMAN_MEM_BASE + \
648 CONFIG_SYS_QMAN_CENA_SIZE)
649#define CONFIG_SYS_QMAN_CINH_SIZE (CONFIG_SYS_QMAN_MEM_SIZE >> 1)
650#define CONFIG_SYS_QMAN_SWP_ISDR_REG 0xE08
651
652#define CONFIG_SYS_DPAA_FMAN
653#define CONFIG_SYS_DPAA_PME
654
655#define CONFIG_QE
656#define CONFIG_U_QE
657
658
659#if defined(CONFIG_SPIFLASH)
660
661
662
663
664#define CONFIG_SYS_QE_FW_IN_SPIFLASH
665#define CONFIG_SYS_FMAN_FW_ADDR 0x110000
666#elif defined(CONFIG_SDCARD)
667
668
669
670
671
672#define CONFIG_SYS_QE_FMAN_FW_IN_MMC
673#define CONFIG_SYS_FMAN_FW_ADDR (512 * 0x820)
674#elif defined(CONFIG_NAND)
675#define CONFIG_SYS_QE_FMAN_FW_IN_NAND
676#define CONFIG_SYS_FMAN_FW_ADDR (5 * CONFIG_SYS_NAND_BLOCK_SIZE)
677#else
678#define CONFIG_SYS_QE_FMAN_FW_IN_NOR
679#define CONFIG_SYS_FMAN_FW_ADDR 0xEFF00000
680#endif
681
682#if defined(CONFIG_SPIFLASH)
683#define CONFIG_SYS_QE_FW_ADDR 0x130000
684#elif defined(CONFIG_SDCARD)
685#define CONFIG_SYS_QE_FW_ADDR (512 * 0x920)
686#elif defined(CONFIG_NAND)
687#define CONFIG_SYS_QE_FW_ADDR (7 * CONFIG_SYS_NAND_BLOCK_SIZE)
688#else
689#define CONFIG_SYS_QE_FW_ADDR 0xEFF10000
690#endif
691
692#define CONFIG_SYS_QE_FMAN_FW_LENGTH 0x10000
693#define CONFIG_SYS_FDT_PAD (0x3000 + CONFIG_SYS_QE_FMAN_FW_LENGTH)
694#endif
695
696#ifdef CONFIG_SYS_DPAA_FMAN
697#define CONFIG_FMAN_ENET
698#define CONFIG_PHY_VITESSE
699#define CONFIG_PHY_REALTEK
700#endif
701
702#ifdef CONFIG_FMAN_ENET
703#if defined(CONFIG_TARGET_T1040RDB) || defined(CONFIG_TARGET_T1042RDB)
704#define CONFIG_SYS_SGMII1_PHY_ADDR 0x03
705#elif defined(CONFIG_TARGET_T1040D4RDB)
706#define CONFIG_SYS_SGMII1_PHY_ADDR 0x01
707#elif defined(CONFIG_TARGET_T1042D4RDB)
708#define CONFIG_SYS_SGMII1_PHY_ADDR 0x02
709#define CONFIG_SYS_SGMII2_PHY_ADDR 0x03
710#define CONFIG_SYS_SGMII3_PHY_ADDR 0x01
711#endif
712
713#if defined(CONFIG_TARGET_T1040D4RDB) || defined(CONFIG_TARGET_T1042D4RDB)
714#define CONFIG_SYS_RGMII1_PHY_ADDR 0x04
715#define CONFIG_SYS_RGMII2_PHY_ADDR 0x05
716#else
717#define CONFIG_SYS_RGMII1_PHY_ADDR 0x01
718#define CONFIG_SYS_RGMII2_PHY_ADDR 0x02
719#endif
720
721
722#if defined(CONFIG_TARGET_T1040RDB) || defined(CONFIG_TARGET_T1040D4RDB)
723#define CONFIG_VSC9953
724#ifdef CONFIG_TARGET_T1040RDB
725#define CONFIG_SYS_FM1_QSGMII11_PHY_ADDR 0x04
726#define CONFIG_SYS_FM1_QSGMII21_PHY_ADDR 0x08
727#else
728#define CONFIG_SYS_FM1_QSGMII11_PHY_ADDR 0x08
729#define CONFIG_SYS_FM1_QSGMII21_PHY_ADDR 0x0c
730#endif
731#endif
732
733#define CONFIG_ETHPRIME "FM1@DTSEC4"
734#endif
735
736
737
738
739#define CONFIG_LOADS_ECHO
740#define CONFIG_SYS_LOADS_BAUD_CHANGE
741
742
743
744
745#define CONFIG_SYS_LOAD_ADDR 0x2000000
746
747
748
749
750
751
752#define CONFIG_SYS_BOOTMAPSZ (64 << 20)
753#define CONFIG_SYS_BOOTM_LEN (64 << 20)
754
755#ifdef CONFIG_CMD_KGDB
756#define CONFIG_KGDB_BAUDRATE 230400
757#endif
758
759
760
761
762#ifdef CONFIG_MTD_NOR_FLASH
763#define CONFIG_FLASH_CFI_MTD
764#endif
765
766
767
768
769#define CONFIG_ROOTPATH "/opt/nfsroot"
770#define CONFIG_BOOTFILE "uImage"
771#define CONFIG_UBOOTPATH "u-boot.bin"
772
773
774#define CONFIG_LOADADDR 1000000
775
776#define __USB_PHY_TYPE utmi
777#define RAMDISKFILE "t104xrdb/ramdisk.uboot"
778
779#ifdef CONFIG_TARGET_T1040RDB
780#define FDTFILE "t1040rdb/t1040rdb.dtb"
781#elif defined(CONFIG_TARGET_T1042RDB_PI)
782#define FDTFILE "t1042rdb_pi/t1042rdb_pi.dtb"
783#elif defined(CONFIG_TARGET_T1042RDB)
784#define FDTFILE "t1042rdb/t1042rdb.dtb"
785#elif defined(CONFIG_TARGET_T1040D4RDB)
786#define FDTFILE "t1042rdb/t1040d4rdb.dtb"
787#elif defined(CONFIG_TARGET_T1042D4RDB)
788#define FDTFILE "t1042rdb/t1042d4rdb.dtb"
789#endif
790
791#ifdef CONFIG_FSL_DIU_FB
792#define DIU_ENVIRONMENT "video-mode=fslfb:1024x768-32@60,monitor=dvi"
793#else
794#define DIU_ENVIRONMENT
795#endif
796
797#define CONFIG_EXTRA_ENV_SETTINGS \
798 "hwconfig=fsl_ddr:bank_intlv=cs0_cs1;" \
799 "usb1:dr_mode=host,phy_type=" __stringify(__USB_PHY_TYPE) ";"\
800 "usb2:dr_mode=host,phy_type=" __stringify(__USB_PHY_TYPE) "\0"\
801 "netdev=eth0\0" \
802 "video-mode=" __stringify(DIU_ENVIRONMENT) "\0" \
803 "uboot=" __stringify(CONFIG_UBOOTPATH) "\0" \
804 "ubootaddr=" __stringify(CONFIG_SYS_TEXT_BASE) "\0" \
805 "tftpflash=tftpboot $loadaddr $uboot && " \
806 "protect off $ubootaddr +$filesize && " \
807 "erase $ubootaddr +$filesize && " \
808 "cp.b $loadaddr $ubootaddr $filesize && " \
809 "protect on $ubootaddr +$filesize && " \
810 "cmp.b $loadaddr $ubootaddr $filesize\0" \
811 "consoledev=ttyS0\0" \
812 "ramdiskaddr=2000000\0" \
813 "ramdiskfile=" __stringify(RAMDISKFILE) "\0" \
814 "fdtaddr=1e00000\0" \
815 "fdtfile=" __stringify(FDTFILE) "\0" \
816 "bdev=sda3\0"
817
818#define CONFIG_LINUX \
819 "setenv bootargs root=/dev/ram rw " \
820 "console=$consoledev,$baudrate $othbootargs;" \
821 "setenv ramdiskaddr 0x02000000;" \
822 "setenv fdtaddr 0x00c00000;" \
823 "setenv loadaddr 0x1000000;" \
824 "bootm $loadaddr $ramdiskaddr $fdtaddr"
825
826#define CONFIG_HDBOOT \
827 "setenv bootargs root=/dev/$bdev rw " \
828 "console=$consoledev,$baudrate $othbootargs;" \
829 "tftp $loadaddr $bootfile;" \
830 "tftp $fdtaddr $fdtfile;" \
831 "bootm $loadaddr - $fdtaddr"
832
833#define CONFIG_NFSBOOTCOMMAND \
834 "setenv bootargs root=/dev/nfs rw " \
835 "nfsroot=$serverip:$rootpath " \
836 "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \
837 "console=$consoledev,$baudrate $othbootargs;" \
838 "tftp $loadaddr $bootfile;" \
839 "tftp $fdtaddr $fdtfile;" \
840 "bootm $loadaddr - $fdtaddr"
841
842#define CONFIG_RAMBOOTCOMMAND \
843 "setenv bootargs root=/dev/ram rw " \
844 "console=$consoledev,$baudrate $othbootargs;" \
845 "tftp $ramdiskaddr $ramdiskfile;" \
846 "tftp $loadaddr $bootfile;" \
847 "tftp $fdtaddr $fdtfile;" \
848 "bootm $loadaddr $ramdiskaddr $fdtaddr"
849
850#define CONFIG_BOOTCOMMAND CONFIG_LINUX
851
852#include <asm/fsl_secure_boot.h>
853
854#endif
855
