LXR uboot/include/configs/mpc8308

   1/* SPDX-License-Identifier: GPL-2.0+ */
   2/*
   3 * Copyright (C) 2009-2010 Freescale Semiconductor, Inc.
   4 * Copyright (C) 2010 Ilya Yanok, Emcraft Systems, yanok@emcraft.com
   5 *
   6 */
   7
   8#ifndef __CONFIG_H
   9#define __CONFIG_H
  10
  11/*
  12 * High Level Configuration Options
  13 */
  14#define CONFIG_E300             1 /* E300 family */
  15#define CONFIG_MPC830x          1 /* MPC830x family */
  16#define CONFIG_MPC8308          1 /* MPC8308 CPU specific */
  17
  18/*
  19 * On-board devices
  20 *
  21 * TSECs
  22 */
  23#define CONFIG_TSEC1
  24#define CONFIG_TSEC2
  25
  26/*
  27 * System Clock Setup
  28 */
  29#define CONFIG_83XX_CLKIN       33333333 /* in Hz */
  30#define CONFIG_SYS_CLK_FREQ     CONFIG_83XX_CLKIN
  31
  32/*
  33 * Hardware Reset Configuration Word
  34 * if CLKIN is 66.66MHz, then
  35 * CSB = 133MHz, DDRC = 266MHz, LBC = 133MHz
  36 * We choose the A type silicon as default, so the core is 400Mhz.
  37 */
  38#define CONFIG_SYS_HRCW_LOW (\
  39        HRCWL_LCL_BUS_TO_SCB_CLK_1X1 |\
  40        HRCWL_DDR_TO_SCB_CLK_2X1 |\
  41        HRCWL_SVCOD_DIV_2 |\
  42        HRCWL_CSB_TO_CLKIN_4X1 |\
  43        HRCWL_CORE_TO_CSB_3X1)
  44/*
  45 * There are neither HRCWH_PCI_HOST nor HRCWH_PCI1_ARBITER_ENABLE bits
  46 * in 8308's HRCWH according to the manual, but original Freescale's
  47 * code has them and I've expirienced some problems using the board
  48 * with BDI3000 attached when I've tried to set these bits to zero
  49 * (UART doesn't work after the 'reset run' command).
  50 */
  51#define CONFIG_SYS_HRCW_HIGH (\
  52        HRCWH_PCI_HOST |\
  53        HRCWH_PCI1_ARBITER_ENABLE |\
  54        HRCWH_CORE_ENABLE |\
  55        HRCWH_FROM_0X00000100 |\
  56        HRCWH_BOOTSEQ_DISABLE |\
  57        HRCWH_SW_WATCHDOG_DISABLE |\
  58        HRCWH_ROM_LOC_LOCAL_16BIT |\
  59        HRCWH_RL_EXT_LEGACY |\
  60        HRCWH_TSEC1M_IN_MII |\
  61        HRCWH_TSEC2M_IN_MII |\
  62        HRCWH_BIG_ENDIAN)
  63
  64/*
  65 * System IO Config
  66 */
  67#define CONFIG_SYS_SICRH (\
  68        SICRH_ESDHC_A_GPIO |\
  69        SICRH_ESDHC_B_GPIO |\
  70        SICRH_ESDHC_C_GTM |\
  71        SICRH_GPIO_A_TSEC2 |\
  72        SICRH_GPIO_B_TSEC2_TX_CLK |\
  73        SICRH_IEEE1588_A_GPIO |\
  74        SICRH_USB |\
  75        SICRH_GTM_GPIO |\
  76        SICRH_IEEE1588_B_GPIO |\
  77        SICRH_ETSEC2_CRS |\
  78        SICRH_GPIOSEL_1 |\
  79        SICRH_TMROBI_V3P3 |\
  80        SICRH_TSOBI1_V3P3 |\
  81        SICRH_TSOBI2_V3P3)      /* 0xf577d100 */
  82#define CONFIG_SYS_SICRL (\
  83        SICRL_SPI_PF0 |\
  84        SICRL_UART_PF0 |\
  85        SICRL_IRQ_PF0 |\
  86        SICRL_I2C2_PF0 |\
  87        SICRL_ETSEC1_TX_CLK)    /* 0x00000000 */
  88
  89#define CONFIG_SYS_GPIO1_PRELIM
  90/* GPIO Default input/output settings */
  91#define CONFIG_SYS_GPIO1_DIR        0x7AAF8C00
  92/*
  93 * Default GPIO values:
  94 * LED#1 enabled; WLAN enabled; Both COM LED on (orange)
  95 */
  96#define CONFIG_SYS_GPIO1_DAT        0x08008C00
  97
  98/*
  99 * IMMR new address
 100 */
 101#define CONFIG_SYS_IMMR         0xE0000000
 102
 103/*
 104 * SERDES
 105 */
 106#define CONFIG_FSL_SERDES
 107#define CONFIG_FSL_SERDES1      0xe3000
 108
 109/*
 110 * Arbiter Setup
 111 */
 112#define CONFIG_SYS_ACR_PIPE_DEP 3 /* Arbiter pipeline depth is 4 */
 113#define CONFIG_SYS_ACR_RPTCNT   3 /* Arbiter repeat count is 4 */
 114#define CONFIG_SYS_SPCR_TSECEP  3 /* eTSEC emergency priority is highest */
 115
 116/*
 117 * DDR Setup
 118 */
 119#define CONFIG_SYS_DDR_BASE             0x00000000 /* DDR is system memory */
 120#define CONFIG_SYS_SDRAM_BASE           CONFIG_SYS_DDR_BASE
 121#define CONFIG_SYS_DDR_SDRAM_BASE       CONFIG_SYS_DDR_BASE
 122#define CONFIG_SYS_DDR_SDRAM_CLK_CNTL   DDR_SDRAM_CLK_CNTL_CLK_ADJUST_05
 123#define CONFIG_SYS_DDRCDR_VALUE (DDRCDR_EN \
 124                                | DDRCDR_PZ_LOZ \
 125                                | DDRCDR_NZ_LOZ \
 126                                | DDRCDR_ODT \
 127                                | DDRCDR_Q_DRN)
 128                                /* 0x7b880001 */
 129/*
 130 * Manually set up DDR parameters
 131 * consist of two chips HY5PS12621BFP-C4 from HYNIX
 132 */
 133
 134#define CONFIG_SYS_DDR_SIZE             128 /* MB */
 135
 136#define CONFIG_SYS_DDR_CS0_BNDS 0x00000007
 137#define CONFIG_SYS_DDR_CS0_CONFIG       (CSCONFIG_EN \
 138                                        | CSCONFIG_ODT_RD_NEVER \
 139                                        | CSCONFIG_ODT_WR_ONLY_CURRENT \
 140                                        | CSCONFIG_ROW_BIT_13 \
 141                                        | CSCONFIG_COL_BIT_10)
 142                                        /* 0x80010102 */
 143#define CONFIG_SYS_DDR_TIMING_3 0x00000000
 144#define CONFIG_SYS_DDR_TIMING_0 ((0 << TIMING_CFG0_RWT_SHIFT) \
 145                                | (0 << TIMING_CFG0_WRT_SHIFT) \
 146                                | (0 << TIMING_CFG0_RRT_SHIFT) \
 147                                | (0 << TIMING_CFG0_WWT_SHIFT) \
 148                                | (2 << TIMING_CFG0_ACT_PD_EXIT_SHIFT) \
 149                                | (2 << TIMING_CFG0_PRE_PD_EXIT_SHIFT) \
 150                                | (8 << TIMING_CFG0_ODT_PD_EXIT_SHIFT) \
 151                                | (2 << TIMING_CFG0_MRS_CYC_SHIFT))
 152                                /* 0x00220802 */
 153#define CONFIG_SYS_DDR_TIMING_1 ((2 << TIMING_CFG1_PRETOACT_SHIFT) \
 154                                | (7 << TIMING_CFG1_ACTTOPRE_SHIFT) \
 155                                | (2 << TIMING_CFG1_ACTTORW_SHIFT) \
 156                                | (5 << TIMING_CFG1_CASLAT_SHIFT) \
 157                                | (6 << TIMING_CFG1_REFREC_SHIFT) \
 158                                | (2 << TIMING_CFG1_WRREC_SHIFT) \
 159                                | (2 << TIMING_CFG1_ACTTOACT_SHIFT) \
 160                                | (2 << TIMING_CFG1_WRTORD_SHIFT))
 161                                /* 0x27256222 */
 162#define CONFIG_SYS_DDR_TIMING_2 ((1 << TIMING_CFG2_ADD_LAT_SHIFT) \
 163                                | (4 << TIMING_CFG2_CPO_SHIFT) \
 164                                | (2 << TIMING_CFG2_WR_LAT_DELAY_SHIFT) \
 165                                | (2 << TIMING_CFG2_RD_TO_PRE_SHIFT) \
 166                                | (2 << TIMING_CFG2_WR_DATA_DELAY_SHIFT) \
 167                                | (3 << TIMING_CFG2_CKE_PLS_SHIFT) \
 168                                | (5 << TIMING_CFG2_FOUR_ACT_SHIFT))
 169                                /* 0x121048c5 */
 170#define CONFIG_SYS_DDR_INTERVAL ((0x0360 << SDRAM_INTERVAL_REFINT_SHIFT) \
 171                                | (0x0100 << SDRAM_INTERVAL_BSTOPRE_SHIFT))
 172                                /* 0x03600100 */
 173#define CONFIG_SYS_DDR_SDRAM_CFG        (SDRAM_CFG_SREN \
 174                                | SDRAM_CFG_SDRAM_TYPE_DDR2 \
 175                                | SDRAM_CFG_DBW_32)
 176                                /* 0x43080000 */
 177
 178#define CONFIG_SYS_DDR_SDRAM_CFG2       0x00401000 /* 1 posted refresh */
 179#define CONFIG_SYS_DDR_MODE             ((0x0448 << SDRAM_MODE_ESD_SHIFT) \
 180                                | (0x0232 << SDRAM_MODE_SD_SHIFT))
 181                                /* ODT 150ohm CL=3, AL=1 on SDRAM */
 182#define CONFIG_SYS_DDR_MODE2            0x00000000
 183
 184/*
 185 * Memory test
 186 */
 187#define CONFIG_SYS_MEMTEST_START        0x00001000 /* memtest region */
 188#define CONFIG_SYS_MEMTEST_END          0x07f00000
 189
 190/*
 191 * The reserved memory
 192 */
 193#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */
 194
 195#define CONFIG_SYS_MONITOR_LEN  (384 * 1024) /* Reserve 384 kB for Mon */
 196#define CONFIG_SYS_MALLOC_LEN   (512 * 1024) /* Reserved for malloc */
 197
 198/*
 199 * Initial RAM Base Address Setup
 200 */
 201#define CONFIG_SYS_INIT_RAM_LOCK        1
 202#define CONFIG_SYS_INIT_RAM_ADDR        0xE6000000 /* Initial RAM address */
 203#define CONFIG_SYS_INIT_RAM_SIZE        0x1000 /* Size of used area in RAM */
 204#define CONFIG_SYS_GBL_DATA_OFFSET      \
 205        (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
 206
 207/*
 208 * Local Bus Configuration & Clock Setup
 209 */
 210#define CONFIG_SYS_LCRR_DBYP            LCRR_DBYP
 211#define CONFIG_SYS_LCRR_CLKDIV          LCRR_CLKDIV_2
 212#define CONFIG_SYS_LBC_LBCR             0x00040000
 213
 214/*
 215 * FLASH on the Local Bus
 216 */
 217#define CONFIG_SYS_FLASH_CFI            /* use the Common Flash Interface */
 218#define CONFIG_FLASH_CFI_DRIVER         /* use the CFI driver */
 219#define CONFIG_SYS_FLASH_CFI_WIDTH      FLASH_CFI_16BIT
 220
 221#define CONFIG_SYS_FLASH_BASE           0xFC000000 /* FLASH base address */
 222#define CONFIG_SYS_FLASH_SIZE           64 /* FLASH size is 64M */
 223#define CONFIG_SYS_FLASH_PROTECTION     1 /* Use h/w Flash protection. */
 224
 225/* Window base at flash base */
 226#define CONFIG_SYS_LBLAWBAR0_PRELIM     CONFIG_SYS_FLASH_BASE
 227#define CONFIG_SYS_LBLAWAR0_PRELIM      (LBLAWAR_EN | LBLAWAR_64MB)
 228
 229#define CONFIG_SYS_BR0_PRELIM   (CONFIG_SYS_FLASH_BASE \
 230                                | BR_PS_16      /* 16 bit port */ \
 231                                | BR_MS_GPCM    /* MSEL = GPCM */ \
 232                                | BR_V)         /* valid */
 233#define CONFIG_SYS_OR0_PRELIM   (MEG_TO_AM(CONFIG_SYS_FLASH_SIZE) \
 234                                | OR_UPM_XAM \
 235                                | OR_GPCM_CSNT \
 236                                | OR_GPCM_ACS_DIV2 \
 237                                | OR_GPCM_XACS \
 238                                | OR_GPCM_SCY_4 \
 239                                | OR_GPCM_TRLX_SET \
 240                                | OR_GPCM_EHTR_SET)
 241
 242#define CONFIG_SYS_MAX_FLASH_BANKS      1 /* number of banks */
 243#define CONFIG_SYS_MAX_FLASH_SECT       512
 244
 245/* Flash Erase Timeout (ms) */
 246#define CONFIG_SYS_FLASH_ERASE_TOUT     (1000 * 1024)
 247/* Flash Write Timeout (ms) */
 248#define CONFIG_SYS_FLASH_WRITE_TOUT     (500 * 1024)
 249
 250/*
 251 * SJA1000 CAN controller on Local Bus
 252 */
 253#define CONFIG_SYS_SJA1000_BASE 0xFBFF0000
 254#define CONFIG_SYS_BR1_PRELIM   (CONFIG_SYS_SJA1000_BASE \
 255                                | BR_PS_8       /* 8 bit port size */ \
 256                                | BR_MS_GPCM    /* MSEL = GPCM */ \
 257                                | BR_V)         /* valid */
 258#define CONFIG_SYS_OR1_PRELIM   (OR_AM_32KB \
 259                                | OR_GPCM_SCY_5 \
 260                                | OR_GPCM_EHTR_SET)
 261                                /* 0xFFFF8052 */
 262
 263#define CONFIG_SYS_LBLAWBAR1_PRELIM     CONFIG_SYS_SJA1000_BASE
 264#define CONFIG_SYS_LBLAWAR1_PRELIM      (LBLAWAR_EN | LBLAWAR_32KB)
 265
 266/*
 267 * CPLD on Local Bus
 268 */
 269#define CONFIG_SYS_CPLD_BASE    0xFBFF8000
 270#define CONFIG_SYS_BR2_PRELIM   (CONFIG_SYS_CPLD_BASE \
 271                                | BR_PS_8       /* 8 bit port */ \
 272                                | BR_MS_GPCM    /* MSEL = GPCM */ \
 273                                | BR_V)         /* valid */
 274#define CONFIG_SYS_OR2_PRELIM   (OR_AM_32KB \
 275                                | OR_GPCM_SCY_4 \
 276                                | OR_GPCM_EHTR_SET)
 277                                /* 0xFFFF8042 */
 278
 279#define CONFIG_SYS_LBLAWBAR2_PRELIM     CONFIG_SYS_CPLD_BASE
 280#define CONFIG_SYS_LBLAWAR2_PRELIM      (LBLAWAR_EN | LBLAWAR_32KB)
 281
 282/*
 283 * Serial Port
 284 */
 285#undef CONFIG_SERIAL_SOFTWARE_FIFO
 286#define CONFIG_SYS_NS16550_SERIAL
 287#define CONFIG_SYS_NS16550_REG_SIZE     1
 288#define CONFIG_SYS_NS16550_CLK          get_bus_freq(0)
 289
 290#define CONFIG_SYS_BAUDRATE_TABLE  \
 291        {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200}
 292
 293#define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_IMMR + 0x4500)
 294#define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_IMMR + 0x4600)
 295
 296/* I2C */
 297#define CONFIG_SYS_I2C
 298#define CONFIG_SYS_I2C_FSL
 299#define CONFIG_SYS_FSL_I2C_SPEED        400000
 300#define CONFIG_SYS_FSL_I2C_SLAVE        0x7F
 301#define CONFIG_SYS_FSL_I2C2_SPEED       400000
 302#define CONFIG_SYS_FSL_I2C2_SLAVE       0x7F
 303#define CONFIG_SYS_FSL_I2C_OFFSET       0x3000
 304#define CONFIG_SYS_FSL_I2C2_OFFSET      0x3100
 305
 306/*
 307 * General PCI
 308 * Addresses are mapped 1-1.
 309 */
 310#define CONFIG_SYS_PCIE1_BASE           0xA0000000
 311#define CONFIG_SYS_PCIE1_MEM_BASE       0xA0000000
 312#define CONFIG_SYS_PCIE1_MEM_PHYS       0xA0000000
 313#define CONFIG_SYS_PCIE1_MEM_SIZE       0x10000000
 314#define CONFIG_SYS_PCIE1_CFG_BASE       0xB0000000
 315#define CONFIG_SYS_PCIE1_CFG_SIZE       0x01000000
 316#define CONFIG_SYS_PCIE1_IO_BASE        0x00000000
 317#define CONFIG_SYS_PCIE1_IO_PHYS        0xB1000000
 318#define CONFIG_SYS_PCIE1_IO_SIZE        0x00800000
 319
 320/* enable PCIE clock */
 321#define CONFIG_SYS_SCCR_PCIEXP1CM       1
 322
 323#define CONFIG_PCI_INDIRECT_BRIDGE
 324#define CONFIG_PCIE
 325
 326#define CONFIG_SYS_PCI_SUBSYS_VENDORID 0x1957   /* Freescale */
 327#define CONFIG_83XX_GENERIC_PCIE_REGISTER_HOSES 1
 328
 329/*
 330 * TSEC
 331 */
 332#define CONFIG_SYS_TSEC1_OFFSET 0x24000
 333#define CONFIG_SYS_TSEC1        (CONFIG_SYS_IMMR+CONFIG_SYS_TSEC1_OFFSET)
 334#define CONFIG_SYS_TSEC2_OFFSET 0x25000
 335#define CONFIG_SYS_TSEC2        (CONFIG_SYS_IMMR+CONFIG_SYS_TSEC2_OFFSET)
 336
 337/*
 338 * TSEC ethernet configuration
 339 */
 340#define CONFIG_TSEC1_NAME       "eTSEC0"
 341#define CONFIG_TSEC2_NAME       "eTSEC1"
 342#define TSEC1_PHY_ADDR          1
 343#define TSEC2_PHY_ADDR          2
 344#define TSEC1_PHYIDX            0
 345#define TSEC2_PHYIDX            0
 346#define TSEC1_FLAGS             0
 347#define TSEC2_FLAGS             0
 348
 349/* Options are: eTSEC[0-1] */
 350#define CONFIG_ETHPRIME         "eTSEC0"
 351
 352/*
 353 * Environment
 354 */
 355#define CONFIG_ENV_ADDR         (CONFIG_SYS_MONITOR_BASE + \
 356                                 CONFIG_SYS_MONITOR_LEN)
 357#define CONFIG_ENV_SECT_SIZE    0x20000 /* 128K(one sector) for env */
 358#define CONFIG_ENV_SIZE         0x2000
 359#define CONFIG_ENV_ADDR_REDUND  (CONFIG_ENV_ADDR + CONFIG_ENV_SECT_SIZE)
 360#define CONFIG_ENV_SIZE_REDUND  CONFIG_ENV_SIZE
 361
 362#define CONFIG_LOADS_ECHO       1       /* echo on for serial download */
 363#define CONFIG_SYS_LOADS_BAUD_CHANGE    1       /* allow baudrate change */
 364
 365/*
 366 * BOOTP options
 367 */
 368#define CONFIG_BOOTP_BOOTFILESIZE
 369
 370/*
 371 * Command line configuration.
 372 */
 373
 374/*
 375 * Miscellaneous configurable options
 376 */
 377#define CONFIG_SYS_LOAD_ADDR            0x2000000 /* default load address */
 378
 379#define CONFIG_SYS_CBSIZE       1024 /* Console I/O Buffer Size */
 380
 381/* Boot Argument Buffer Size */
 382#define CONFIG_SYS_BARGSIZE     CONFIG_SYS_CBSIZE
 383
 384/*
 385 * For booting Linux, the board info and command line data
 386 * have to be in the first 8 MB of memory, since this is
 387 * the maximum mapped by the Linux kernel during initialization.
 388 */
 389#define CONFIG_SYS_BOOTMAPSZ    (256 << 20) /* Initial Memory map for Linux */
 390
 391/*
 392 * Core HID Setup
 393 */
 394#define CONFIG_SYS_HID0_INIT    0x000000000
 395#define CONFIG_SYS_HID0_FINAL   (HID0_ENABLE_MACHINE_CHECK | \
 396                                 HID0_ENABLE_INSTRUCTION_CACHE | \
 397                                 HID0_ENABLE_DYNAMIC_POWER_MANAGMENT)
 398#define CONFIG_SYS_HID2         HID2_HBE
 399
 400/*
 401 * MMU Setup
 402 */
 403
 404/* DDR: cache cacheable */
 405#define CONFIG_SYS_IBAT0L       (CONFIG_SYS_SDRAM_BASE | BATL_PP_RW | \
 406                                        BATL_MEMCOHERENCE)
 407#define CONFIG_SYS_IBAT0U       (CONFIG_SYS_SDRAM_BASE | BATU_BL_128M | \
 408                                        BATU_VS | BATU_VP)
 409#define CONFIG_SYS_DBAT0L       CONFIG_SYS_IBAT0L
 410#define CONFIG_SYS_DBAT0U       CONFIG_SYS_IBAT0U
 411
 412/* IMMRBAR, PCI IO and NAND: cache-inhibit and guarded */
 413#define CONFIG_SYS_IBAT1L       (CONFIG_SYS_IMMR | BATL_PP_RW | \
 414                        BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE)
 415#define CONFIG_SYS_IBAT1U       (CONFIG_SYS_IMMR | BATU_BL_8M | BATU_VS | \
 416                                        BATU_VP)
 417#define CONFIG_SYS_DBAT1L       CONFIG_SYS_IBAT1L
 418#define CONFIG_SYS_DBAT1U       CONFIG_SYS_IBAT1U
 419
 420/* FLASH: icache cacheable, but dcache-inhibit and guarded */
 421#define CONFIG_SYS_IBAT2L       (CONFIG_SYS_FLASH_BASE | BATL_PP_RW | \
 422                                        BATL_MEMCOHERENCE)
 423#define CONFIG_SYS_IBAT2U       (CONFIG_SYS_FLASH_BASE | BATU_BL_8M | \
 424                                        BATU_VS | BATU_VP)
 425#define CONFIG_SYS_DBAT2L       (CONFIG_SYS_FLASH_BASE | BATL_PP_RW | \
 426                                        BATL_CACHEINHIBIT | \
 427                                        BATL_GUARDEDSTORAGE)
 428#define CONFIG_SYS_DBAT2U       CONFIG_SYS_IBAT2U
 429
 430/* Stack in dcache: cacheable, no memory coherence */
 431#define CONFIG_SYS_IBAT3L       (CONFIG_SYS_INIT_RAM_ADDR | BATL_PP_RW)
 432#define CONFIG_SYS_IBAT3U       (CONFIG_SYS_INIT_RAM_ADDR | BATU_BL_128K | \
 433                                        BATU_VS | BATU_VP)
 434#define CONFIG_SYS_DBAT3L       CONFIG_SYS_IBAT3L
 435#define CONFIG_SYS_DBAT3U       CONFIG_SYS_IBAT3U
 436
 437/*
 438 * Environment Configuration
 439 */
 440
 441#define CONFIG_ENV_OVERWRITE
 442
 443#if defined(CONFIG_TSEC_ENET)
 444#define CONFIG_HAS_ETH0
 445#define CONFIG_HAS_ETH1
 446#endif
 447
 448#define CONFIG_LOADADDR 800000  /* default location for tftp and bootm */
 449
 450
 451#define CONFIG_EXTRA_ENV_SETTINGS                                       \
 452        "netdev=eth0\0"                                                 \
 453        "consoledev=ttyS0\0"                                            \
 454        "nfsargs=setenv bootargs root=/dev/nfs rw "                     \
 455                "nfsroot=${serverip}:${rootpath}\0"                     \
 456        "ramargs=setenv bootargs root=/dev/ram rw\0"                    \
 457        "addip=setenv bootargs ${bootargs} "                            \
 458                "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}"      \
 459                ":${hostname}:${netdev}:off panic=1\0"                  \
 460        "addtty=setenv bootargs ${bootargs}"                            \
 461                " console=${consoledev},${baudrate}\0"                  \
 462        "addmtd=setenv bootargs ${bootargs} ${mtdparts}\0"              \
 463        "addmisc=setenv bootargs ${bootargs}\0"                         \
 464        "kernel_addr=FC0A0000\0"                                        \
 465        "fdt_addr=FC2A0000\0"                                           \
 466        "ramdisk_addr=FC2C0000\0"                                       \
 467        "u-boot=mpc8308_p1m/u-boot.bin\0"                               \
 468        "kernel_addr_r=1000000\0"                                       \
 469        "fdt_addr_r=C00000\0"                                           \
 470        "hostname=mpc8308_p1m\0"                                        \
 471        "bootfile=mpc8308_p1m/uImage\0"                                 \
 472        "fdtfile=mpc8308_p1m/mpc8308_p1m.dtb\0"                         \
 473        "rootpath=/opt/eldk-4.2/ppc_6xx\0"                              \
 474        "flash_self=run ramargs addip addtty addmtd addmisc;"           \
 475                "bootm ${kernel_addr} ${ramdisk_addr} ${fdt_addr}\0"    \
 476        "flash_nfs=run nfsargs addip addtty addmtd addmisc;"            \
 477                "bootm ${kernel_addr} - ${fdt_addr}\0"                  \
 478        "net_nfs=tftp ${kernel_addr_r} ${bootfile};"                    \
 479                "tftp ${fdt_addr_r} ${fdtfile};"                        \
 480                "run nfsargs addip addtty addmtd addmisc;"              \
 481                "bootm ${kernel_addr_r} - ${fdt_addr_r}\0"              \
 482        "bootcmd=run flash_self\0"                                      \
 483        "load=tftp ${loadaddr} ${u-boot}\0"                             \
 484        "update=protect off " __stringify(CONFIG_SYS_MONITOR_BASE)      \
 485                " +${filesize};era " __stringify(CONFIG_SYS_MONITOR_BASE)\
 486                " +${filesize};cp.b ${fileaddr} "                       \
 487                __stringify(CONFIG_SYS_MONITOR_BASE) " ${filesize}\0"   \
 488        "upd=run load update\0"                                         \
 489
 490#endif  /* __CONFIG_H */
 491