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7#ifndef _TEGRA_CLK_RST_H_
8#define _TEGRA_CLK_RST_H_
9
10
11struct clk_pll {
12 uint pll_base;
13
14 uint pll_out[2];
15 uint pll_misc;
16};
17
18
19struct clk_pll_simple {
20 uint pll_base;
21 uint pll_misc;
22};
23
24struct clk_pllm {
25 uint pllm_base;
26 uint pllm_out;
27 uint pllm_misc1;
28 uint pllm_misc2;
29};
30
31
32struct clk_set_clr {
33 uint set;
34 uint clr;
35};
36
37
38
39
40
41
42enum {
43 TEGRA_CLK_PLLS = 6,
44 TEGRA_CLK_SIMPLE_PLLS = 3,
45 TEGRA_CLK_REGS = 3,
46 TEGRA_CLK_SOURCES = 64,
47 TEGRA_CLK_REGS_VW = 2,
48 TEGRA_CLK_SOURCES_VW = 32,
49 TEGRA_CLK_SOURCES_X = 32,
50 TEGRA_CLK_SOURCES_Y = 18,
51};
52
53
54struct clk_rst_ctlr {
55 uint crc_rst_src;
56 uint crc_rst_dev[TEGRA_CLK_REGS];
57 uint crc_clk_out_enb[TEGRA_CLK_REGS];
58 uint crc_reserved0;
59 uint crc_cclk_brst_pol;
60 uint crc_super_cclk_div;
61 uint crc_sclk_brst_pol;
62 uint crc_super_sclk_div;
63 uint crc_clk_sys_rate;
64 uint crc_prog_dly_clk;
65 uint crc_aud_sync_clk_rate;
66 uint crc_reserved1;
67 uint crc_cop_clk_skip_plcy;
68 uint crc_clk_mask_arm;
69 uint crc_misc_clk_enb;
70 uint crc_clk_cpu_cmplx;
71 uint crc_osc_ctrl;
72 uint crc_pll_lfsr;
73 uint crc_osc_freq_det;
74 uint crc_osc_freq_det_stat;
75 uint crc_reserved2[8];
76
77 struct clk_pll crc_pll[TEGRA_CLK_PLLS];
78
79
80 struct clk_pll_simple crc_pll_simple[TEGRA_CLK_SIMPLE_PLLS];
81
82 uint crc_reserved10;
83 uint crc_reserved11;
84
85 uint crc_clk_src[TEGRA_CLK_SOURCES];
86
87 uint crc_reserved20[32];
88
89 uint crc_clk_out_enb_x;
90 uint crc_clk_enb_x_set;
91 uint crc_clk_enb_x_clr;
92
93 uint crc_rst_devices_x;
94 uint crc_rst_dev_x_set;
95 uint crc_rst_dev_x_clr;
96
97 uint crc_clk_out_enb_y;
98 uint crc_clk_enb_y_set;
99 uint crc_clk_enb_y_clr;
100
101 uint crc_rst_devices_y;
102 uint crc_rst_dev_y_set;
103 uint crc_rst_dev_y_clr;
104
105 uint crc_reserved21[17];
106
107 uint crc_dfll_base;
108
109 uint crc_reserved22[2];
110
111
112 struct clk_set_clr crc_rst_dev_ex[TEGRA_CLK_REGS];
113
114 uint crc_reserved30[2];
115
116
117 struct clk_set_clr crc_clk_enb_ex[TEGRA_CLK_REGS];
118
119 uint crc_reserved31[2];
120
121 uint crc_cpu_cmplx_set;
122 uint crc_cpu_cmplx_clr;
123
124
125 uint crc_clk_cpu_cmplx_set;
126 uint crc_clk_cpu_cmplx_clr;
127
128 uint crc_reserved32[2];
129
130 uint crc_rst_dev_vw[TEGRA_CLK_REGS_VW];
131 uint crc_clk_out_enb_vw[TEGRA_CLK_REGS_VW];
132 uint crc_cclkg_brst_pol;
133 uint crc_super_cclkg_div;
134 uint crc_cclklp_brst_pol;
135 uint crc_super_cclkp_div;
136 uint crc_clk_cpug_cmplx;
137 uint crc_clk_cpulp_cmplx;
138 uint crc_cpu_softrst_ctrl;
139 uint crc_cpu_softrst_ctrl1;
140 uint crc_cpu_softrst_ctrl2;
141 uint crc_reserved33[9];
142 uint crc_clk_src_vw[TEGRA_CLK_SOURCES_VW];
143
144 struct clk_set_clr crc_rst_dev_ex_vw[TEGRA_CLK_REGS_VW];
145
146 struct clk_set_clr crc_clk_enb_ex_vw[TEGRA_CLK_REGS_VW];
147
148 uint crc_rst_cpug_cmplx_set;
149 uint crc_rst_cpug_cmplx_clr;
150 uint crc_rst_cpulp_cmplx_set;
151 uint crc_rst_cpulp_cmplx_clr;
152 uint crc_clk_cpug_cmplx_set;
153 uint crc_clk_cpug_cmplx_clr;
154 uint crc_clk_cpulp_cmplx_set;
155 uint crc_clk_cpulp_cmplx_clr;
156 uint crc_cpu_cmplx_status;
157 uint crc_reserved40[1];
158 uint crc_intstatus;
159 uint crc_intmask;
160 uint crc_utmip_pll_cfg0;
161 uint crc_utmip_pll_cfg1;
162 uint crc_utmip_pll_cfg2;
163
164 uint crc_plle_aux;
165 uint crc_sata_pll_cfg0;
166 uint crc_sata_pll_cfg1;
167 uint crc_pcie_pll_cfg0;
168
169 uint crc_prog_audio_dly_clk;
170 uint crc_audio_sync_clk_i2s0;
171 uint crc_audio_sync_clk_i2s1;
172 uint crc_audio_sync_clk_i2s2;
173 uint crc_audio_sync_clk_i2s3;
174 uint crc_audio_sync_clk_i2s4;
175 uint crc_audio_sync_clk_spdif;
176
177 uint crc_plld2_base;
178 uint crc_plld2_misc;
179 uint crc_utmip_pll_cfg3;
180 uint crc_pllrefe_base;
181 uint crc_pllrefe_misc;
182 uint crs_reserved_50[7];
183 uint crc_pllc2_base;
184 uint crc_pllc2_misc0;
185 uint crc_pllc2_misc1;
186 uint crc_pllc2_misc2;
187 uint crc_pllc2_misc3;
188 uint crc_pllc3_base;
189 uint crc_pllc3_misc0;
190 uint crc_pllc3_misc1;
191 uint crc_pllc3_misc2;
192 uint crc_pllc3_misc3;
193 uint crc_pllx_misc1;
194 uint crc_pllx_misc2;
195 uint crc_pllx_misc3;
196 uint crc_xusbio_pll_cfg0;
197 uint crc_xusbio_pll_cfg1;
198 uint crc_plle_aux1;
199 uint crc_pllp_reshift;
200 uint crc_utmipll_hw_pwrdn_cfg0;
201 uint crc_pllu_hw_pwrdn_cfg0;
202 uint crc_xusb_pll_cfg0;
203 uint crc_reserved51[1];
204 uint crc_clk_cpu_misc;
205 uint crc_clk_cpug_misc;
206 uint crc_clk_cpulp_misc;
207 uint crc_pllx_hw_ctrl_cfg;
208 uint crc_pllx_sw_ramp_cfg;
209 uint crc_pllx_hw_ctrl_status;
210 uint crc_reserved52[1];
211 uint crc_super_gr3d_clk_div;
212 uint crc_spare_reg0;
213 u32 _rsv32[4];
214 u32 crc_plld2_ss_cfg;
215 u32 _rsv32_1[7];
216 struct clk_pll_simple plldp;
217 u32 crc_plldp_ss_cfg;
218
219
220 uint _rsrv32_2[25];
221 uint crc_clk_src_x[TEGRA_CLK_SOURCES_X];
222
223
224 uint crc_reserved61[5];
225
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227
228
229 uint crc_clk_src_y[TEGRA_CLK_SOURCES_Y];
230};
231
232
233#define CPU3_CLK_STP_SHIFT 11
234#define CPU2_CLK_STP_SHIFT 10
235#define CPU1_CLK_STP_SHIFT 9
236#define CPU0_CLK_STP_SHIFT 8
237#define CPU0_CLK_STP_MASK (1U << CPU0_CLK_STP_SHIFT)
238
239
240#define PLL_BYPASS_SHIFT 31
241#define PLL_BYPASS_MASK (1U << PLL_BYPASS_SHIFT)
242
243#define PLL_ENABLE_SHIFT 30
244#define PLL_ENABLE_MASK (1U << PLL_ENABLE_SHIFT)
245
246#define PLL_BASE_OVRRIDE_MASK (1U << 28)
247
248#define PLL_LOCK_SHIFT 27
249#define PLL_LOCK_MASK (1U << PLL_LOCK_SHIFT)
250
251
252#define PLL_OUT_RSTN (1 << 0)
253#define PLL_OUT_CLKEN (1 << 1)
254#define PLL_OUT_OVRRIDE (1 << 2)
255
256#define PLL_OUT_RATIO_SHIFT 8
257#define PLL_OUT_RATIO_MASK (0xffU << PLL_OUT_RATIO_SHIFT)
258
259
260#define PLL_DCCON_SHIFT 20
261#define PLL_DCCON_MASK (1U << PLL_DCCON_SHIFT)
262
263#define PLLP_OUT1_OVR (1 << 2)
264#define PLLP_OUT2_OVR (1 << 18)
265#define PLLP_OUT3_OVR (1 << 2)
266#define PLLP_OUT4_OVR (1 << 18)
267#define PLLP_OUT1_RATIO 8
268#define PLLP_OUT2_RATIO 24
269#define PLLP_OUT3_RATIO 8
270#define PLLP_OUT4_RATIO 24
271
272enum {
273 IN_408_OUT_204_DIVISOR = 2,
274 IN_408_OUT_102_DIVISOR = 6,
275 IN_408_OUT_48_DIVISOR = 15,
276 IN_408_OUT_9_6_DIVISOR = 83,
277};
278
279#define PLLP_OUT1_RSTN_DIS (1 << 0)
280#define PLLP_OUT1_RSTN_EN (0 << 0)
281#define PLLP_OUT1_CLKEN (1 << 1)
282#define PLLP_OUT2_RSTN_DIS (1 << 16)
283#define PLLP_OUT2_RSTN_EN (0 << 16)
284#define PLLP_OUT2_CLKEN (1 << 17)
285
286#define PLLP_OUT3_RSTN_DIS (1 << 0)
287#define PLLP_OUT3_RSTN_EN (0 << 0)
288#define PLLP_OUT3_CLKEN (1 << 1)
289#define PLLP_OUT4_RSTN_DIS (1 << 16)
290#define PLLP_OUT4_RSTN_EN (0 << 16)
291#define PLLP_OUT4_CLKEN (1 << 17)
292
293
294#define PLLU_POWERDOWN (1 << 16)
295#define PLL_ENABLE_POWERDOWN (1 << 14)
296#define PLL_ACTIVE_POWERDOWN (1 << 12)
297
298
299#define UTMIP_FORCE_PD_SAMP_C_POWERDOWN (1 << 4)
300#define UTMIP_FORCE_PD_SAMP_B_POWERDOWN (1 << 2)
301#define UTMIP_FORCE_PD_SAMP_A_POWERDOWN (1 << 0)
302
303
304#define OSC_XOE_SHIFT 0
305#define OSC_XOE_MASK (1 << OSC_XOE_SHIFT)
306#define OSC_XOE_ENABLE (1 << OSC_XOE_SHIFT)
307#define OSC_XOBP_SHIFT 1
308#define OSC_XOBP_MASK (1U << OSC_XOBP_SHIFT)
309#define OSC_XOFS_SHIFT 4
310#define OSC_XOFS_MASK (0x3F << OSC_XOFS_SHIFT)
311#define OSC_DRIVE_STRENGTH 7
312
313
314
315
316
317
318
319
320#define OUT_CLK_DIVISOR_SHIFT 0
321#define OUT_CLK_DIVISOR_MASK (0xffff << OUT_CLK_DIVISOR_SHIFT)
322
323#define OUT_CLK_SOURCE_31_30_SHIFT 30
324#define OUT_CLK_SOURCE_31_30_MASK (3U << OUT_CLK_SOURCE_31_30_SHIFT)
325
326#define OUT_CLK_SOURCE_31_29_SHIFT 29
327#define OUT_CLK_SOURCE_31_29_MASK (7U << OUT_CLK_SOURCE_31_29_SHIFT)
328
329
330#define OUT_CLK_SOURCE_31_28_SHIFT 28
331#define OUT_CLK_SOURCE_31_28_MASK (15U << OUT_CLK_SOURCE_31_28_SHIFT)
332
333
334#define SCLK_SYS_STATE_SHIFT 28U
335#define SCLK_SYS_STATE_MASK (15U << SCLK_SYS_STATE_SHIFT)
336enum {
337 SCLK_SYS_STATE_STDBY,
338 SCLK_SYS_STATE_IDLE,
339 SCLK_SYS_STATE_RUN,
340 SCLK_SYS_STATE_IRQ = 4U,
341 SCLK_SYS_STATE_FIQ = 8U,
342};
343#define SCLK_COP_FIQ_MASK (1 << 27)
344#define SCLK_CPU_FIQ_MASK (1 << 26)
345#define SCLK_COP_IRQ_MASK (1 << 25)
346#define SCLK_CPU_IRQ_MASK (1 << 24)
347
348#define SCLK_SWAKEUP_FIQ_SOURCE_SHIFT 12
349#define SCLK_SWAKEUP_FIQ_SOURCE_MASK \
350 (7 << SCLK_SWAKEUP_FIQ_SOURCE_SHIFT)
351#define SCLK_SWAKEUP_IRQ_SOURCE_SHIFT 8
352#define SCLK_SWAKEUP_IRQ_SOURCE_MASK \
353 (7 << SCLK_SWAKEUP_FIQ_SOURCE_SHIFT)
354#define SCLK_SWAKEUP_RUN_SOURCE_SHIFT 4
355#define SCLK_SWAKEUP_RUN_SOURCE_MASK \
356 (7 << SCLK_SWAKEUP_FIQ_SOURCE_SHIFT)
357#define SCLK_SWAKEUP_IDLE_SOURCE_SHIFT 0
358
359#define SCLK_SWAKEUP_IDLE_SOURCE_MASK \
360 (7 << SCLK_SWAKEUP_FIQ_SOURCE_SHIFT)
361enum {
362 SCLK_SOURCE_CLKM,
363 SCLK_SOURCE_PLLC_OUT1,
364 SCLK_SOURCE_PLLP_OUT4,
365 SCLK_SOURCE_PLLP_OUT3,
366 SCLK_SOURCE_PLLP_OUT2,
367 SCLK_SOURCE_CLKD,
368 SCLK_SOURCE_CLKS,
369 SCLK_SOURCE_PLLM_OUT1,
370};
371#define SCLK_SWAKE_FIQ_SRC_PLLM_OUT1 (7 << 12)
372#define SCLK_SWAKE_IRQ_SRC_PLLM_OUT1 (7 << 8)
373#define SCLK_SWAKE_RUN_SRC_PLLM_OUT1 (7 << 4)
374#define SCLK_SWAKE_IDLE_SRC_PLLM_OUT1 (7 << 0)
375
376
377#define SUPER_SCLK_ENB_SHIFT 31U
378#define SUPER_SCLK_ENB_MASK (1U << 31)
379#define SUPER_SCLK_DIVIDEND_SHIFT 8
380#define SUPER_SCLK_DIVIDEND_MASK (0xff << SUPER_SCLK_DIVIDEND_SHIFT)
381#define SUPER_SCLK_DIVISOR_SHIFT 0
382#define SUPER_SCLK_DIVISOR_MASK (0xff << SUPER_SCLK_DIVISOR_SHIFT)
383
384
385#define CLK_SYS_RATE_HCLK_DISABLE_SHIFT 7
386#define CLK_SYS_RATE_HCLK_DISABLE_MASK (1 << CLK_SYS_RATE_HCLK_DISABLE_SHIFT)
387#define CLK_SYS_RATE_AHB_RATE_SHIFT 4
388#define CLK_SYS_RATE_AHB_RATE_MASK (3 << CLK_SYS_RATE_AHB_RATE_SHIFT)
389#define CLK_SYS_RATE_PCLK_DISABLE_SHIFT 3
390#define CLK_SYS_RATE_PCLK_DISABLE_MASK (1 << CLK_SYS_RATE_PCLK_DISABLE_SHIFT)
391#define CLK_SYS_RATE_APB_RATE_SHIFT 0
392#define CLK_SYS_RATE_APB_RATE_MASK (3 << CLK_SYS_RATE_AHB_RATE_SHIFT)
393
394
395#define CLR_CPURESET0 (1 << 0)
396#define CLR_CPURESET1 (1 << 1)
397#define CLR_CPURESET2 (1 << 2)
398#define CLR_CPURESET3 (1 << 3)
399#define CLR_DBGRESET0 (1 << 12)
400#define CLR_DBGRESET1 (1 << 13)
401#define CLR_DBGRESET2 (1 << 14)
402#define CLR_DBGRESET3 (1 << 15)
403#define CLR_CORERESET0 (1 << 16)
404#define CLR_CORERESET1 (1 << 17)
405#define CLR_CORERESET2 (1 << 18)
406#define CLR_CORERESET3 (1 << 19)
407#define CLR_CXRESET0 (1 << 20)
408#define CLR_CXRESET1 (1 << 21)
409#define CLR_CXRESET2 (1 << 22)
410#define CLR_CXRESET3 (1 << 23)
411#define CLR_L2RESET (1 << 24)
412#define CLR_NONCPURESET (1 << 29)
413#define CLR_PRESETDBG (1 << 30)
414
415
416#define CLR_CPU0_CLK_STP (1 << 8)
417#define CLR_CPU1_CLK_STP (1 << 9)
418#define CLR_CPU2_CLK_STP (1 << 10)
419#define CLR_CPU3_CLK_STP (1 << 11)
420
421
422#define MSELECT_CLK_SRC_PLLP_OUT0 (0 << 29)
423
424
425#define SET_CLK_ENB_CPUG_ENABLE (1 << 0)
426#define SET_CLK_ENB_CPULP_ENABLE (1 << 1)
427#define SET_CLK_ENB_MSELECT_ENABLE (1 << 3)
428
429
430#define PLL_ACTIVE_POWERDOWN (1 << 12)
431#define PLL_ENABLE_POWERDOWN (1 << 14)
432#define PLLU_POWERDOWN (1 << 16)
433
434
435#define UTMIP_FORCE_PD_SAMP_A_POWERDOWN (1 << 0)
436#define UTMIP_FORCE_PD_SAMP_B_POWERDOWN (1 << 2)
437#define UTMIP_FORCE_PD_SAMP_C_POWERDOWN (1 << 4)
438
439
440#define PLLX_IDDQ_SHIFT 3
441#define PLLX_IDDQ_MASK (1U << PLLX_IDDQ_SHIFT)
442
443
444#define PLLDP_SS_CFG_CLAMP (1 << 22)
445#define PLLDP_SS_CFG_UNDOCUMENTED (1 << 24)
446#define PLLDP_SS_CFG_DITHER (1 << 28)
447
448
449#define PLLD_CLKENABLE 30
450
451#endif
452