LXR uboot/arch/arm/include/asm/macro.h

   1/* SPDX-License-Identifier: GPL-2.0+ */
   2/*
   3 * include/asm-arm/macro.h
   4 *
   5 * Copyright (C) 2009 Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
   6 */
   7
   8#ifndef __ASM_ARM_MACRO_H__
   9#define __ASM_ARM_MACRO_H__
  10
  11#ifdef CONFIG_ARM64
  12#include <asm/system.h>
  13#endif
  14
  15#ifdef __ASSEMBLY__
  16
  17/*
  18 * These macros provide a convenient way to write 8, 16 and 32 bit data
  19 * to any address.
  20 * Registers r4 and r5 are used, any data in these registers are
  21 * overwritten by the macros.
  22 * The macros are valid for any ARM architecture, they do not implement
  23 * any memory barriers so caution is recommended when using these when the
  24 * caches are enabled or on a multi-core system.
  25 */
  26
  27.macro  write32, addr, data
  28        ldr     r4, =\addr
  29        ldr     r5, =\data
  30        str     r5, [r4]
  31.endm
  32
  33.macro  write16, addr, data
  34        ldr     r4, =\addr
  35        ldrh    r5, =\data
  36        strh    r5, [r4]
  37.endm
  38
  39.macro  write8, addr, data
  40        ldr     r4, =\addr
  41        ldrb    r5, =\data
  42        strb    r5, [r4]
  43.endm
  44
  45/*
  46 * This macro generates a loop that can be used for delays in the code.
  47 * Register r4 is used, any data in this register is overwritten by the
  48 * macro.
  49 * The macro is valid for any ARM architeture. The actual time spent in the
  50 * loop will vary from CPU to CPU though.
  51 */
  52
  53.macro  wait_timer, time
  54        ldr     r4, =\time
  551:
  56        nop
  57        subs    r4, r4, #1
  58        bcs     1b
  59.endm
  60
  61#ifdef CONFIG_ARM64
  62/*
  63 * Register aliases.
  64 */
  65lr      .req    x30
  66
  67/*
  68 * Branch according to exception level
  69 */
  70.macro  switch_el, xreg, el3_label, el2_label, el1_label
  71        mrs     \xreg, CurrentEL
  72        cmp     \xreg, 0xc
  73        b.eq    \el3_label
  74        cmp     \xreg, 0x8
  75        b.eq    \el2_label
  76        cmp     \xreg, 0x4
  77        b.eq    \el1_label
  78.endm
  79
  80/*
  81 * Branch if current processor is a Cortex-A57 core.
  82 */
  83.macro  branch_if_a57_core, xreg, a57_label
  84        mrs     \xreg, midr_el1
  85        lsr     \xreg, \xreg, #4
  86        and     \xreg, \xreg, #0x00000FFF
  87        cmp     \xreg, #0xD07           /* Cortex-A57 MPCore processor. */
  88        b.eq    \a57_label
  89.endm
  90
  91/*
  92 * Branch if current processor is a Cortex-A53 core.
  93 */
  94.macro  branch_if_a53_core, xreg, a53_label
  95        mrs     \xreg, midr_el1
  96        lsr     \xreg, \xreg, #4
  97        and     \xreg, \xreg, #0x00000FFF
  98        cmp     \xreg, #0xD03           /* Cortex-A53 MPCore processor. */
  99        b.eq    \a53_label
 100.endm
 101
 102/*
 103 * Branch if current processor is a slave,
 104 * choose processor with all zero affinity value as the master.
 105 */
 106.macro  branch_if_slave, xreg, slave_label
 107#ifdef CONFIG_ARMV8_MULTIENTRY
 108        /* NOTE: MPIDR handling will be erroneous on multi-cluster machines */
 109        mrs     \xreg, mpidr_el1
 110        tst     \xreg, #0xff            /* Test Affinity 0 */
 111        b.ne    \slave_label
 112        lsr     \xreg, \xreg, #8
 113        tst     \xreg, #0xff            /* Test Affinity 1 */
 114        b.ne    \slave_label
 115        lsr     \xreg, \xreg, #8
 116        tst     \xreg, #0xff            /* Test Affinity 2 */
 117        b.ne    \slave_label
 118        lsr     \xreg, \xreg, #16
 119        tst     \xreg, #0xff            /* Test Affinity 3 */
 120        b.ne    \slave_label
 121#endif
 122.endm
 123
 124/*
 125 * Branch if current processor is a master,
 126 * choose processor with all zero affinity value as the master.
 127 */
 128.macro  branch_if_master, xreg1, xreg2, master_label
 129#ifdef CONFIG_ARMV8_MULTIENTRY
 130        /* NOTE: MPIDR handling will be erroneous on multi-cluster machines */
 131        mrs     \xreg1, mpidr_el1
 132        lsr     \xreg2, \xreg1, #32
 133        lsl     \xreg2, \xreg2, #32
 134        lsl     \xreg1, \xreg1, #40
 135        lsr     \xreg1, \xreg1, #40
 136        orr     \xreg1, \xreg1, \xreg2
 137        cbz     \xreg1, \master_label
 138#else
 139        b       \master_label
 140#endif
 141.endm
 142
 143/*
 144 * Switch from EL3 to EL2 for ARMv8
 145 * @ep:     kernel entry point
 146 * @flag:   The execution state flag for lower exception
 147 *          level, ES_TO_AARCH64 or ES_TO_AARCH32
 148 * @tmp:    temporary register
 149 *
 150 * For loading 32-bit OS, x1 is machine nr and x2 is ftaddr.
 151 * For loading 64-bit OS, x0 is physical address to the FDT blob.
 152 * They will be passed to the guest.
 153 */
 154.macro armv8_switch_to_el2_m, ep, flag, tmp
 155        msr     cptr_el3, xzr           /* Disable coprocessor traps to EL3 */
 156        mov     \tmp, #CPTR_EL2_RES1
 157        msr     cptr_el2, \tmp          /* Disable coprocessor traps to EL2 */
 158
 159        /* Initialize Generic Timers */
 160        msr     cntvoff_el2, xzr
 161
 162        /* Initialize SCTLR_EL2
 163         *
 164         * setting RES1 bits (29,28,23,22,18,16,11,5,4) to 1
 165         * and RES0 bits (31,30,27,26,24,21,20,17,15-13,10-6) +
 166         * EE,WXN,I,SA,C,A,M to 0
 167         */
 168        ldr     \tmp, =(SCTLR_EL2_RES1 | SCTLR_EL2_EE_LE |\
 169                        SCTLR_EL2_WXN_DIS | SCTLR_EL2_ICACHE_DIS |\
 170                        SCTLR_EL2_SA_DIS | SCTLR_EL2_DCACHE_DIS |\
 171                        SCTLR_EL2_ALIGN_DIS | SCTLR_EL2_MMU_DIS)
 172        msr     sctlr_el2, \tmp
 173
 174        mov     \tmp, sp
 175        msr     sp_el2, \tmp            /* Migrate SP */
 176        mrs     \tmp, vbar_el3
 177        msr     vbar_el2, \tmp          /* Migrate VBAR */
 178
 179        /* Check switch to AArch64 EL2 or AArch32 Hypervisor mode */
 180        cmp     \flag, #ES_TO_AARCH32
 181        b.eq    1f
 182
 183        /*
 184         * The next lower exception level is AArch64, 64bit EL2 | HCE |
 185         * RES1 (Bits[5:4]) | Non-secure EL0/EL1.
 186         * and the SMD depends on requirements.
 187         */
 188#ifdef CONFIG_ARMV8_PSCI
 189        ldr     \tmp, =(SCR_EL3_RW_AARCH64 | SCR_EL3_HCE_EN |\
 190                        SCR_EL3_RES1 | SCR_EL3_NS_EN)
 191#else
 192        ldr     \tmp, =(SCR_EL3_RW_AARCH64 | SCR_EL3_HCE_EN |\
 193                        SCR_EL3_SMD_DIS | SCR_EL3_RES1 |\
 194                        SCR_EL3_NS_EN)
 195#endif
 196        msr     scr_el3, \tmp
 197
 198        /* Return to the EL2_SP2 mode from EL3 */
 199        ldr     \tmp, =(SPSR_EL_DEBUG_MASK | SPSR_EL_SERR_MASK |\
 200                        SPSR_EL_IRQ_MASK | SPSR_EL_FIQ_MASK |\
 201                        SPSR_EL_M_AARCH64 | SPSR_EL_M_EL2H)
 202        msr     spsr_el3, \tmp
 203        msr     elr_el3, \ep
 204        eret
 205
 2061:
 207        /*
 208         * The next lower exception level is AArch32, 32bit EL2 | HCE |
 209         * SMD | RES1 (Bits[5:4]) | Non-secure EL0/EL1.
 210         */
 211        ldr     \tmp, =(SCR_EL3_RW_AARCH32 | SCR_EL3_HCE_EN |\
 212                        SCR_EL3_SMD_DIS | SCR_EL3_RES1 |\
 213                        SCR_EL3_NS_EN)
 214        msr     scr_el3, \tmp
 215
 216        /* Return to AArch32 Hypervisor mode */
 217        ldr     \tmp, =(SPSR_EL_END_LE | SPSR_EL_ASYN_MASK |\
 218                        SPSR_EL_IRQ_MASK | SPSR_EL_FIQ_MASK |\
 219                        SPSR_EL_T_A32 | SPSR_EL_M_AARCH32 |\
 220                        SPSR_EL_M_HYP)
 221        msr     spsr_el3, \tmp
 222        msr     elr_el3, \ep
 223        eret
 224.endm
 225
 226/*
 227 * Switch from EL2 to EL1 for ARMv8
 228 * @ep:     kernel entry point
 229 * @flag:   The execution state flag for lower exception
 230 *          level, ES_TO_AARCH64 or ES_TO_AARCH32
 231 * @tmp:    temporary register
 232 *
 233 * For loading 32-bit OS, x1 is machine nr and x2 is ftaddr.
 234 * For loading 64-bit OS, x0 is physical address to the FDT blob.
 235 * They will be passed to the guest.
 236 */
 237.macro armv8_switch_to_el1_m, ep, flag, tmp
 238        /* Initialize Generic Timers */
 239        mrs     \tmp, cnthctl_el2
 240        /* Enable EL1 access to timers */
 241        orr     \tmp, \tmp, #(CNTHCTL_EL2_EL1PCEN_EN |\
 242                CNTHCTL_EL2_EL1PCTEN_EN)
 243        msr     cnthctl_el2, \tmp
 244        msr     cntvoff_el2, xzr
 245
 246        /* Initilize MPID/MPIDR registers */
 247        mrs     \tmp, midr_el1
 248        msr     vpidr_el2, \tmp
 249        mrs     \tmp, mpidr_el1
 250        msr     vmpidr_el2, \tmp
 251
 252        /* Disable coprocessor traps */
 253        mov     \tmp, #CPTR_EL2_RES1
 254        msr     cptr_el2, \tmp          /* Disable coprocessor traps to EL2 */
 255        msr     hstr_el2, xzr           /* Disable coprocessor traps to EL2 */
 256        mov     \tmp, #CPACR_EL1_FPEN_EN
 257        msr     cpacr_el1, \tmp         /* Enable FP/SIMD at EL1 */
 258
 259        /* SCTLR_EL1 initialization
 260         *
 261         * setting RES1 bits (29,28,23,22,20,11) to 1
 262         * and RES0 bits (31,30,27,21,17,13,10,6) +
 263         * UCI,EE,EOE,WXN,nTWE,nTWI,UCT,DZE,I,UMA,SED,ITD,
 264         * CP15BEN,SA0,SA,C,A,M to 0
 265         */
 266        ldr     \tmp, =(SCTLR_EL1_RES1 | SCTLR_EL1_UCI_DIS |\
 267                        SCTLR_EL1_EE_LE | SCTLR_EL1_WXN_DIS |\
 268                        SCTLR_EL1_NTWE_DIS | SCTLR_EL1_NTWI_DIS |\
 269                        SCTLR_EL1_UCT_DIS | SCTLR_EL1_DZE_DIS |\
 270                        SCTLR_EL1_ICACHE_DIS | SCTLR_EL1_UMA_DIS |\
 271                        SCTLR_EL1_SED_EN | SCTLR_EL1_ITD_EN |\
 272                        SCTLR_EL1_CP15BEN_DIS | SCTLR_EL1_SA0_DIS |\
 273                        SCTLR_EL1_SA_DIS | SCTLR_EL1_DCACHE_DIS |\
 274                        SCTLR_EL1_ALIGN_DIS | SCTLR_EL1_MMU_DIS)
 275        msr     sctlr_el1, \tmp
 276
 277        mov     \tmp, sp
 278        msr     sp_el1, \tmp            /* Migrate SP */
 279        mrs     \tmp, vbar_el2
 280        msr     vbar_el1, \tmp          /* Migrate VBAR */
 281
 282        /* Check switch to AArch64 EL1 or AArch32 Supervisor mode */
 283        cmp     \flag, #ES_TO_AARCH32
 284        b.eq    1f
 285
 286        /* Initialize HCR_EL2 */
 287        ldr     \tmp, =(HCR_EL2_RW_AARCH64 | HCR_EL2_HCD_DIS)
 288        msr     hcr_el2, \tmp
 289
 290        /* Return to the EL1_SP1 mode from EL2 */
 291        ldr     \tmp, =(SPSR_EL_DEBUG_MASK | SPSR_EL_SERR_MASK |\
 292                        SPSR_EL_IRQ_MASK | SPSR_EL_FIQ_MASK |\
 293                        SPSR_EL_M_AARCH64 | SPSR_EL_M_EL1H)
 294        msr     spsr_el2, \tmp
 295        msr     elr_el2, \ep
 296        eret
 297
 2981:
 299        /* Initialize HCR_EL2 */
 300        ldr     \tmp, =(HCR_EL2_RW_AARCH32 | HCR_EL2_HCD_DIS)
 301        msr     hcr_el2, \tmp
 302
 303        /* Return to AArch32 Supervisor mode from EL2 */
 304        ldr     \tmp, =(SPSR_EL_END_LE | SPSR_EL_ASYN_MASK |\
 305                        SPSR_EL_IRQ_MASK | SPSR_EL_FIQ_MASK |\
 306                        SPSR_EL_T_A32 | SPSR_EL_M_AARCH32 |\
 307                        SPSR_EL_M_SVC)
 308        msr     spsr_el2, \tmp
 309        msr     elr_el2, \ep
 310        eret
 311.endm
 312
 313#if defined(CONFIG_GICV3)
 314.macro gic_wait_for_interrupt_m xreg1
 3150 :     wfi
 316        mrs     \xreg1, ICC_IAR1_EL1
 317        msr     ICC_EOIR1_EL1, \xreg1
 318        cbnz    \xreg1, 0b
 319.endm
 320#elif defined(CONFIG_GICV2)
 321.macro gic_wait_for_interrupt_m xreg1, wreg2
 3220 :     wfi
 323        ldr     \wreg2, [\xreg1, GICC_AIAR]
 324        str     \wreg2, [\xreg1, GICC_AEOIR]
 325        and     \wreg2, \wreg2, #0x3ff
 326        cbnz    \wreg2, 0b
 327.endm
 328#endif
 329
 330#endif /* CONFIG_ARM64 */
 331
 332#endif /* __ASSEMBLY__ */
 333#endif /* __ASM_ARM_MACRO_H__ */
 334