LXR uboot/arch/arm/mach-socfpga/spl

   1// SPDX-License-Identifier: GPL-2.0+
   2/*
   3 *  Copyright (C) 2012 Altera Corporation <www.altera.com>
   4 */
   5
   6#include <common.h>
   7#include <asm/io.h>
   8#include <asm/pl310.h>
   9#include <asm/u-boot.h>
  10#include <asm/utils.h>
  11#include <image.h>
  12#include <asm/arch/reset_manager.h>
  13#include <spl.h>
  14#include <asm/arch/system_manager.h>
  15#include <asm/arch/freeze_controller.h>
  16#include <asm/arch/clock_manager.h>
  17#include <asm/arch/scan_manager.h>
  18#include <asm/arch/sdram.h>
  19#include <asm/arch/scu.h>
  20#include <asm/arch/misc.h>
  21#include <asm/arch/nic301.h>
  22#include <asm/sections.h>
  23#include <fdtdec.h>
  24#include <watchdog.h>
  25#include <asm/arch/pinmux.h>
  26
  27DECLARE_GLOBAL_DATA_PTR;
  28
  29static const struct socfpga_system_manager *sysmgr_regs =
  30        (struct socfpga_system_manager *)SOCFPGA_SYSMGR_ADDRESS;
  31
  32u32 spl_boot_device(void)
  33{
  34        const u32 bsel = readl(&sysmgr_regs->bootinfo);
  35
  36        switch (SYSMGR_GET_BOOTINFO_BSEL(bsel)) {
  37        case 0x1:       /* FPGA (HPS2FPGA Bridge) */
  38                return BOOT_DEVICE_RAM;
  39        case 0x2:       /* NAND Flash (1.8V) */
  40        case 0x3:       /* NAND Flash (3.0V) */
  41                socfpga_per_reset(SOCFPGA_RESET(NAND), 0);
  42                return BOOT_DEVICE_NAND;
  43        case 0x4:       /* SD/MMC External Transceiver (1.8V) */
  44        case 0x5:       /* SD/MMC Internal Transceiver (3.0V) */
  45                socfpga_per_reset(SOCFPGA_RESET(SDMMC), 0);
  46                socfpga_per_reset(SOCFPGA_RESET(DMA), 0);
  47                return BOOT_DEVICE_MMC1;
  48        case 0x6:       /* QSPI Flash (1.8V) */
  49        case 0x7:       /* QSPI Flash (3.0V) */
  50                socfpga_per_reset(SOCFPGA_RESET(QSPI), 0);
  51                return BOOT_DEVICE_SPI;
  52        default:
  53                printf("Invalid boot device (bsel=%08x)!\n", bsel);
  54                hang();
  55        }
  56}
  57
  58#ifdef CONFIG_SPL_MMC_SUPPORT
  59u32 spl_boot_mode(const u32 boot_device)
  60{
  61#if defined(CONFIG_SPL_FAT_SUPPORT) || defined(CONFIG_SPL_EXT_SUPPORT)
  62        return MMCSD_MODE_FS;
  63#else
  64        return MMCSD_MODE_RAW;
  65#endif
  66}
  67#endif
  68
  69void spl_board_init(void)
  70{
  71        /* enable console uart printing */
  72        preloader_console_init();
  73        WATCHDOG_RESET();
  74
  75        arch_early_init_r();
  76}
  77
  78void board_init_f(ulong dummy)
  79{
  80        socfpga_init_security_policies();
  81        socfpga_sdram_remap_zero();
  82
  83        /* Assert reset to all except L4WD0 and L4TIMER0 */
  84        socfpga_per_reset_all();
  85        socfpga_watchdog_disable();
  86
  87        spl_early_init();
  88
  89        /* Configure the clock based on handoff */
  90        cm_basic_init(gd->fdt_blob);
  91
  92#ifdef CONFIG_HW_WATCHDOG
  93        /* release osc1 watchdog timer 0 from reset */
  94        socfpga_reset_deassert_osc1wd0();
  95
  96        /* reconfigure and enable the watchdog */
  97        hw_watchdog_init();
  98        WATCHDOG_RESET();
  99#endif /* CONFIG_HW_WATCHDOG */
 100
 101        config_dedicated_pins(gd->fdt_blob);
 102        WATCHDOG_RESET();
 103}
 104