LXR uboot/arch/arm/mach-sunxi/dram_timings/lpddr3

   1#include <common.h>
   2#include <asm/arch/dram.h>
   3#include <asm/arch/cpu.h>
   4
   5void mctl_set_timing_params(uint16_t socid, struct dram_para *para)
   6{
   7        struct sunxi_mctl_ctl_reg * const mctl_ctl =
   8                        (struct sunxi_mctl_ctl_reg *)SUNXI_DRAM_CTL0_BASE;
   9
  10        u8 tccd         = 2;
  11        u8 tfaw         = max(ns_to_t(50), 4);
  12        u8 trrd         = max(ns_to_t(10), 2);
  13        u8 trcd         = max(ns_to_t(24), 2);
  14        u8 trc          = ns_to_t(70);
  15        u8 txp          = max(ns_to_t(8), 2);
  16        u8 twtr         = max(ns_to_t(8), 2);
  17        u8 trtp         = max(ns_to_t(8), 2);
  18        u8 twr          = max(ns_to_t(15), 3);
  19        u8 trp          = max(ns_to_t(27), 2);
  20        u8 tras         = ns_to_t(42);
  21        u16 trefi       = ns_to_t(3900) / 32;
  22        u16 trfc        = ns_to_t(210);
  23
  24        u8 tmrw         = 5;
  25        u8 tmrd         = 5;
  26        u8 tmod         = 12;
  27        u8 tcke         = 3;
  28        u8 tcksrx       = 5;
  29        u8 tcksre       = 5;
  30        u8 tckesr       = 5;
  31        u8 trasmax      = 24;
  32
  33        u8 tcl          = 6; /* CL 12 */
  34        u8 tcwl         = 3; /* CWL 6 */
  35        u8 t_rdata_en   = 5;
  36        u8 wr_latency   = 2;
  37
  38        u32 tdinit0     = (200 * CONFIG_DRAM_CLK) + 1;          /* 200us */
  39        u32 tdinit1     = (100 * CONFIG_DRAM_CLK) / 1000 + 1;   /* 100ns */
  40        u32 tdinit2     = (11 * CONFIG_DRAM_CLK) + 1;           /* 11us */
  41        u32 tdinit3     = (1 * CONFIG_DRAM_CLK) + 1;            /* 1us */
  42
  43        u8 twtp         = tcwl + 4 + twr + 1;
  44        u8 twr2rd       = tcwl + 4 + 1 + twtr;
  45        u8 trd2wr       = tcl + 4 + 5 - tcwl + 1;
  46
  47        /* set mode register */
  48        writel(0xc3, &mctl_ctl->mr[1]);         /* nWR=8, BL8 */
  49        writel(0xa, &mctl_ctl->mr[2]);          /* RL=12, WL=6 */
  50        writel(0x2, &mctl_ctl->mr[3]);          /* 40 0hms PD/PU */
  51
  52        /* set DRAM timing */
  53        writel(DRAMTMG0_TWTP(twtp) | DRAMTMG0_TFAW(tfaw) |
  54               DRAMTMG0_TRAS_MAX(trasmax) | DRAMTMG0_TRAS(tras),
  55               &mctl_ctl->dramtmg[0]);
  56        writel(DRAMTMG1_TXP(txp) | DRAMTMG1_TRTP(trtp) | DRAMTMG1_TRC(trc),
  57               &mctl_ctl->dramtmg[1]);
  58        writel(DRAMTMG2_TCWL(tcwl) | DRAMTMG2_TCL(tcl) |
  59               DRAMTMG2_TRD2WR(trd2wr) | DRAMTMG2_TWR2RD(twr2rd),
  60               &mctl_ctl->dramtmg[2]);
  61        writel(DRAMTMG3_TMRW(tmrw) | DRAMTMG3_TMRD(tmrd) | DRAMTMG3_TMOD(tmod),
  62               &mctl_ctl->dramtmg[3]);
  63        writel(DRAMTMG4_TRCD(trcd) | DRAMTMG4_TCCD(tccd) | DRAMTMG4_TRRD(trrd) |
  64               DRAMTMG4_TRP(trp), &mctl_ctl->dramtmg[4]);
  65        writel(DRAMTMG5_TCKSRX(tcksrx) | DRAMTMG5_TCKSRE(tcksre) |
  66               DRAMTMG5_TCKESR(tckesr) | DRAMTMG5_TCKE(tcke),
  67               &mctl_ctl->dramtmg[5]);
  68
  69        /* set two rank timing */
  70        clrsetbits_le32(&mctl_ctl->dramtmg[8], (0xff << 8) | (0xff << 0),
  71                        (0x66 << 8) | (0x10 << 0));
  72
  73        /* set PHY interface timing, write latency and read latency configure */
  74        writel((0x2 << 24) | (t_rdata_en << 16) | (0x1 << 8) |
  75               (wr_latency << 0), &mctl_ctl->pitmg[0]);
  76
  77        /* set PHY timing, PTR0-2 use default */
  78        writel(PTR3_TDINIT0(tdinit0) | PTR3_TDINIT1(tdinit1), &mctl_ctl->ptr[3]);
  79        writel(PTR4_TDINIT2(tdinit2) | PTR4_TDINIT3(tdinit3), &mctl_ctl->ptr[4]);
  80
  81        /* set refresh timing */
  82        writel(RFSHTMG_TREFI(trefi) | RFSHTMG_TRFC(trfc), &mctl_ctl->rfshtmg);
  83}
  84