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11#include <common.h>
12#include <errno.h>
13#include <spl.h>
14#include <asm/arch/cpu.h>
15#include <asm/arch/hardware.h>
16#include <asm/arch/omap.h>
17#include <asm/arch/ddr_defs.h>
18#include <asm/arch/clock.h>
19#include <asm/arch/gpio.h>
20#include <asm/arch/sys_proto.h>
21#include <asm/arch/mem.h>
22#include <asm/io.h>
23#include <asm/emif.h>
24#include <asm/gpio.h>
25#include <i2c.h>
26#include <power/tps65217.h>
27#include "../common/bur_common.h"
28#include <lcd.h>
29
30
31
32#define ESC_KEY (0+19)
33#define LCD_PWR (0+5)
34#define PUSH_KEY (0+31)
35
36
37
38
39#define RSTCTRL_ADDR 0x75
40
41#define RSTCTRL_CTRLREG 0x01
42
43#define RSTCTRL_SCRATCHREG 0x04
44
45
46#define RSTCTRL_FORCE_PWR_NEN 0x0404
47#define RSTCTRL_CAN_STB 0x4040
48
49DECLARE_GLOBAL_DATA_PTR;
50
51#if defined(CONFIG_SPL_BUILD)
52
53static const struct ddr_data ddr3_data = {
54 .datardsratio0 = MT41K256M16HA125E_RD_DQS,
55 .datawdsratio0 = MT41K256M16HA125E_WR_DQS,
56 .datafwsratio0 = MT41K256M16HA125E_PHY_FIFO_WE,
57 .datawrsratio0 = MT41K256M16HA125E_PHY_WR_DATA,
58};
59static const struct cmd_control ddr3_cmd_ctrl_data = {
60 .cmd0csratio = MT41K256M16HA125E_RATIO,
61 .cmd0iclkout = MT41K256M16HA125E_INVERT_CLKOUT,
62
63 .cmd1csratio = MT41K256M16HA125E_RATIO,
64 .cmd1iclkout = MT41K256M16HA125E_INVERT_CLKOUT,
65
66 .cmd2csratio = MT41K256M16HA125E_RATIO,
67 .cmd2iclkout = MT41K256M16HA125E_INVERT_CLKOUT,
68};
69static struct emif_regs ddr3_emif_reg_data = {
70 .sdram_config = MT41K256M16HA125E_EMIF_SDCFG,
71 .ref_ctrl = MT41K256M16HA125E_EMIF_SDREF,
72 .sdram_tim1 = MT41K256M16HA125E_EMIF_TIM1,
73 .sdram_tim2 = MT41K256M16HA125E_EMIF_TIM2,
74 .sdram_tim3 = MT41K256M16HA125E_EMIF_TIM3,
75 .zq_config = MT41K256M16HA125E_ZQ_CFG,
76 .emif_ddr_phy_ctlr_1 = MT41K256M16HA125E_EMIF_READ_LATENCY,
77};
78
79static const struct ctrl_ioregs ddr3_ioregs = {
80 .cm0ioctl = MT41K256M16HA125E_IOCTRL_VALUE,
81 .cm1ioctl = MT41K256M16HA125E_IOCTRL_VALUE,
82 .cm2ioctl = MT41K256M16HA125E_IOCTRL_VALUE,
83 .dt0ioctl = MT41K256M16HA125E_IOCTRL_VALUE,
84 .dt1ioctl = MT41K256M16HA125E_IOCTRL_VALUE,
85};
86
87#define OSC (V_OSCK/1000000)
88const struct dpll_params dpll_ddr3 = { 400, OSC-1, 1, -1, -1, -1, -1};
89
90void am33xx_spl_board_init(void)
91{
92 unsigned int oldspeed;
93 unsigned short buf;
94
95 struct cm_perpll *const cmper = (struct cm_perpll *)CM_PER;
96 struct cm_wkuppll *const cmwkup = (struct cm_wkuppll *)CM_WKUP;
97
98
99
100
101 u32 *const clk_domains[] = { 0 };
102
103 u32 *const clk_modules_xre1specific[] = {
104 &cmwkup->wkup_adctscctrl,
105 &cmper->spi1clkctrl,
106 &cmper->dcan0clkctrl,
107 &cmper->dcan1clkctrl,
108 &cmper->epwmss0clkctrl,
109 &cmper->epwmss1clkctrl,
110 &cmper->epwmss2clkctrl,
111 &cmper->lcdclkctrl,
112 &cmper->lcdcclkstctrl,
113 0
114 };
115 do_enable_clocks(clk_domains, clk_modules_xre1specific, 1);
116
117 gpio_direction_output(LCD_PWR, 0);
118
119
120 enable_i2c_pin_mux();
121 i2c_set_bus_num(0);
122 i2c_init(CONFIG_SYS_OMAP24_I2C_SPEED, CONFIG_SYS_OMAP24_I2C_SLAVE);
123
124
125 oldspeed = i2c_get_bus_speed();
126 if (i2c_set_bus_speed(CONFIG_SYS_OMAP24_I2C_SPEED_PSOC) >= 0) {
127 buf = RSTCTRL_FORCE_PWR_NEN | RSTCTRL_CAN_STB;
128 i2c_write(RSTCTRL_ADDR, RSTCTRL_CTRLREG, 1,
129 (uint8_t *)&buf, sizeof(buf));
130 i2c_set_bus_speed(oldspeed);
131 } else {
132 puts("ERROR: i2c_set_bus_speed failed! (turn on PWR_nEN)\n");
133 }
134
135 pmicsetup(0);
136}
137
138const struct dpll_params *get_dpll_ddr_params(void)
139{
140 return &dpll_ddr3;
141}
142
143void sdram_init(void)
144{
145 config_ddr(400, &ddr3_ioregs,
146 &ddr3_data,
147 &ddr3_cmd_ctrl_data,
148 &ddr3_emif_reg_data, 0);
149}
150#endif
151
152
153
154int board_init(void)
155{
156 gpmc_init();
157 return 0;
158}
159
160#ifdef CONFIG_BOARD_LATE_INIT
161int board_late_init(void)
162{
163 const unsigned int toff = 1000;
164 unsigned int cnt = 3;
165 unsigned short buf = 0xAAAA;
166 unsigned char scratchreg = 0;
167 unsigned int oldspeed;
168
169
170 oldspeed = i2c_get_bus_speed();
171 if (i2c_set_bus_speed(CONFIG_SYS_OMAP24_I2C_SPEED_PSOC) >= 0) {
172 i2c_read(RSTCTRL_ADDR, RSTCTRL_SCRATCHREG, 1,
173 &scratchreg, sizeof(scratchreg));
174 i2c_set_bus_speed(oldspeed);
175 } else {
176 puts("ERROR: i2c_set_bus_speed failed! (scratchregister)\n");
177 }
178
179 if (gpio_get_value(ESC_KEY)) {
180 do {
181 lcd_position_cursor(1, 8);
182 switch (cnt) {
183 case 3:
184 lcd_puts(
185 "release ESC-KEY to enter SERVICE-mode.");
186 break;
187 case 2:
188 lcd_puts(
189 "release ESC-KEY to enter DIAGNOSE-mode.");
190 break;
191 case 1:
192 lcd_puts(
193 "release ESC-KEY to enter BOOT-mode. ");
194 break;
195 }
196 mdelay(toff);
197 cnt--;
198 if (!gpio_get_value(ESC_KEY) &&
199 gpio_get_value(PUSH_KEY) && 2 == cnt) {
200 lcd_position_cursor(1, 8);
201 lcd_puts(
202 "switching to network-console ... ");
203 env_set("bootcmd", "run netconsole");
204 cnt = 4;
205 break;
206 } else if (!gpio_get_value(ESC_KEY) &&
207 gpio_get_value(PUSH_KEY) && 1 == cnt) {
208 lcd_position_cursor(1, 8);
209 lcd_puts(
210 "starting u-boot script from USB ... ");
211 env_set("bootcmd", "run usbscript");
212 cnt = 4;
213 break;
214 } else if ((!gpio_get_value(ESC_KEY) &&
215 gpio_get_value(PUSH_KEY) && cnt == 0) ||
216 (gpio_get_value(ESC_KEY) &&
217 gpio_get_value(PUSH_KEY) && cnt == 0)) {
218 lcd_position_cursor(1, 8);
219 lcd_puts(
220 "starting script from network ... ");
221 env_set("bootcmd", "run netscript");
222 cnt = 4;
223 break;
224 } else if (!gpio_get_value(ESC_KEY)) {
225 break;
226 }
227 } while (cnt);
228 } else if (scratchreg == 0xCC) {
229 lcd_position_cursor(1, 8);
230 lcd_puts(
231 "starting vxworks from network ... ");
232 env_set("bootcmd", "run netboot");
233 cnt = 4;
234 } else if (scratchreg == 0xCD) {
235 lcd_position_cursor(1, 8);
236 lcd_puts(
237 "starting script from network ... ");
238 env_set("bootcmd", "run netscript");
239 cnt = 4;
240 } else if (scratchreg == 0xCE) {
241 lcd_position_cursor(1, 8);
242 lcd_puts(
243 "starting AR from eMMC ... ");
244 env_set("bootcmd", "run mmcboot");
245 cnt = 4;
246 }
247
248 lcd_position_cursor(1, 8);
249 switch (cnt) {
250 case 0:
251 lcd_puts("entering BOOT-mode. ");
252 env_set("bootcmd", "run defaultAR");
253 buf = 0x0000;
254 break;
255 case 1:
256 lcd_puts("entering DIAGNOSE-mode. ");
257 buf = 0x0F0F;
258 break;
259 case 2:
260 lcd_puts("entering SERVICE mode. ");
261 buf = 0xB4B4;
262 break;
263 case 3:
264 lcd_puts("loading OS... ");
265 buf = 0x0404;
266 break;
267 }
268
269 oldspeed = i2c_get_bus_speed();
270 if (i2c_set_bus_speed(CONFIG_SYS_OMAP24_I2C_SPEED_PSOC) >= 0) {
271 i2c_write(RSTCTRL_ADDR, RSTCTRL_SCRATCHREG, 1,
272 (uint8_t *)&buf, sizeof(buf));
273 i2c_set_bus_speed(oldspeed);
274 } else {
275 puts("ERROR: i2c_set_bus_speed failed! (scratchregister)\n");
276 }
277
278 char othbootargs[128];
279 snprintf(othbootargs, sizeof(othbootargs),
280 "u=vxWorksFTP pw=vxWorks o=0x%08x;0x%08x;0x%08x;0x%08x",
281 (unsigned int) gd->fb_base-0x20,
282 (u32)env_get_ulong("vx_memtop", 16, gd->fb_base-0x20),
283 (u32)env_get_ulong("vx_romfsbase", 16, 0),
284 (u32)env_get_ulong("vx_romfssize", 16, 0));
285 env_set("othbootargs", othbootargs);
286
287
288
289
290 __asm__("ldr r0,=0x20000");
291 __asm__("mcr p15, 0, r0, c12, c0, 0");
292
293 return 0;
294}
295#endif
296
