1
2
3
4
5
6
7
8
9
10
11
12#include <asm/arch/clock.h>
13#include <asm/arch/imx-regs.h>
14#include <asm/arch/iomux.h>
15#include <asm/arch/mx6-pins.h>
16#include <linux/errno.h>
17#include <asm/gpio.h>
18#include <asm/mach-imx/iomux-v3.h>
19#include <asm/mach-imx/boot_mode.h>
20#include <asm/mach-imx/mxc_i2c.h>
21#include <asm/mach-imx/video.h>
22#include <mmc.h>
23#include <fsl_esdhc.h>
24#include <miiphy.h>
25#include <netdev.h>
26#include <asm/arch/mxc_hdmi.h>
27#include <asm/arch/crm_regs.h>
28#include <linux/fb.h>
29#include <ipu_pixfmt.h>
30#include <input.h>
31#include <asm/io.h>
32#include <asm/arch/sys_proto.h>
33#include <pwm.h>
34
35DECLARE_GLOBAL_DATA_PTR;
36
37#define UART_PAD_CTRL (PAD_CTL_PUS_100K_UP | \
38 PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm | \
39 PAD_CTL_SRE_FAST | PAD_CTL_HYS)
40
41#define USDHC_PAD_CTRL (PAD_CTL_PUS_47K_UP | \
42 PAD_CTL_SPEED_LOW | PAD_CTL_DSE_80ohm | \
43 PAD_CTL_SRE_FAST | PAD_CTL_HYS)
44
45#define ENET_PAD_CTRL (PAD_CTL_PUS_100K_UP | \
46 PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm | PAD_CTL_HYS)
47
48#define SPI_PAD_CTRL (PAD_CTL_HYS | PAD_CTL_SPEED_MED | \
49 PAD_CTL_DSE_40ohm | PAD_CTL_SRE_FAST)
50
51#define I2C_PAD_CTRL (PAD_CTL_PUS_100K_UP | \
52 PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm | PAD_CTL_HYS | \
53 PAD_CTL_ODE | PAD_CTL_SRE_FAST)
54
55#define PC MUX_PAD_CTRL(I2C_PAD_CTRL)
56
57#define DISP_PAD_CTRL (0x10)
58
59#define ECSPI4_CS1 IMX_GPIO_NR(5, 2)
60
61#if (CONFIG_SYS_BOARD_VERSION == 1)
62#include "./aristainetos-v1.c"
63#elif ((CONFIG_SYS_BOARD_VERSION == 2) || (CONFIG_SYS_BOARD_VERSION == 3))
64#include "./aristainetos-v2.c"
65#endif
66
67
68struct i2c_pads_info i2c_pad_info1 = {
69 .scl = {
70 .i2c_mode = MX6_PAD_CSI0_DAT9__I2C1_SCL | PC,
71 .gpio_mode = MX6_PAD_CSI0_DAT9__GPIO5_IO27 | PC,
72 .gp = IMX_GPIO_NR(5, 27)
73 },
74 .sda = {
75 .i2c_mode = MX6_PAD_CSI0_DAT8__I2C1_SDA | PC,
76 .gpio_mode = MX6_PAD_CSI0_DAT8__GPIO5_IO26 | PC,
77 .gp = IMX_GPIO_NR(5, 26)
78 }
79};
80
81struct i2c_pads_info i2c_pad_info2 = {
82 .scl = {
83 .i2c_mode = MX6_PAD_KEY_COL3__I2C2_SCL | PC,
84 .gpio_mode = MX6_PAD_KEY_COL3__GPIO4_IO12 | PC,
85 .gp = IMX_GPIO_NR(4, 12)
86 },
87 .sda = {
88 .i2c_mode = MX6_PAD_KEY_ROW3__I2C2_SDA | PC,
89 .gpio_mode = MX6_PAD_KEY_ROW3__GPIO4_IO13 | PC,
90 .gp = IMX_GPIO_NR(4, 13)
91 }
92};
93
94iomux_v3_cfg_t const usdhc1_pads[] = {
95 MX6_PAD_SD1_CLK__SD1_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL),
96 MX6_PAD_SD1_CMD__SD1_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL),
97 MX6_PAD_SD1_DAT0__SD1_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
98 MX6_PAD_SD1_DAT1__SD1_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
99 MX6_PAD_SD1_DAT2__SD1_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
100 MX6_PAD_SD1_DAT3__SD1_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
101};
102
103int dram_init(void)
104{
105 gd->ram_size = imx_ddr_size();
106
107 return 0;
108}
109
110#ifdef CONFIG_FSL_ESDHC
111struct fsl_esdhc_cfg usdhc_cfg[2] = {
112 {USDHC1_BASE_ADDR},
113 {USDHC2_BASE_ADDR},
114};
115
116int board_mmc_getcd(struct mmc *mmc)
117{
118 return 1;
119}
120
121int board_mmc_init(bd_t *bis)
122{
123 usdhc_cfg[0].sdhc_clk = mxc_get_clock(MXC_ESDHC_CLK);
124 imx_iomux_v3_setup_multiple_pads(usdhc1_pads, ARRAY_SIZE(usdhc1_pads));
125#if (CONFIG_SYS_BOARD_VERSION == 2)
126
127
128
129
130
131
132
133
134
135
136
137 imx_iomux_v3_setup_pad(MX6_PAD_SD2_DAT3__GPIO1_IO12 |
138 MUX_PAD_CTRL(NO_PAD_CTRL));
139 gpio_direction_output(IMX_GPIO_NR(1, 12) , 1);
140#endif
141 return fsl_esdhc_initialize(bis, &usdhc_cfg[0]);
142}
143#endif
144
145
146
147
148
149int overwrite_console(void)
150{
151 return 1;
152}
153
154struct display_info_t const displays[] = {
155 {
156 .bus = -1,
157 .addr = 0,
158 .pixfmt = IPU_PIX_FMT_RGB24,
159 .detect = NULL,
160 .enable = enable_lvds,
161 .mode = {
162 .name = "lb07wv8",
163 .refresh = 60,
164 .xres = 800,
165 .yres = 480,
166 .pixclock = 30066,
167 .left_margin = 88,
168 .right_margin = 88,
169 .upper_margin = 20,
170 .lower_margin = 20,
171 .hsync_len = 80,
172 .vsync_len = 5,
173 .sync = FB_SYNC_EXT,
174 .vmode = FB_VMODE_NONINTERLACED
175 }
176 }
177#if ((CONFIG_SYS_BOARD_VERSION == 2) || (CONFIG_SYS_BOARD_VERSION == 3))
178 , {
179 .bus = -1,
180 .addr = 0,
181 .pixfmt = IPU_PIX_FMT_RGB24,
182 .detect = NULL,
183 .enable = enable_spi_display,
184 .mode = {
185 .name = "lg4573",
186 .refresh = 57,
187 .xres = 480,
188 .yres = 800,
189 .pixclock = 37037,
190 .left_margin = 59,
191 .right_margin = 10,
192 .upper_margin = 15,
193 .lower_margin = 15,
194 .hsync_len = 10,
195 .vsync_len = 15,
196 .sync = FB_SYNC_EXT | FB_SYNC_HOR_HIGH_ACT |
197 FB_SYNC_VERT_HIGH_ACT,
198 .vmode = FB_VMODE_NONINTERLACED
199 }
200 }
201#endif
202};
203size_t display_count = ARRAY_SIZE(displays);
204
205
206int board_cfb_skip(void)
207{
208 return 1;
209}
210
211iomux_v3_cfg_t nfc_pads[] = {
212 MX6_PAD_NANDF_CLE__NAND_CLE | MUX_PAD_CTRL(NO_PAD_CTRL),
213 MX6_PAD_NANDF_ALE__NAND_ALE | MUX_PAD_CTRL(NO_PAD_CTRL),
214 MX6_PAD_NANDF_WP_B__NAND_WP_B | MUX_PAD_CTRL(NO_PAD_CTRL),
215 MX6_PAD_NANDF_RB0__NAND_READY_B | MUX_PAD_CTRL(NO_PAD_CTRL),
216 MX6_PAD_NANDF_CS0__NAND_CE0_B | MUX_PAD_CTRL(NO_PAD_CTRL),
217 MX6_PAD_SD4_CMD__NAND_RE_B | MUX_PAD_CTRL(NO_PAD_CTRL),
218 MX6_PAD_SD4_CLK__NAND_WE_B | MUX_PAD_CTRL(NO_PAD_CTRL),
219 MX6_PAD_NANDF_D0__NAND_DATA00 | MUX_PAD_CTRL(NO_PAD_CTRL),
220 MX6_PAD_NANDF_D1__NAND_DATA01 | MUX_PAD_CTRL(NO_PAD_CTRL),
221 MX6_PAD_NANDF_D2__NAND_DATA02 | MUX_PAD_CTRL(NO_PAD_CTRL),
222 MX6_PAD_NANDF_D3__NAND_DATA03 | MUX_PAD_CTRL(NO_PAD_CTRL),
223 MX6_PAD_NANDF_D4__NAND_DATA04 | MUX_PAD_CTRL(NO_PAD_CTRL),
224 MX6_PAD_NANDF_D5__NAND_DATA05 | MUX_PAD_CTRL(NO_PAD_CTRL),
225 MX6_PAD_NANDF_D6__NAND_DATA06 | MUX_PAD_CTRL(NO_PAD_CTRL),
226 MX6_PAD_NANDF_D7__NAND_DATA07 | MUX_PAD_CTRL(NO_PAD_CTRL),
227 MX6_PAD_SD4_DAT0__NAND_DQS | MUX_PAD_CTRL(NO_PAD_CTRL),
228};
229
230static void setup_gpmi_nand(void)
231{
232 struct mxc_ccm_reg *mxc_ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR;
233
234
235 imx_iomux_v3_setup_multiple_pads(nfc_pads,
236 ARRAY_SIZE(nfc_pads));
237
238
239 clrbits_le32(&mxc_ccm->CCGR2, MXC_CCM_CCGR2_IOMUX_IPT_CLK_IO_MASK);
240
241
242 clrsetbits_le32(&mxc_ccm->cs2cdr,
243 MXC_CCM_CS2CDR_ENFC_CLK_PODF_MASK |
244 MXC_CCM_CS2CDR_ENFC_CLK_PRED_MASK |
245 MXC_CCM_CS2CDR_ENFC_CLK_SEL_MASK,
246 MXC_CCM_CS2CDR_ENFC_CLK_PODF(0) |
247 MXC_CCM_CS2CDR_ENFC_CLK_PRED(3) |
248 MXC_CCM_CS2CDR_ENFC_CLK_SEL(3));
249
250
251 setbits_le32(&mxc_ccm->CCGR2, MXC_CCM_CCGR2_IOMUX_IPT_CLK_IO_MASK);
252
253
254 setbits_le32(&mxc_ccm->CCGR4,
255 MXC_CCM_CCGR4_RAWNAND_U_BCH_INPUT_APB_MASK |
256 MXC_CCM_CCGR4_RAWNAND_U_GPMI_BCH_INPUT_BCH_MASK |
257 MXC_CCM_CCGR4_RAWNAND_U_GPMI_BCH_INPUT_GPMI_IO_MASK |
258 MXC_CCM_CCGR4_RAWNAND_U_GPMI_INPUT_APB_MASK |
259 MXC_CCM_CCGR4_PL301_MX6QPER1_BCH_OFFSET);
260
261
262 setbits_le32(&mxc_ccm->CCGR0, MXC_CCM_CCGR0_APBHDMA_MASK);
263}
264
265int board_init(void)
266{
267 struct iomuxc *iomux = (struct iomuxc *)IOMUXC_BASE_ADDR;
268
269
270 gd->bd->bi_boot_params = PHYS_SDRAM + 0x100;
271
272 setup_spi();
273
274 setup_i2c(0, CONFIG_SYS_I2C_SPEED, CONFIG_SYS_I2C_SLAVE,
275 &i2c_pad_info1);
276 setup_i2c(1, CONFIG_SYS_I2C_SPEED, CONFIG_SYS_I2C_SLAVE,
277 &i2c_pad_info2);
278 setup_i2c(2, CONFIG_SYS_I2C_SPEED, CONFIG_SYS_I2C_SLAVE,
279 &i2c_pad_info3);
280 setup_i2c4();
281
282
283 gpio_request(CONFIG_GPIO_ENABLE_SPI_FLASH, "ena_spi_nor");
284 gpio_direction_output(CONFIG_GPIO_ENABLE_SPI_FLASH, 0);
285 gpio_free(CONFIG_GPIO_ENABLE_SPI_FLASH);
286
287 setup_board_gpio();
288 setup_gpmi_nand();
289 setup_board_spi();
290
291
292 clrsetbits_le32(&iomux->gpr[1], IOMUXC_GPR1_USB_OTG_ID_SEL_MASK, 0);
293 imx_iomux_v3_setup_multiple_pads(misc_pads, ARRAY_SIZE(misc_pads));
294 return 0;
295}
296
297int checkboard(void)
298{
299 printf("Board: %s\n", CONFIG_BOARDNAME);
300 return 0;
301}
302
303#ifdef CONFIG_USB_EHCI_MX6
304int board_ehci_hcd_init(int port)
305{
306 int ret;
307
308 ret = gpio_request(ARISTAINETOS_USB_H1_PWR, "usb-h1-pwr");
309 if (!ret)
310 gpio_direction_output(ARISTAINETOS_USB_H1_PWR, 1);
311 ret = gpio_request(ARISTAINETOS_USB_OTG_PWR, "usb-OTG-pwr");
312 if (!ret)
313 gpio_direction_output(ARISTAINETOS_USB_OTG_PWR, 1);
314 return 0;
315}
316
317int board_ehci_power(int port, int on)
318{
319 if (port)
320 gpio_set_value(ARISTAINETOS_USB_OTG_PWR, on);
321 else
322 gpio_set_value(ARISTAINETOS_USB_H1_PWR, on);
323 return 0;
324}
325#endif
326
