LXR uboot/board/atmel/sama5d2_ptc_ek/sama5d2_ptc

   1// SPDX-License-Identifier: GPL-2.0+
   2/*
   3 * Copyright (C) 2017 Microchip Corporation
   4 *                    Wenyou Yang <wenyou.yang@microchip.com>
   5 */
   6
   7#include <common.h>
   8#include <debug_uart.h>
   9#include <dm.h>
  10#include <i2c.h>
  11#include <nand.h>
  12#include <version.h>
  13#include <asm/io.h>
  14#include <asm/arch/at91_common.h>
  15#include <asm/arch/atmel_pio4.h>
  16#include <asm/arch/atmel_mpddrc.h>
  17#include <asm/arch/atmel_sdhci.h>
  18#include <asm/arch/clk.h>
  19#include <asm/arch/gpio.h>
  20#include <asm/arch/sama5d2.h>
  21#include <asm/arch/sama5d2_smc.h>
  22
  23extern void at91_pda_detect(void);
  24
  25DECLARE_GLOBAL_DATA_PTR;
  26
  27#ifdef CONFIG_NAND_ATMEL
  28static void board_nand_hw_init(void)
  29{
  30        struct at91_smc *smc = (struct at91_smc *)ATMEL_BASE_SMC;
  31
  32        at91_periph_clk_enable(ATMEL_ID_HSMC);
  33
  34        /* Configure SMC CS3 for NAND */
  35        writel(AT91_SMC_SETUP_NWE(1) | AT91_SMC_SETUP_NCS_WR(1) |
  36               AT91_SMC_SETUP_NRD(1) | AT91_SMC_SETUP_NCS_RD(1),
  37               &smc->cs[3].setup);
  38        writel(AT91_SMC_PULSE_NWE(2) | AT91_SMC_PULSE_NCS_WR(4) |
  39               AT91_SMC_PULSE_NRD(2) | AT91_SMC_PULSE_NCS_RD(3),
  40               &smc->cs[3].pulse);
  41        writel(AT91_SMC_CYCLE_NWE(6) | AT91_SMC_CYCLE_NRD(5),
  42               &smc->cs[3].cycle);
  43        writel(AT91_SMC_TIMINGS_TCLR(2) | AT91_SMC_TIMINGS_TADL(7) |
  44               AT91_SMC_TIMINGS_TAR(2)  | AT91_SMC_TIMINGS_TRR(3)   |
  45               AT91_SMC_TIMINGS_TWB(7)  | AT91_SMC_TIMINGS_RBNSEL(3) |
  46               AT91_SMC_TIMINGS_NFSEL(1), &smc->cs[3].timings);
  47        writel(AT91_SMC_MODE_RM_NRD | AT91_SMC_MODE_WM_NWE |
  48               AT91_SMC_MODE_EXNW_DISABLE |
  49               AT91_SMC_MODE_DBW_8 |
  50               AT91_SMC_MODE_TDF_CYCLE(3),
  51               &smc->cs[3].mode);
  52
  53        atmel_pio4_set_b_periph(AT91_PIO_PORTA, 22, ATMEL_PIO_DRVSTR_ME);       /* D0 */
  54        atmel_pio4_set_b_periph(AT91_PIO_PORTA, 23, ATMEL_PIO_DRVSTR_ME);       /* D1 */
  55        atmel_pio4_set_b_periph(AT91_PIO_PORTA, 24, ATMEL_PIO_DRVSTR_ME);       /* D2 */
  56        atmel_pio4_set_b_periph(AT91_PIO_PORTA, 25, ATMEL_PIO_DRVSTR_ME);       /* D3 */
  57        atmel_pio4_set_b_periph(AT91_PIO_PORTA, 26, ATMEL_PIO_DRVSTR_ME);       /* D4 */
  58        atmel_pio4_set_b_periph(AT91_PIO_PORTA, 27, ATMEL_PIO_DRVSTR_ME);       /* D5 */
  59        atmel_pio4_set_b_periph(AT91_PIO_PORTA, 28, ATMEL_PIO_DRVSTR_ME);       /* D6 */
  60        atmel_pio4_set_b_periph(AT91_PIO_PORTA, 29, ATMEL_PIO_DRVSTR_ME);       /* D7 */
  61        atmel_pio4_set_b_periph(AT91_PIO_PORTB, 2, 0);  /* RE */
  62        atmel_pio4_set_b_periph(AT91_PIO_PORTA, 30, 0); /* WE */
  63        atmel_pio4_set_b_periph(AT91_PIO_PORTA, 31, ATMEL_PIO_PUEN_MASK);       /* NCS */
  64        atmel_pio4_set_b_periph(AT91_PIO_PORTC, 8, ATMEL_PIO_PUEN_MASK);        /* RDY */
  65        atmel_pio4_set_b_periph(AT91_PIO_PORTB, 0, ATMEL_PIO_PUEN_MASK);        /* ALE */
  66        atmel_pio4_set_b_periph(AT91_PIO_PORTB, 1, ATMEL_PIO_PUEN_MASK);        /* CLE */
  67}
  68#endif
  69
  70#ifdef CONFIG_BOARD_LATE_INIT
  71int board_late_init(void)
  72{
  73        at91_pda_detect();
  74        return 0;
  75}
  76#endif
  77
  78static void board_usb_hw_init(void)
  79{
  80        atmel_pio4_set_pio_output(AT91_PIO_PORTB, 12, ATMEL_PIO_PUEN_MASK);
  81}
  82
  83#ifdef CONFIG_DEBUG_UART_BOARD_INIT
  84static void board_uart0_hw_init(void)
  85{
  86        atmel_pio4_set_c_periph(AT91_PIO_PORTB, 26, ATMEL_PIO_PUEN_MASK);       /* URXD0 */
  87        atmel_pio4_set_c_periph(AT91_PIO_PORTB, 27, 0); /* UTXD0 */
  88
  89        at91_periph_clk_enable(ATMEL_ID_UART0);
  90}
  91
  92void board_debug_uart_init(void)
  93{
  94        board_uart0_hw_init();
  95}
  96#endif
  97
  98#ifdef CONFIG_BOARD_EARLY_INIT_F
  99int board_early_init_f(void)
 100{
 101#ifdef CONFIG_DEBUG_UART
 102        debug_uart_init();
 103#endif
 104        return 0;
 105}
 106#endif
 107
 108int board_init(void)
 109{
 110        /* address of boot parameters */
 111        gd->bd->bi_boot_params = CONFIG_SYS_SDRAM_BASE + 0x100;
 112
 113#ifdef CONFIG_NAND_ATMEL
 114        board_nand_hw_init();
 115#endif
 116#ifdef CONFIG_CMD_USB
 117        board_usb_hw_init();
 118#endif
 119        return 0;
 120}
 121
 122int dram_init(void)
 123{
 124        gd->ram_size = get_ram_size((void *)CONFIG_SYS_SDRAM_BASE,
 125                                    CONFIG_SYS_SDRAM_SIZE);
 126        return 0;
 127}
 128
 129#define AT24MAC_MAC_OFFSET      0xfa
 130
 131#ifdef CONFIG_MISC_INIT_R
 132int misc_init_r(void)
 133{
 134#ifdef CONFIG_I2C_EEPROM
 135        at91_set_ethaddr(AT24MAC_MAC_OFFSET);
 136#endif
 137        return 0;
 138}
 139#endif
 140