LXR uboot/board/cssi/MCR3000/nand.c

   1// SPDX-License-Identifier: GPL-2.0+
   2/*
   3 * Copyright (C) 2010-2017 CS Systemes d'Information
   4 * Florent Trinh Thai <florent.trinh-thai@c-s.fr>
   5 * Christophe Leroy <christophe.leroy@c-s.fr>
   6 */
   7
   8#include <config.h>
   9#include <common.h>
  10#include <nand.h>
  11#include <asm/io.h>
  12
  13#define BIT_CLE                 ((unsigned short)0x0800)
  14#define BIT_ALE                 ((unsigned short)0x0400)
  15#define BIT_NCE                 ((unsigned short)0x1000)
  16
  17static void nand_hwcontrol(struct mtd_info *mtdinfo, int cmd, unsigned int ctrl)
  18{
  19        struct nand_chip *this  = mtd_to_nand(mtdinfo);
  20        immap_t __iomem *immr   = (immap_t __iomem *)CONFIG_SYS_IMMR;
  21        unsigned short pddat    = 0;
  22
  23        /* The hardware control change */
  24        if (ctrl & NAND_CTRL_CHANGE) {
  25                pddat = in_be16(&immr->im_ioport.iop_pddat);
  26
  27                /* Clearing ALE and CLE */
  28                pddat &= ~(BIT_CLE | BIT_ALE);
  29
  30                /* Driving NCE pin */
  31                if (ctrl & NAND_NCE)
  32                        pddat &= ~BIT_NCE;
  33                else
  34                        pddat |= BIT_NCE;
  35
  36                /* Driving CLE and ALE pin */
  37                if (ctrl & NAND_CLE)
  38                        pddat |= BIT_CLE;
  39                if (ctrl & NAND_ALE)
  40                        pddat |= BIT_ALE;
  41
  42                out_be16(&immr->im_ioport.iop_pddat, pddat);
  43        }
  44
  45        /* Writing the command */
  46        if (cmd != NAND_CMD_NONE)
  47                out_8(this->IO_ADDR_W, cmd);
  48}
  49
  50int board_nand_init(struct nand_chip *nand)
  51{
  52        immap_t __iomem *immr   = (immap_t __iomem *)CONFIG_SYS_IMMR;
  53
  54        /* Set GPIO Port */
  55        setbits_be16(&immr->im_ioport.iop_pddir, 0x1c00);
  56        clrbits_be16(&immr->im_ioport.iop_pdpar, 0x1c00);
  57        clrsetbits_be16(&immr->im_ioport.iop_pddat, 0x0c00, 0x1000);
  58
  59        nand->chip_delay        = 60;
  60        nand->ecc.mode          = NAND_ECC_SOFT;
  61        nand->cmd_ctrl          = nand_hwcontrol;
  62
  63        return 0;
  64}
  65