uboot/board/freescale/ls2080ardb/ls2080ardb.c
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   1// SPDX-License-Identifier: GPL-2.0+
   2/*
   3 * Copyright 2015 Freescale Semiconductor
   4 * Copyright 2017 NXP
   5 */
   6#include <common.h>
   7#include <malloc.h>
   8#include <errno.h>
   9#include <netdev.h>
  10#include <fsl_ifc.h>
  11#include <fsl_ddr.h>
  12#include <asm/io.h>
  13#include <hwconfig.h>
  14#include <fdt_support.h>
  15#include <linux/libfdt.h>
  16#include <fsl-mc/fsl_mc.h>
  17#include <environment.h>
  18#include <efi_loader.h>
  19#include <i2c.h>
  20#include <asm/arch/mmu.h>
  21#include <asm/arch/soc.h>
  22#include <asm/arch/ppa.h>
  23#include <fsl_sec.h>
  24
  25#ifdef CONFIG_FSL_QIXIS
  26#include "../common/qixis.h"
  27#include "ls2080ardb_qixis.h"
  28#endif
  29#include "../common/vid.h"
  30
  31#define PIN_MUX_SEL_SDHC        0x00
  32#define PIN_MUX_SEL_DSPI        0x0a
  33
  34#define SET_SDHC_MUX_SEL(reg, value)    ((reg & 0xf0) | value)
  35DECLARE_GLOBAL_DATA_PTR;
  36
  37enum {
  38        MUX_TYPE_SDHC,
  39        MUX_TYPE_DSPI,
  40};
  41
  42unsigned long long get_qixis_addr(void)
  43{
  44        unsigned long long addr;
  45
  46        if (gd->flags & GD_FLG_RELOC)
  47                addr = QIXIS_BASE_PHYS;
  48        else
  49                addr = QIXIS_BASE_PHYS_EARLY;
  50
  51        /*
  52         * IFC address under 256MB is mapped to 0x30000000, any address above
  53         * is mapped to 0x5_10000000 up to 4GB.
  54         */
  55        addr = addr  > 0x10000000 ? addr + 0x500000000ULL : addr + 0x30000000;
  56
  57        return addr;
  58}
  59
  60int checkboard(void)
  61{
  62#ifdef CONFIG_FSL_QIXIS
  63        u8 sw;
  64#endif
  65        char buf[15];
  66
  67        cpu_name(buf);
  68        printf("Board: %s-RDB, ", buf);
  69
  70#ifdef CONFIG_TARGET_LS2081ARDB
  71#ifdef CONFIG_FSL_QIXIS
  72        sw = QIXIS_READ(arch);
  73        printf("Board version: %c, ", (sw & 0xf) + 'A');
  74
  75        sw = QIXIS_READ(brdcfg[0]);
  76        sw = (sw >> QIXIS_QMAP_SHIFT) & QIXIS_QMAP_MASK;
  77        switch (sw) {
  78        case 0:
  79                puts("boot from QSPI DEV#0\n");
  80                puts("QSPI_CSA_1 mapped to QSPI DEV#1\n");
  81                break;
  82        case 1:
  83                puts("boot from QSPI DEV#1\n");
  84                puts("QSPI_CSA_1 mapped to QSPI DEV#0\n");
  85                break;
  86        case 2:
  87                puts("boot from QSPI EMU\n");
  88                puts("QSPI_CSA_1 mapped to QSPI DEV#0\n");
  89                break;
  90        case 3:
  91                puts("boot from QSPI EMU\n");
  92                puts("QSPI_CSA_1 mapped to QSPI DEV#1\n");
  93                break;
  94        case 4:
  95                puts("boot from QSPI DEV#0\n");
  96                puts("QSPI_CSA_1 mapped to QSPI EMU\n");
  97                break;
  98        default:
  99                printf("invalid setting of SW%u\n", sw);
 100                break;
 101        }
 102        printf("FPGA: v%d.%d\n", QIXIS_READ(scver), QIXIS_READ(tagdata));
 103#endif
 104        puts("SERDES1 Reference : ");
 105        printf("Clock1 = 100MHz ");
 106        printf("Clock2 = 161.13MHz");
 107#else
 108#ifdef CONFIG_FSL_QIXIS
 109        sw = QIXIS_READ(arch);
 110        printf("Board Arch: V%d, ", sw >> 4);
 111        printf("Board version: %c, boot from ", (sw & 0xf) + 'A');
 112
 113        sw = QIXIS_READ(brdcfg[0]);
 114        sw = (sw & QIXIS_LBMAP_MASK) >> QIXIS_LBMAP_SHIFT;
 115
 116        if (sw < 0x8)
 117                printf("vBank: %d\n", sw);
 118        else if (sw == 0x9)
 119                puts("NAND\n");
 120        else
 121                printf("invalid setting of SW%u\n", QIXIS_LBMAP_SWITCH);
 122
 123        printf("FPGA: v%d.%d\n", QIXIS_READ(scver), QIXIS_READ(tagdata));
 124#endif
 125        puts("SERDES1 Reference : ");
 126        printf("Clock1 = 156.25MHz ");
 127        printf("Clock2 = 156.25MHz");
 128#endif
 129
 130        puts("\nSERDES2 Reference : ");
 131        printf("Clock1 = 100MHz ");
 132        printf("Clock2 = 100MHz\n");
 133
 134        return 0;
 135}
 136
 137unsigned long get_board_sys_clk(void)
 138{
 139#ifdef CONFIG_FSL_QIXIS
 140        u8 sysclk_conf = QIXIS_READ(brdcfg[1]);
 141
 142        switch (sysclk_conf & 0x0F) {
 143        case QIXIS_SYSCLK_83:
 144                return 83333333;
 145        case QIXIS_SYSCLK_100:
 146                return 100000000;
 147        case QIXIS_SYSCLK_125:
 148                return 125000000;
 149        case QIXIS_SYSCLK_133:
 150                return 133333333;
 151        case QIXIS_SYSCLK_150:
 152                return 150000000;
 153        case QIXIS_SYSCLK_160:
 154                return 160000000;
 155        case QIXIS_SYSCLK_166:
 156                return 166666666;
 157        }
 158#endif
 159        return 100000000;
 160}
 161
 162int select_i2c_ch_pca9547(u8 ch)
 163{
 164        int ret;
 165
 166        ret = i2c_write(I2C_MUX_PCA_ADDR_PRI, 0, 1, &ch, 1);
 167        if (ret) {
 168                puts("PCA: failed to select proper channel\n");
 169                return ret;
 170        }
 171
 172        return 0;
 173}
 174
 175int i2c_multiplexer_select_vid_channel(u8 channel)
 176{
 177        return select_i2c_ch_pca9547(channel);
 178}
 179
 180int config_board_mux(int ctrl_type)
 181{
 182#ifdef CONFIG_FSL_QIXIS
 183        u8 reg5;
 184
 185        reg5 = QIXIS_READ(brdcfg[5]);
 186
 187        switch (ctrl_type) {
 188        case MUX_TYPE_SDHC:
 189                reg5 = SET_SDHC_MUX_SEL(reg5, PIN_MUX_SEL_SDHC);
 190                break;
 191        case MUX_TYPE_DSPI:
 192                reg5 = SET_SDHC_MUX_SEL(reg5, PIN_MUX_SEL_DSPI);
 193                break;
 194        default:
 195                printf("Wrong mux interface type\n");
 196                return -1;
 197        }
 198
 199        QIXIS_WRITE(brdcfg[5], reg5);
 200#endif
 201        return 0;
 202}
 203
 204int board_init(void)
 205{
 206#ifdef CONFIG_FSL_MC_ENET
 207        u32 __iomem *irq_ccsr = (u32 __iomem *)ISC_BASE;
 208#endif
 209
 210        init_final_memctl_regs();
 211
 212#ifdef CONFIG_ENV_IS_NOWHERE
 213        gd->env_addr = (ulong)&default_environment[0];
 214#endif
 215        select_i2c_ch_pca9547(I2C_MUX_CH_DEFAULT);
 216
 217#ifdef CONFIG_FSL_QIXIS
 218        QIXIS_WRITE(rst_ctl, QIXIS_RST_CTL_RESET_EN);
 219#endif
 220
 221#ifdef CONFIG_FSL_CAAM
 222        sec_init();
 223#endif
 224#ifdef CONFIG_FSL_LS_PPA
 225        ppa_init();
 226#endif
 227
 228#ifdef CONFIG_FSL_MC_ENET
 229        /* invert AQR405 IRQ pins polarity */
 230        out_le32(irq_ccsr + IRQCR_OFFSET / 4, AQR405_IRQ_MASK);
 231#endif
 232#ifdef CONFIG_FSL_CAAM
 233        sec_init();
 234#endif
 235
 236        return 0;
 237}
 238
 239int board_early_init_f(void)
 240{
 241#ifdef CONFIG_SYS_I2C_EARLY_INIT
 242        i2c_early_init_f();
 243#endif
 244        fsl_lsch3_early_init_f();
 245        return 0;
 246}
 247
 248int misc_init_r(void)
 249{
 250        char *env_hwconfig;
 251        u32 __iomem *dcfg_ccsr = (u32 __iomem *)DCFG_BASE;
 252        u32 val;
 253        struct ccsr_gur __iomem *gur = (void *)(CONFIG_SYS_FSL_GUTS_ADDR);
 254        u32 svr = gur_in32(&gur->svr);
 255
 256        val = in_le32(dcfg_ccsr + DCFG_RCWSR13 / 4);
 257
 258        env_hwconfig = env_get("hwconfig");
 259
 260        if (hwconfig_f("dspi", env_hwconfig) &&
 261            DCFG_RCWSR13_DSPI == (val & (u32)(0xf << 8)))
 262                config_board_mux(MUX_TYPE_DSPI);
 263        else
 264                config_board_mux(MUX_TYPE_SDHC);
 265
 266        /*
 267         * LS2081ARDB RevF board has smart voltage translator
 268         * which needs to be programmed to enable high speed SD interface
 269         * by setting GPIO4_10 output to zero
 270         */
 271#ifdef CONFIG_TARGET_LS2081ARDB
 272                out_le32(GPIO4_GPDIR_ADDR, (1 << 21 |
 273                                            in_le32(GPIO4_GPDIR_ADDR)));
 274                out_le32(GPIO4_GPDAT_ADDR, (~(1 << 21) &
 275                                            in_le32(GPIO4_GPDAT_ADDR)));
 276#endif
 277        if (hwconfig("sdhc"))
 278                config_board_mux(MUX_TYPE_SDHC);
 279
 280        if (adjust_vdd(0))
 281                printf("Warning: Adjusting core voltage failed.\n");
 282        /*
 283         * Default value of board env is based on filename which is
 284         * ls2080ardb. Modify board env for other supported SoCs
 285         */
 286        if ((SVR_SOC_VER(svr) == SVR_LS2088A) ||
 287            (SVR_SOC_VER(svr) == SVR_LS2048A))
 288                env_set("board", "ls2088ardb");
 289        else if ((SVR_SOC_VER(svr) == SVR_LS2081A) ||
 290            (SVR_SOC_VER(svr) == SVR_LS2041A))
 291                env_set("board", "ls2081ardb");
 292
 293        return 0;
 294}
 295
 296void detail_board_ddr_info(void)
 297{
 298        puts("\nDDR    ");
 299        print_size(gd->bd->bi_dram[0].size + gd->bd->bi_dram[1].size, "");
 300        print_ddr_info(0);
 301#ifdef CONFIG_SYS_FSL_HAS_DP_DDR
 302        if (soc_has_dp_ddr() && gd->bd->bi_dram[2].size) {
 303                puts("\nDP-DDR ");
 304                print_size(gd->bd->bi_dram[2].size, "");
 305                print_ddr_info(CONFIG_DP_DDR_CTRL);
 306        }
 307#endif
 308}
 309
 310#if defined(CONFIG_ARCH_MISC_INIT)
 311int arch_misc_init(void)
 312{
 313        return 0;
 314}
 315#endif
 316
 317#ifdef CONFIG_FSL_MC_ENET
 318void fdt_fixup_board_enet(void *fdt)
 319{
 320        int offset;
 321
 322        offset = fdt_path_offset(fdt, "/soc/fsl-mc");
 323
 324        if (offset < 0)
 325                offset = fdt_path_offset(fdt, "/fsl-mc");
 326
 327        if (offset < 0) {
 328                printf("%s: ERROR: fsl-mc node not found in device tree (error %d)\n",
 329                       __func__, offset);
 330                return;
 331        }
 332
 333        if ((get_mc_boot_status() == 0) && (get_dpl_apply_status() == 0))
 334                fdt_status_okay(fdt, offset);
 335        else
 336                fdt_status_fail(fdt, offset);
 337}
 338
 339void board_quiesce_devices(void)
 340{
 341        fsl_mc_ldpaa_exit(gd->bd);
 342}
 343#endif
 344
 345#ifdef CONFIG_OF_BOARD_SETUP
 346void fsl_fdt_fixup_flash(void *fdt)
 347{
 348        int offset;
 349
 350/*
 351 * IFC and QSPI are muxed on board.
 352 * So disable IFC node in dts if QSPI is enabled or
 353 * disable QSPI node in dts in case QSPI is not enabled.
 354 */
 355#ifdef CONFIG_FSL_QSPI
 356        offset = fdt_path_offset(fdt, "/soc/ifc");
 357
 358        if (offset < 0)
 359                offset = fdt_path_offset(fdt, "/ifc");
 360#else
 361        offset = fdt_path_offset(fdt, "/soc/quadspi");
 362
 363        if (offset < 0)
 364                offset = fdt_path_offset(fdt, "/quadspi");
 365#endif
 366        if (offset < 0)
 367                return;
 368
 369        fdt_status_disabled(fdt, offset);
 370}
 371
 372int ft_board_setup(void *blob, bd_t *bd)
 373{
 374        u64 base[CONFIG_NR_DRAM_BANKS];
 375        u64 size[CONFIG_NR_DRAM_BANKS];
 376
 377        ft_cpu_setup(blob, bd);
 378
 379        /* fixup DT for the two GPP DDR banks */
 380        base[0] = gd->bd->bi_dram[0].start;
 381        size[0] = gd->bd->bi_dram[0].size;
 382        base[1] = gd->bd->bi_dram[1].start;
 383        size[1] = gd->bd->bi_dram[1].size;
 384
 385#ifdef CONFIG_RESV_RAM
 386        /* reduce size if reserved memory is within this bank */
 387        if (gd->arch.resv_ram >= base[0] &&
 388            gd->arch.resv_ram < base[0] + size[0])
 389                size[0] = gd->arch.resv_ram - base[0];
 390        else if (gd->arch.resv_ram >= base[1] &&
 391                 gd->arch.resv_ram < base[1] + size[1])
 392                size[1] = gd->arch.resv_ram - base[1];
 393#endif
 394
 395        fdt_fixup_memory_banks(blob, base, size, 2);
 396
 397        fdt_fsl_mc_fixup_iommu_map_entry(blob);
 398
 399        fsl_fdt_fixup_dr_usb(blob, bd);
 400
 401        fsl_fdt_fixup_flash(blob);
 402
 403#ifdef CONFIG_FSL_MC_ENET
 404        fdt_fixup_board_enet(blob);
 405#endif
 406
 407        return 0;
 408}
 409#endif
 410
 411void qixis_dump_switch(void)
 412{
 413#ifdef CONFIG_FSL_QIXIS
 414        int i, nr_of_cfgsw;
 415
 416        QIXIS_WRITE(cms[0], 0x00);
 417        nr_of_cfgsw = QIXIS_READ(cms[1]);
 418
 419        puts("DIP switch settings dump:\n");
 420        for (i = 1; i <= nr_of_cfgsw; i++) {
 421                QIXIS_WRITE(cms[0], i);
 422                printf("SW%d = (0x%02x)\n", i, QIXIS_READ(cms[1]));
 423        }
 424#endif
 425}
 426
 427/*
 428 * Board rev C and earlier has duplicated I2C addresses for 2nd controller.
 429 * Both slots has 0x54, resulting 2nd slot unusable.
 430 */
 431void update_spd_address(unsigned int ctrl_num,
 432                        unsigned int slot,
 433                        unsigned int *addr)
 434{
 435#ifndef CONFIG_TARGET_LS2081ARDB
 436#ifdef CONFIG_FSL_QIXIS
 437        u8 sw;
 438
 439        sw = QIXIS_READ(arch);
 440        if ((sw & 0xf) < 0x3) {
 441                if (ctrl_num == 1 && slot == 0)
 442                        *addr = SPD_EEPROM_ADDRESS4;
 443                else if (ctrl_num == 1 && slot == 1)
 444                        *addr = SPD_EEPROM_ADDRESS3;
 445        }
 446#endif
 447#endif
 448}
 449