LXR uboot/board/freescale/t4qds/ddr.c

   1// SPDX-License-Identifier: GPL-2.0
   2/*
   3 * Copyright 2012 Freescale Semiconductor, Inc.
   4 */
   5
   6#include <common.h>
   7#include <i2c.h>
   8#include <hwconfig.h>
   9#include <asm/mmu.h>
  10#include <fsl_ddr_sdram.h>
  11#include <fsl_ddr_dimm_params.h>
  12#include <asm/fsl_law.h>
  13#include "ddr.h"
  14
  15DECLARE_GLOBAL_DATA_PTR;
  16
  17void fsl_ddr_board_options(memctl_options_t *popts,
  18                                dimm_params_t *pdimm,
  19                                unsigned int ctrl_num)
  20{
  21        const struct board_specific_parameters *pbsp, *pbsp_highest = NULL;
  22        ulong ddr_freq;
  23
  24        if (ctrl_num > 2) {
  25                printf("Not supported controller number %d\n", ctrl_num);
  26                return;
  27        }
  28        if (!pdimm->n_ranks)
  29                return;
  30
  31        /*
  32         * we use identical timing for all slots. If needed, change the code
  33         * to  pbsp = rdimms[ctrl_num] or pbsp = udimms[ctrl_num];
  34         */
  35        if (popts->registered_dimm_en)
  36                pbsp = rdimms[0];
  37        else
  38                pbsp = udimms[0];
  39
  40
  41        /* Get clk_adjust, cpo, write_data_delay,2T, according to the board ddr
  42         * freqency and n_banks specified in board_specific_parameters table.
  43         */
  44        ddr_freq = get_ddr_freq(0) / 1000000;
  45        while (pbsp->datarate_mhz_high) {
  46                if (pbsp->n_ranks == pdimm->n_ranks &&
  47                    (pdimm->rank_density >> 30) >= pbsp->rank_gb) {
  48                        if (ddr_freq <= pbsp->datarate_mhz_high) {
  49                                popts->cpo_override = pbsp->cpo;
  50                                popts->write_data_delay =
  51                                        pbsp->write_data_delay;
  52                                popts->clk_adjust = pbsp->clk_adjust;
  53                                popts->wrlvl_start = pbsp->wrlvl_start;
  54                                popts->wrlvl_ctl_2 = pbsp->wrlvl_ctl_2;
  55                                popts->wrlvl_ctl_3 = pbsp->wrlvl_ctl_3;
  56                                popts->twot_en = pbsp->force_2t;
  57                                goto found;
  58                        }
  59                        pbsp_highest = pbsp;
  60                }
  61                pbsp++;
  62        }
  63
  64        if (pbsp_highest) {
  65                printf("Error: board specific timing not found "
  66                        "for data rate %lu MT/s\n"
  67                        "Trying to use the highest speed (%u) parameters\n",
  68                        ddr_freq, pbsp_highest->datarate_mhz_high);
  69                popts->cpo_override = pbsp_highest->cpo;
  70                popts->write_data_delay = pbsp_highest->write_data_delay;
  71                popts->clk_adjust = pbsp_highest->clk_adjust;
  72                popts->wrlvl_start = pbsp_highest->wrlvl_start;
  73                popts->wrlvl_ctl_2 = pbsp->wrlvl_ctl_2;
  74                popts->wrlvl_ctl_3 = pbsp->wrlvl_ctl_3;
  75                popts->twot_en = pbsp_highest->force_2t;
  76        } else {
  77                panic("DIMM is not supported by this board");
  78        }
  79found:
  80        debug("Found timing match: n_ranks %d, data rate %d, rank_gb %d\n"
  81                "\tclk_adjust %d, wrlvl_start %d, wrlvl_ctrl_2 0x%x, "
  82                "wrlvl_ctrl_3 0x%x\n",
  83                pbsp->n_ranks, pbsp->datarate_mhz_high, pbsp->rank_gb,
  84                pbsp->clk_adjust, pbsp->wrlvl_start, pbsp->wrlvl_ctl_2,
  85                pbsp->wrlvl_ctl_3);
  86
  87        /*
  88         * Factors to consider for half-strength driver enable:
  89         *      - number of DIMMs installed
  90         */
  91        popts->half_strength_driver_enable = 0;
  92        /*
  93         * Write leveling override
  94         */
  95        popts->wrlvl_override = 1;
  96        popts->wrlvl_sample = 0xf;
  97
  98        /*
  99         * Rtt and Rtt_WR override
 100         */
 101        popts->rtt_override = 0;
 102
 103        /* Enable ZQ calibration */
 104        popts->zq_en = 1;
 105
 106        /* DHC_EN =1, ODT = 75 Ohm */
 107        popts->ddr_cdr1 = DDR_CDR1_DHC_EN | DDR_CDR1_ODT(DDR_CDR_ODT_75ohm);
 108        popts->ddr_cdr2 = DDR_CDR2_ODT(DDR_CDR_ODT_75ohm);
 109
 110        /* optimize cpo for erratum A-009942 */
 111        popts->cpo_sample = 0x63;
 112}
 113
 114int dram_init(void)
 115{
 116        phys_size_t dram_size;
 117
 118        puts("Initializing....using SPD\n");
 119
 120#if defined(CONFIG_SPL_BUILD) || !defined(CONFIG_RAMBOOT_PBL)
 121        dram_size = fsl_ddr_sdram();
 122#else
 123        /* DDR has been initialised by first stage boot loader */
 124        dram_size = fsl_ddr_sdram_size();
 125#endif
 126        dram_size = setup_ddr_tlbs(dram_size / 0x100000);
 127        dram_size *= 0x100000;
 128
 129        gd->ram_size = dram_size;
 130
 131        return 0;
 132}
 133