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7#include <asm/arch/clock.h>
8#include <asm/arch/iomux.h>
9#include <asm/arch/imx-regs.h>
10#include <asm/arch/crm_regs.h>
11#include <asm/arch/litesom.h>
12#include <asm/arch/mx6ul_pins.h>
13#include <asm/arch/mx6-pins.h>
14#include <asm/arch/sys_proto.h>
15#include <asm/gpio.h>
16#include <asm/mach-imx/iomux-v3.h>
17#include <asm/mach-imx/boot_mode.h>
18#include <asm/io.h>
19#include <common.h>
20#include <fsl_esdhc.h>
21#include <linux/sizes.h>
22#include <linux/fb.h>
23#include <miiphy.h>
24#include <mmc.h>
25#include <netdev.h>
26#include <spl.h>
27#include <usb.h>
28#include <usb/ehci-ci.h>
29
30DECLARE_GLOBAL_DATA_PTR;
31
32#define UART_PAD_CTRL (PAD_CTL_PKE | PAD_CTL_PUE | \
33 PAD_CTL_PUS_100K_UP | PAD_CTL_SPEED_MED | \
34 PAD_CTL_DSE_40ohm | PAD_CTL_SRE_FAST | PAD_CTL_HYS)
35
36#define USDHC_PAD_CTRL (PAD_CTL_PKE | PAD_CTL_PUE | \
37 PAD_CTL_PUS_22K_UP | PAD_CTL_SPEED_LOW | \
38 PAD_CTL_DSE_80ohm | PAD_CTL_SRE_FAST | PAD_CTL_HYS)
39
40#define ENET_PAD_CTRL (PAD_CTL_PUS_100K_UP | PAD_CTL_PUE | \
41 PAD_CTL_SPEED_HIGH | \
42 PAD_CTL_DSE_48ohm | PAD_CTL_SRE_FAST)
43
44#define MDIO_PAD_CTRL (PAD_CTL_PUS_100K_UP | PAD_CTL_PUE | \
45 PAD_CTL_DSE_48ohm | PAD_CTL_SRE_FAST | PAD_CTL_ODE)
46
47#define ENET_CLK_PAD_CTRL (PAD_CTL_DSE_40ohm | PAD_CTL_SRE_FAST)
48
49static iomux_v3_cfg_t const uart1_pads[] = {
50 MX6_PAD_UART1_TX_DATA__UART1_DCE_TX | MUX_PAD_CTRL(UART_PAD_CTRL),
51 MX6_PAD_UART1_RX_DATA__UART1_DCE_RX | MUX_PAD_CTRL(UART_PAD_CTRL),
52};
53
54static iomux_v3_cfg_t const sd_pads[] = {
55 MX6_PAD_SD1_CLK__USDHC1_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL),
56 MX6_PAD_SD1_CMD__USDHC1_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL),
57 MX6_PAD_SD1_DATA0__USDHC1_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
58 MX6_PAD_SD1_DATA1__USDHC1_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
59 MX6_PAD_SD1_DATA2__USDHC1_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
60 MX6_PAD_SD1_DATA3__USDHC1_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
61
62
63 MX6_PAD_UART1_RTS_B__GPIO1_IO19 | MUX_PAD_CTRL(NO_PAD_CTRL),
64};
65
66#ifdef CONFIG_FEC_MXC
67static iomux_v3_cfg_t const fec1_pads[] = {
68 MX6_PAD_GPIO1_IO06__ENET1_MDIO | MUX_PAD_CTRL(MDIO_PAD_CTRL),
69 MX6_PAD_GPIO1_IO07__ENET1_MDC | MUX_PAD_CTRL(ENET_PAD_CTRL),
70 MX6_PAD_ENET1_TX_DATA0__ENET1_TDATA00 | MUX_PAD_CTRL(ENET_PAD_CTRL),
71 MX6_PAD_ENET1_TX_DATA1__ENET1_TDATA01 | MUX_PAD_CTRL(ENET_PAD_CTRL),
72 MX6_PAD_ENET1_TX_EN__ENET1_TX_EN | MUX_PAD_CTRL(ENET_PAD_CTRL),
73 MX6_PAD_ENET1_TX_CLK__ENET1_REF_CLK1 | MUX_PAD_CTRL(ENET_CLK_PAD_CTRL),
74 MX6_PAD_ENET1_RX_DATA0__ENET1_RDATA00 | MUX_PAD_CTRL(ENET_PAD_CTRL),
75 MX6_PAD_ENET1_RX_DATA1__ENET1_RDATA01 | MUX_PAD_CTRL(ENET_PAD_CTRL),
76 MX6_PAD_ENET1_RX_ER__ENET1_RX_ER | MUX_PAD_CTRL(ENET_PAD_CTRL),
77 MX6_PAD_ENET1_RX_EN__ENET1_RX_EN | MUX_PAD_CTRL(ENET_PAD_CTRL),
78};
79
80static void setup_iomux_fec(void)
81{
82 imx_iomux_v3_setup_multiple_pads(fec1_pads, ARRAY_SIZE(fec1_pads));
83}
84#endif
85
86static void setup_iomux_uart(void)
87{
88 imx_iomux_v3_setup_multiple_pads(uart1_pads, ARRAY_SIZE(uart1_pads));
89}
90
91#ifdef CONFIG_FSL_ESDHC
92static struct fsl_esdhc_cfg sd_cfg = {USDHC1_BASE_ADDR, 0, 4};
93
94#define SD_CD_GPIO IMX_GPIO_NR(1, 19)
95
96static int mmc_get_env_devno(void)
97{
98 u32 soc_sbmr = readl(SRC_BASE_ADDR + 0x4);
99 int dev_no;
100 u32 bootsel;
101
102 bootsel = (soc_sbmr & 0x000000FF) >> 6;
103
104
105 if (bootsel != 1)
106 return CONFIG_SYS_MMC_ENV_DEV;
107
108
109 dev_no = (soc_sbmr & 0x00001800) >> 11;
110
111 return dev_no;
112}
113
114int board_mmc_getcd(struct mmc *mmc)
115{
116 struct fsl_esdhc_cfg *cfg = (struct fsl_esdhc_cfg *)mmc->priv;
117 int ret = 0;
118
119 switch (cfg->esdhc_base) {
120 case USDHC1_BASE_ADDR:
121 ret = !gpio_get_value(SD_CD_GPIO);
122 break;
123 case USDHC2_BASE_ADDR:
124 ret = 1;
125 break;
126 }
127
128 return ret;
129}
130
131int board_mmc_init(bd_t *bis)
132{
133 int ret;
134
135
136 imx_iomux_v3_setup_multiple_pads(sd_pads, ARRAY_SIZE(sd_pads));
137 gpio_direction_input(SD_CD_GPIO);
138 sd_cfg.sdhc_clk = mxc_get_clock(MXC_ESDHC_CLK);
139
140 ret = fsl_esdhc_initialize(bis, &sd_cfg);
141 if (ret) {
142 printf("Warning: failed to initialize mmc dev 0 (SD)\n");
143 return ret;
144 }
145
146 return litesom_mmc_init(bis);
147}
148
149static int check_mmc_autodetect(void)
150{
151 char *autodetect_str = env_get("mmcautodetect");
152
153 if ((autodetect_str != NULL) &&
154 (strcmp(autodetect_str, "yes") == 0)) {
155 return 1;
156 }
157
158 return 0;
159}
160
161void board_late_mmc_init(void)
162{
163 char cmd[32];
164 char mmcblk[32];
165 u32 dev_no = mmc_get_env_devno();
166
167 if (!check_mmc_autodetect())
168 return;
169
170 env_set_ulong("mmcdev", dev_no);
171
172
173 sprintf(mmcblk, "/dev/mmcblk%dp2 rootwait rw",
174 dev_no);
175 env_set("mmcroot", mmcblk);
176
177 sprintf(cmd, "mmc dev %d", dev_no);
178 run_command(cmd, 0);
179}
180#endif
181
182#ifdef CONFIG_FEC_MXC
183int board_eth_init(bd_t *bis)
184{
185 setup_iomux_fec();
186
187 return fecmxc_initialize(bis);
188}
189
190static int setup_fec(void)
191{
192 struct iomuxc *const iomuxc_regs = (struct iomuxc *)IOMUXC_BASE_ADDR;
193 int ret;
194
195
196
197 clrsetbits_le32(&iomuxc_regs->gpr[1], IOMUX_GPR1_FEC1_MASK,
198 IOMUX_GPR1_FEC1_CLOCK_MUX1_SEL_MASK);
199
200 ret = enable_fec_anatop_clock(0, ENET_50MHZ);
201 if (ret)
202 return ret;
203
204 enable_enet_clk(1);
205
206 return 0;
207}
208#endif
209
210#ifdef CONFIG_USB_EHCI_MX6
211int board_usb_phy_mode(int port)
212{
213 return USB_INIT_HOST;
214}
215#endif
216
217int board_early_init_f(void)
218{
219 setup_iomux_uart();
220
221 return 0;
222}
223
224int board_init(void)
225{
226
227 gd->bd->bi_boot_params = PHYS_SDRAM + 0x100;
228
229#ifdef CONFIG_FEC_MXC
230 setup_fec();
231#endif
232
233 return 0;
234}
235
236#ifdef CONFIG_CMD_BMODE
237static const struct boot_mode board_boot_modes[] = {
238
239 {"sd", MAKE_CFGVAL(0x40, 0x20, 0x00, 0x00)},
240 {"emmc", MAKE_CFGVAL(0x60, 0x48, 0x00, 0x00)},
241 {NULL, 0},
242};
243#endif
244
245int board_late_init(void)
246{
247#ifdef CONFIG_CMD_BMODE
248 add_board_boot_modes(board_boot_modes);
249#endif
250
251#ifdef CONFIG_ENV_IS_IN_MMC
252 board_late_mmc_init();
253#endif
254
255 return 0;
256}
257
258int checkboard(void)
259{
260 puts("Board: Grinn liteBoard\n");
261
262 return 0;
263}
264
265#ifdef CONFIG_SPL_BUILD
266void board_boot_order(u32 *spl_boot_list)
267{
268 struct src *psrc = (struct src *)SRC_BASE_ADDR;
269 unsigned gpr10_boot = readl(&psrc->gpr10) & (1 << 28);
270 unsigned reg = gpr10_boot ? readl(&psrc->gpr9) : readl(&psrc->sbmr1);
271 unsigned port = (reg >> 11) & 0x1;
272
273 if (port == 0) {
274 spl_boot_list[0] = BOOT_DEVICE_MMC1;
275 spl_boot_list[1] = BOOT_DEVICE_MMC2;
276 } else {
277 spl_boot_list[0] = BOOT_DEVICE_MMC2;
278 spl_boot_list[1] = BOOT_DEVICE_MMC1;
279 }
280}
281
282void board_init_f(ulong dummy)
283{
284 litesom_init_f();
285}
286#endif
287
