LXR uboot/board/isee/igep00x0/spl.c

   1// SPDX-License-Identifier: GPL-2.0+
   2
   3#include <asm/io.h>
   4#include <asm/arch/mem.h>
   5#include <asm/arch/sys_proto.h>
   6#include <jffs2/load_kernel.h>
   7#include <linux/mtd/rawnand.h>
   8#include "igep00x0.h"
   9
  10/*
  11 * Routine: get_board_mem_timings
  12 * Description: If we use SPL then there is no x-loader nor config header
  13 * so we have to setup the DDR timings ourself on both banks.
  14 */
  15void get_board_mem_timings(struct board_sdrc_timings *timings)
  16{
  17        int mfr, id, err = identify_nand_chip(&mfr, &id);
  18
  19        timings->mr = MICRON_V_MR_165;
  20        if (!err) {
  21                switch (mfr) {
  22                case NAND_MFR_HYNIX:
  23                        timings->mcfg = HYNIX_V_MCFG_200(256 << 20);
  24                        timings->ctrla = HYNIX_V_ACTIMA_200;
  25                        timings->ctrlb = HYNIX_V_ACTIMB_200;
  26                        break;
  27                case NAND_MFR_MICRON:
  28                        timings->mcfg = MICRON_V_MCFG_200(256 << 20);
  29                        timings->ctrla = MICRON_V_ACTIMA_200;
  30                        timings->ctrlb = MICRON_V_ACTIMB_200;
  31                        break;
  32                default:
  33                        /* Should not happen... */
  34                        break;
  35                }
  36                timings->rfr_ctrl = SDP_3430_SDRC_RFR_CTRL_200MHz;
  37                gpmc_cs0_flash = MTD_DEV_TYPE_NAND;
  38        } else {
  39                if (get_cpu_family() == CPU_OMAP34XX) {
  40                        timings->mcfg = NUMONYX_V_MCFG_165(256 << 20);
  41                        timings->ctrla = NUMONYX_V_ACTIMA_165;
  42                        timings->ctrlb = NUMONYX_V_ACTIMB_165;
  43                        timings->rfr_ctrl = SDP_3430_SDRC_RFR_CTRL_165MHz;
  44                } else {
  45                        timings->mcfg = NUMONYX_V_MCFG_200(256 << 20);
  46                        timings->ctrla = NUMONYX_V_ACTIMA_200;
  47                        timings->ctrlb = NUMONYX_V_ACTIMB_200;
  48                        timings->rfr_ctrl = SDP_3430_SDRC_RFR_CTRL_200MHz;
  49                }
  50                gpmc_cs0_flash = MTD_DEV_TYPE_ONENAND;
  51        }
  52}
  53
  54#ifdef CONFIG_SPL_OS_BOOT
  55int spl_start_uboot(void)
  56{
  57        /* break into full u-boot on 'c' */
  58        if (serial_tstc() && serial_getc() == 'c')
  59                return 1;
  60
  61        return 0;
  62}
  63#endif
  64