LXR uboot/board/qca/ap143/ap143.c

   1// SPDX-License-Identifier: GPL-2.0+
   2/*
   3 * Copyright (C) 2015-2016 Wills Wang <wills.wang@live.com>
   4 */
   5
   6#include <common.h>
   7#include <asm/io.h>
   8#include <asm/addrspace.h>
   9#include <asm/types.h>
  10#include <mach/ar71xx_regs.h>
  11#include <mach/ddr.h>
  12#include <mach/ath79.h>
  13#include <debug_uart.h>
  14
  15#ifdef CONFIG_DEBUG_UART_BOARD_INIT
  16void board_debug_uart_init(void)
  17{
  18        void __iomem *regs;
  19        u32 val;
  20
  21        regs = map_physmem(AR71XX_GPIO_BASE, AR71XX_GPIO_SIZE,
  22                           MAP_NOCACHE);
  23
  24        /*
  25         * GPIO9 as input, GPIO10 as output
  26         */
  27        val = readl(regs + AR71XX_GPIO_REG_OE);
  28        val |= QCA953X_GPIO(9);
  29        val &= ~QCA953X_GPIO(10);
  30        writel(val, regs + AR71XX_GPIO_REG_OE);
  31
  32        /*
  33         * Enable GPIO10 as UART0_SOUT
  34         */
  35        val = readl(regs + QCA953X_GPIO_REG_OUT_FUNC2);
  36        val &= ~QCA953X_GPIO_MUX_MASK(16);
  37        val |= QCA953X_GPIO_OUT_MUX_UART0_SOUT << 16;
  38        writel(val, regs + QCA953X_GPIO_REG_OUT_FUNC2);
  39
  40        /*
  41         * Enable GPIO9 as UART0_SIN
  42         */
  43        val = readl(regs + QCA953X_GPIO_REG_IN_ENABLE0);
  44        val &= ~QCA953X_GPIO_MUX_MASK(8);
  45        val |= QCA953X_GPIO_IN_MUX_UART0_SIN << 8;
  46        writel(val, regs + QCA953X_GPIO_REG_IN_ENABLE0);
  47
  48        /*
  49         * Enable GPIO10 output
  50         */
  51        val = readl(regs + AR71XX_GPIO_REG_OUT);
  52        val |= QCA953X_GPIO(10);
  53        writel(val, regs + AR71XX_GPIO_REG_OUT);
  54}
  55#endif
  56
  57int board_early_init_f(void)
  58{
  59        ddr_init();
  60        ath79_eth_reset();
  61        return 0;
  62}
  63