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10#ifndef __CONFIG_H
11#define __CONFIG_H
12
13#include "../board/freescale/common/ics307_clk.h"
14
15#ifdef CONFIG_SDCARD
16#define CONFIG_RAMBOOT_SDCARD 1
17#define CONFIG_RESET_VECTOR_ADDRESS 0xf8fffffc
18#endif
19
20#ifdef CONFIG_SPIFLASH
21#define CONFIG_RAMBOOT_SPIFLASH 1
22#define CONFIG_RESET_VECTOR_ADDRESS 0xf8fffffc
23#endif
24
25#ifndef CONFIG_RESET_VECTOR_ADDRESS
26#define CONFIG_RESET_VECTOR_ADDRESS 0xeffffffc
27#endif
28
29#ifndef CONFIG_SYS_MONITOR_BASE
30#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE
31#endif
32
33#define CONFIG_PCI1 1
34#define CONFIG_PCIE1 1
35#define CONFIG_PCIE2 1
36#define CONFIG_PCIE3 1
37#define CONFIG_FSL_PCI_INIT 1
38#define CONFIG_PCI_INDIRECT_BRIDGE 1
39#define CONFIG_FSL_PCIE_RESET 1
40#define CONFIG_SYS_PCI_64BIT 1
41
42
43#define CONFIG_ENV_OVERWRITE
44
45#define CONFIG_SYS_CLK_FREQ get_board_sys_clk()
46#define CONFIG_DDR_CLK_FREQ get_board_ddr_clk()
47#define CONFIG_ICS307_REFCLK_HZ 33333000
48
49
50
51
52#define CONFIG_L2_CACHE
53#define CONFIG_BTB
54
55#define CONFIG_ENABLE_36BIT_PHYS 1
56
57#ifdef CONFIG_PHYS_64BIT
58#define CONFIG_ADDR_MAP 1
59#define CONFIG_SYS_NUM_ADDR_MAP 16
60#endif
61
62#define CONFIG_SYS_MEMTEST_START 0x00010000
63#define CONFIG_SYS_MEMTEST_END 0x1f000000
64
65
66
67
68#define CONFIG_SYS_INIT_L2_ADDR 0xf8f80000
69#ifdef CONFIG_PHYS_64BIT
70#define CONFIG_SYS_INIT_L2_ADDR_PHYS 0xff8f80000ull
71#else
72#define CONFIG_SYS_INIT_L2_ADDR_PHYS CONFIG_SYS_INIT_L2_ADDR
73#endif
74#define CONFIG_SYS_L2_SIZE (512 << 10)
75#define CONFIG_SYS_INIT_L2_END (CONFIG_SYS_INIT_L2_ADDR + CONFIG_SYS_L2_SIZE)
76
77#define CONFIG_SYS_CCSRBAR 0xffe00000
78#define CONFIG_SYS_CCSRBAR_PHYS_LOW CONFIG_SYS_CCSRBAR
79
80#if defined(CONFIG_NAND_SPL)
81#define CONFIG_SYS_CCSR_DO_NOT_RELOCATE
82#endif
83
84
85#define CONFIG_VERY_BIG_RAM
86#undef CONFIG_FSL_DDR_INTERACTIVE
87#define CONFIG_SPD_EEPROM
88#define CONFIG_DDR_SPD
89
90#define CONFIG_ECC_INIT_VIA_DDRCONTROLLER
91#define CONFIG_MEM_INIT_VALUE 0xDeadBeef
92
93#define CONFIG_SYS_DDR_SDRAM_BASE 0x00000000
94#define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE
95
96#define CONFIG_DIMM_SLOTS_PER_CTLR 1
97#define CONFIG_CHIP_SELECTS_PER_CTRL 2
98
99
100#define SPD_EEPROM_ADDRESS 0x51
101#define CONFIG_SYS_SPD_BUS_NUM 1
102
103
104#define CONFIG_SYS_SDRAM_SIZE 256
105#define CONFIG_SYS_DDR_CS0_BNDS 0x0000001F
106#define CONFIG_SYS_DDR_CS0_CONFIG 0x80010102
107#define CONFIG_SYS_DDR_TIMING_3 0x00000000
108#define CONFIG_SYS_DDR_TIMING_0 0x00260802
109#define CONFIG_SYS_DDR_TIMING_1 0x3935d322
110#define CONFIG_SYS_DDR_TIMING_2 0x14904cc8
111#define CONFIG_SYS_DDR_MODE_1 0x00480432
112#define CONFIG_SYS_DDR_MODE_2 0x00000000
113#define CONFIG_SYS_DDR_INTERVAL 0x06180100
114#define CONFIG_SYS_DDR_DATA_INIT 0xdeadbeef
115#define CONFIG_SYS_DDR_CLK_CTRL 0x03800000
116#define CONFIG_SYS_DDR_OCD_CTRL 0x00000000
117#define CONFIG_SYS_DDR_OCD_STATUS 0x00000000
118#define CONFIG_SYS_DDR_CONTROL 0xC3008000
119#define CONFIG_SYS_DDR_CONTROL2 0x04400010
120
121#define CONFIG_SYS_DDR_ERR_INT_EN 0x0000000d
122#define CONFIG_SYS_DDR_ERR_DIS 0x00000000
123#define CONFIG_SYS_DDR_SBE 0x00010000
124
125
126#ifndef CONFIG_SPD_EEPROM
127#error ("CONFIG_SPD_EEPROM is required")
128#endif
129
130#undef CONFIG_CLOCKS_IN_MHZ
131
132
133
134
135
136
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142
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153
154
155#define CONFIG_SYS_FLASH_BASE 0xe0000000
156#ifdef CONFIG_PHYS_64BIT
157#define CONFIG_SYS_FLASH_BASE_PHYS 0xfe0000000ull
158#else
159#define CONFIG_SYS_FLASH_BASE_PHYS CONFIG_SYS_FLASH_BASE
160#endif
161
162#define CONFIG_FLASH_BR_PRELIM \
163 (BR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS + 0x8000000) | BR_PS_16 | BR_V)
164#define CONFIG_FLASH_OR_PRELIM 0xf8000ff7
165
166#define CONFIG_SYS_BR1_PRELIM \
167 (BR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS) \
168 | BR_PS_16 | BR_V)
169#define CONFIG_SYS_OR1_PRELIM 0xf8000ff7
170
171#define CONFIG_SYS_FLASH_BANKS_LIST { CONFIG_SYS_FLASH_BASE_PHYS + 0x8000000, \
172 CONFIG_SYS_FLASH_BASE_PHYS }
173#define CONFIG_SYS_FLASH_QUIET_TEST
174#define CONFIG_FLASH_SHOW_PROGRESS 45
175
176#define CONFIG_SYS_MAX_FLASH_BANKS 2
177#define CONFIG_SYS_MAX_FLASH_SECT 1024
178#undef CONFIG_SYS_FLASH_CHECKSUM
179#define CONFIG_SYS_FLASH_ERASE_TOUT 60000
180#define CONFIG_SYS_FLASH_WRITE_TOUT 500
181
182#if defined(CONFIG_RAMBOOT_SDCARD) || defined(CONFIG_RAMBOOT_SPIFLASH)
183#define CONFIG_SYS_RAMBOOT
184#else
185#undef CONFIG_SYS_RAMBOOT
186#endif
187
188#define CONFIG_SYS_FLASH_EMPTY_INFO
189#define CONFIG_SYS_FLASH_AMD_CHECK_DQ7
190
191#define CONFIG_HWCONFIG
192#define CONFIG_FSL_PIXIS 1
193#define PIXIS_BASE 0xffdf0000
194#ifdef CONFIG_PHYS_64BIT
195#define PIXIS_BASE_PHYS 0xfffdf0000ull
196#else
197#define PIXIS_BASE_PHYS PIXIS_BASE
198#endif
199
200#define CONFIG_SYS_BR3_PRELIM (BR_PHYS_ADDR(PIXIS_BASE_PHYS) | BR_PS_8 | BR_V)
201#define CONFIG_SYS_OR3_PRELIM 0xffffeff7
202
203#define PIXIS_ID 0x0
204#define PIXIS_VER 0x1
205#define PIXIS_PVER 0x2
206#define PIXIS_CSR 0x3
207#define PIXIS_RST 0x4
208#define PIXIS_PWR 0x5
209#define PIXIS_AUX 0x6
210#define PIXIS_SPD 0x7
211#define PIXIS_AUX2 0x8
212#define PIXIS_VCTL 0x10
213#define PIXIS_VSTAT 0x11
214#define PIXIS_VCFGEN0 0x12
215#define PIXIS_VCFGEN1 0x13
216#define PIXIS_VCORE0 0x14
217#define PIXIS_VBOOT 0x16
218#define PIXIS_VBOOT_LBMAP 0xe0
219#define PIXIS_VBOOT_LBMAP_NOR0 0x00
220#define PIXIS_VBOOT_LBMAP_NOR1 0x01
221#define PIXIS_VBOOT_LBMAP_NOR2 0x02
222#define PIXIS_VBOOT_LBMAP_NOR3 0x03
223#define PIXIS_VBOOT_LBMAP_PJET 0x04
224#define PIXIS_VBOOT_LBMAP_NAND 0x05
225#define PIXIS_VSPEED0 0x17
226#define PIXIS_VSPEED1 0x18
227#define PIXIS_VSPEED2 0x19
228#define PIXIS_VSYSCLK0 0x1A
229#define PIXIS_VSYSCLK1 0x1B
230#define PIXIS_VSYSCLK2 0x1C
231#define PIXIS_VDDRCLK0 0x1D
232#define PIXIS_VDDRCLK1 0x1E
233#define PIXIS_VDDRCLK2 0x1F
234#define PIXIS_VWATCH 0x24
235#define PIXIS_LED 0x25
236
237#define PIXIS_SPD_SYSCLK 0x7
238
239
240#define PIXIS_VCLKH 0x19
241#define PIXIS_VCLKL 0x1A
242#define CONFIG_SYS_PIXIS_VBOOT_MASK 0x4e
243
244#define CONFIG_SYS_INIT_RAM_LOCK 1
245#define CONFIG_SYS_INIT_RAM_ADDR 0xffd00000
246#define CONFIG_SYS_INIT_RAM_SIZE 0x00004000
247
248#define CONFIG_SYS_GBL_DATA_OFFSET \
249 (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
250#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
251
252#define CONFIG_SYS_MONITOR_LEN (256 * 1024)
253#define CONFIG_SYS_MALLOC_LEN (1024 * 1024)
254
255#ifndef CONFIG_NAND_SPL
256#define CONFIG_SYS_NAND_BASE 0xffa00000
257#ifdef CONFIG_PHYS_64BIT
258#define CONFIG_SYS_NAND_BASE_PHYS 0xfffa00000ull
259#else
260#define CONFIG_SYS_NAND_BASE_PHYS CONFIG_SYS_NAND_BASE
261#endif
262#else
263#define CONFIG_SYS_NAND_BASE 0xfff00000
264#ifdef CONFIG_PHYS_64BIT
265#define CONFIG_SYS_NAND_BASE_PHYS 0xffff00000ull
266#else
267#define CONFIG_SYS_NAND_BASE_PHYS CONFIG_SYS_NAND_BASE
268#endif
269#endif
270#define CONFIG_SYS_NAND_BASE_LIST { CONFIG_SYS_NAND_BASE,\
271 CONFIG_SYS_NAND_BASE + 0x40000, \
272 CONFIG_SYS_NAND_BASE + 0x80000, \
273 CONFIG_SYS_NAND_BASE + 0xC0000}
274#define CONFIG_SYS_MAX_NAND_DEVICE 4
275#define CONFIG_NAND_FSL_ELBC 1
276#define CONFIG_SYS_NAND_BLOCK_SIZE (128 * 1024)
277
278
279#define CONFIG_SYS_NAND_SPL_SIZE 0x1000
280#define CONFIG_SYS_NAND_U_BOOT_SIZE ((768 << 10) - 0x2000)
281#define CONFIG_SYS_NAND_U_BOOT_DST (CONFIG_SYS_INIT_L2_ADDR)
282#define CONFIG_SYS_NAND_U_BOOT_START \
283 (CONFIG_SYS_INIT_L2_ADDR + CONFIG_SYS_NAND_SPL_SIZE)
284#define CONFIG_SYS_NAND_U_BOOT_OFFS (0)
285#define CONFIG_SYS_NAND_U_BOOT_RELOC (CONFIG_SYS_INIT_L2_END - 0x2000)
286#define CONFIG_SYS_NAND_U_BOOT_RELOC_SP ((CONFIG_SYS_INIT_L2_END - 1) & ~0xF)
287
288
289#define CONFIG_SYS_NAND_BR_PRELIM \
290 (BR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS) \
291 | (2<<BR_DECC_SHIFT) \
292 | BR_PS_8 \
293 | BR_MS_FCM \
294 | BR_V)
295#define CONFIG_SYS_NAND_OR_PRELIM (0xFFFC0000 \
296 | OR_FCM_PGS \
297 | OR_FCM_CSCT \
298 | OR_FCM_CST \
299 | OR_FCM_CHT \
300 | OR_FCM_SCY_1 \
301 | OR_FCM_TRLX \
302 | OR_FCM_EHTR)
303
304#define CONFIG_SYS_BR0_PRELIM CONFIG_FLASH_BR_PRELIM
305#define CONFIG_SYS_OR0_PRELIM CONFIG_FLASH_OR_PRELIM
306#define CONFIG_SYS_BR2_PRELIM CONFIG_SYS_NAND_BR_PRELIM
307#define CONFIG_SYS_OR2_PRELIM CONFIG_SYS_NAND_OR_PRELIM
308
309#define CONFIG_SYS_BR4_PRELIM \
310 (BR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS + 0x40000) \
311 | (2<<BR_DECC_SHIFT) \
312 | BR_PS_8 \
313 | BR_MS_FCM \
314 | BR_V)
315#define CONFIG_SYS_OR4_PRELIM CONFIG_SYS_NAND_OR_PRELIM
316#define CONFIG_SYS_BR5_PRELIM \
317 (BR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS + 0x80000) \
318 | (2<<BR_DECC_SHIFT) \
319 | BR_PS_8 \
320 | BR_MS_FCM \
321 | BR_V)
322#define CONFIG_SYS_OR5_PRELIM CONFIG_SYS_NAND_OR_PRELIM
323
324#define CONFIG_SYS_BR6_PRELIM \
325 (BR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS + 0xc0000) \
326 | (2<<BR_DECC_SHIFT) \
327 | BR_PS_8 \
328 | BR_MS_FCM \
329 | BR_V)
330#define CONFIG_SYS_OR6_PRELIM CONFIG_SYS_NAND_OR_PRELIM
331
332
333
334
335
336#define CONFIG_SYS_NS16550_SERIAL
337#define CONFIG_SYS_NS16550_REG_SIZE 1
338#define CONFIG_SYS_NS16550_CLK get_bus_freq(0)
339#ifdef CONFIG_NAND_SPL
340#define CONFIG_NS16550_MIN_FUNCTIONS
341#endif
342
343#define CONFIG_SYS_BAUDRATE_TABLE \
344 {300, 600, 1200, 2400, 4800, 9600, 19200, 38400,115200}
345
346#define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_CCSRBAR + 0x4500)
347#define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_CCSRBAR + 0x4600)
348
349
350
351
352#define CONFIG_SYS_I2C
353#define CONFIG_SYS_I2C_FSL
354#define CONFIG_SYS_FSL_I2C_SPEED 400000
355#define CONFIG_SYS_FSL_I2C_SLAVE 0x7F
356#define CONFIG_SYS_FSL_I2C_OFFSET 0x3000
357#define CONFIG_SYS_FSL_I2C2_SPEED 400000
358#define CONFIG_SYS_FSL_I2C2_SLAVE 0x7F
359#define CONFIG_SYS_FSL_I2C2_OFFSET 0x3100
360#define CONFIG_SYS_I2C_NOPROBES { {0, 0x29} }
361
362
363
364
365#define CONFIG_ID_EEPROM
366#ifdef CONFIG_ID_EEPROM
367#define CONFIG_SYS_I2C_EEPROM_NXID
368#endif
369#define CONFIG_SYS_I2C_EEPROM_ADDR 0x57
370#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1
371#define CONFIG_SYS_EEPROM_BUS_NUM 1
372
373
374
375
376#define CONFIG_HARD_SPI
377
378#if defined(CONFIG_SPI_FLASH)
379#define CONFIG_SF_DEFAULT_SPEED 10000000
380#define CONFIG_SF_DEFAULT_MODE 0
381#endif
382
383
384
385
386
387
388#define CONFIG_SYS_PCI1_MEM_VIRT 0x80000000
389#ifdef CONFIG_PHYS_64BIT
390#define CONFIG_SYS_PCI1_MEM_BUS 0xf0000000
391#define CONFIG_SYS_PCI1_MEM_PHYS 0xc00000000ull
392#else
393#define CONFIG_SYS_PCI1_MEM_BUS 0x80000000
394#define CONFIG_SYS_PCI1_MEM_PHYS 0x80000000
395#endif
396#define CONFIG_SYS_PCI1_MEM_SIZE 0x10000000
397#define CONFIG_SYS_PCI1_IO_VIRT 0xffc00000
398#define CONFIG_SYS_PCI1_IO_BUS 0x00000000
399#ifdef CONFIG_PHYS_64BIT
400#define CONFIG_SYS_PCI1_IO_PHYS 0xfffc00000ull
401#else
402#define CONFIG_SYS_PCI1_IO_PHYS 0xffc00000
403#endif
404#define CONFIG_SYS_PCI1_IO_SIZE 0x00010000
405
406
407#define CONFIG_SYS_PCIE1_NAME "Slot 1"
408#define CONFIG_SYS_PCIE1_MEM_VIRT 0x90000000
409#ifdef CONFIG_PHYS_64BIT
410#define CONFIG_SYS_PCIE1_MEM_BUS 0xf8000000
411#define CONFIG_SYS_PCIE1_MEM_PHYS 0xc10000000ull
412#else
413#define CONFIG_SYS_PCIE1_MEM_BUS 0x90000000
414#define CONFIG_SYS_PCIE1_MEM_PHYS 0x90000000
415#endif
416#define CONFIG_SYS_PCIE1_MEM_SIZE 0x08000000
417#define CONFIG_SYS_PCIE1_IO_VIRT 0xffc10000
418#define CONFIG_SYS_PCIE1_IO_BUS 0x00000000
419#ifdef CONFIG_PHYS_64BIT
420#define CONFIG_SYS_PCIE1_IO_PHYS 0xfffc10000ull
421#else
422#define CONFIG_SYS_PCIE1_IO_PHYS 0xffc10000
423#endif
424#define CONFIG_SYS_PCIE1_IO_SIZE 0x00010000
425
426
427#define CONFIG_SYS_PCIE2_NAME "Slot 2"
428#define CONFIG_SYS_PCIE2_MEM_VIRT 0x98000000
429#ifdef CONFIG_PHYS_64BIT
430#define CONFIG_SYS_PCIE2_MEM_BUS 0xf8000000
431#define CONFIG_SYS_PCIE2_MEM_PHYS 0xc18000000ull
432#else
433#define CONFIG_SYS_PCIE2_MEM_BUS 0x98000000
434#define CONFIG_SYS_PCIE2_MEM_PHYS 0x98000000
435#endif
436#define CONFIG_SYS_PCIE2_MEM_SIZE 0x08000000
437#define CONFIG_SYS_PCIE2_IO_VIRT 0xffc20000
438#define CONFIG_SYS_PCIE2_IO_BUS 0x00000000
439#ifdef CONFIG_PHYS_64BIT
440#define CONFIG_SYS_PCIE2_IO_PHYS 0xfffc20000ull
441#else
442#define CONFIG_SYS_PCIE2_IO_PHYS 0xffc20000
443#endif
444#define CONFIG_SYS_PCIE2_IO_SIZE 0x00010000
445
446
447#define CONFIG_SYS_PCIE3_NAME "Slot 3"
448#define CONFIG_SYS_PCIE3_MEM_VIRT 0xa0000000
449#ifdef CONFIG_PHYS_64BIT
450#define CONFIG_SYS_PCIE3_MEM_BUS 0xe0000000
451#define CONFIG_SYS_PCIE3_MEM_PHYS 0xc20000000ull
452#else
453#define CONFIG_SYS_PCIE3_MEM_BUS 0xa0000000
454#define CONFIG_SYS_PCIE3_MEM_PHYS 0xa0000000
455#endif
456#define CONFIG_SYS_PCIE3_MEM_SIZE 0x20000000
457#define CONFIG_SYS_PCIE3_IO_VIRT 0xffc30000
458#define CONFIG_SYS_PCIE3_IO_BUS 0x00000000
459#ifdef CONFIG_PHYS_64BIT
460#define CONFIG_SYS_PCIE3_IO_PHYS 0xfffc30000ull
461#else
462#define CONFIG_SYS_PCIE3_IO_PHYS 0xffc30000
463#endif
464#define CONFIG_SYS_PCIE3_IO_SIZE 0x00010000
465
466#if defined(CONFIG_PCI)
467
468#define VIDEO_IO_OFFSET CONFIG_SYS_PCIE3_IO_VIRT
469
470
471
472
473
474
475#if defined(CONFIG_VIDEO)
476#define CONFIG_BIOSEMU
477#define CONFIG_ATI_RADEON_FB
478#define CONFIG_VIDEO_LOGO
479#define CONFIG_SYS_ISA_IO_BASE_ADDRESS CONFIG_SYS_PCIE3_IO_VIRT
480#endif
481
482#undef CONFIG_EEPRO100
483#undef CONFIG_TULIP
484
485#ifndef CONFIG_PCI_PNP
486 #define PCI_ENET0_IOADDR CONFIG_SYS_PCI1_IO_BUS
487 #define PCI_ENET0_MEMADDR CONFIG_SYS_PCI1_IO_BUS
488 #define PCI_IDSEL_NUMBER 0x11
489#endif
490
491#define CONFIG_PCI_SCAN_SHOW
492
493#endif
494
495
496#define CONFIG_SYS_SATA_MAX_DEVICE 2
497#define CONFIG_SATA1
498#define CONFIG_SYS_SATA1 CONFIG_SYS_MPC85xx_SATA1_ADDR
499#define CONFIG_SYS_SATA1_FLAGS FLAGS_DMA
500#define CONFIG_SATA2
501#define CONFIG_SYS_SATA2 CONFIG_SYS_MPC85xx_SATA2_ADDR
502#define CONFIG_SYS_SATA2_FLAGS FLAGS_DMA
503
504#ifdef CONFIG_FSL_SATA
505#define CONFIG_LBA48
506#endif
507
508#if defined(CONFIG_TSEC_ENET)
509
510#define CONFIG_MII_DEFAULT_TSEC 1
511#define CONFIG_TSEC1 1
512#define CONFIG_TSEC1_NAME "eTSEC1"
513#define CONFIG_TSEC3 1
514#define CONFIG_TSEC3_NAME "eTSEC3"
515
516#define CONFIG_FSL_SGMII_RISER 1
517#define SGMII_RISER_PHY_OFFSET 0x1c
518
519#define TSEC1_PHY_ADDR 1
520#define TSEC3_PHY_ADDR 0
521
522#define TSEC1_FLAGS (TSEC_GIGABIT | TSEC_REDUCED)
523#define TSEC3_FLAGS (TSEC_GIGABIT | TSEC_REDUCED)
524
525#define TSEC1_PHYIDX 0
526#define TSEC3_PHYIDX 0
527
528#define CONFIG_ETHPRIME "eTSEC1"
529
530#endif
531
532
533
534
535
536#if defined(CONFIG_SYS_RAMBOOT)
537#if defined(CONFIG_RAMBOOT_SPIFLASH)
538#define CONFIG_ENV_SPI_BUS 0
539#define CONFIG_ENV_SPI_CS 0
540#define CONFIG_ENV_SPI_MAX_HZ 10000000
541#define CONFIG_ENV_SPI_MODE 0
542#define CONFIG_ENV_SIZE 0x2000
543#define CONFIG_ENV_OFFSET 0xF0000
544#define CONFIG_ENV_SECT_SIZE 0x10000
545#elif defined(CONFIG_RAMBOOT_SDCARD)
546#define CONFIG_FSL_FIXED_MMC_LOCATION
547#define CONFIG_ENV_SIZE 0x2000
548#define CONFIG_SYS_MMC_ENV_DEV 0
549#else
550 #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - 0x1000)
551 #define CONFIG_ENV_SIZE 0x2000
552#endif
553#else
554 #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - CONFIG_ENV_SECT_SIZE)
555 #define CONFIG_ENV_SIZE 0x2000
556 #define CONFIG_ENV_SECT_SIZE 0x20000
557#endif
558
559#define CONFIG_LOADS_ECHO 1
560#define CONFIG_SYS_LOADS_BAUD_CHANGE 1
561
562#undef CONFIG_WATCHDOG
563
564#ifdef CONFIG_MMC
565#define CONFIG_SYS_FSL_ESDHC_ADDR CONFIG_SYS_MPC85xx_ESDHC_ADDR
566#endif
567
568
569
570
571#define CONFIG_HAS_FSL_MPH_USB
572#ifdef CONFIG_HAS_FSL_MPH_USB
573#ifdef CONFIG_USB_EHCI_HCD
574#define CONFIG_EHCI_HCD_INIT_AFTER_RESET
575#define CONFIG_USB_EHCI_FSL
576#endif
577#endif
578
579
580
581
582#define CONFIG_SYS_LOAD_ADDR 0x2000000
583
584
585
586
587
588
589#define CONFIG_SYS_BOOTMAPSZ (64 << 20)
590#define CONFIG_SYS_BOOTM_LEN (64 << 20)
591
592#if defined(CONFIG_CMD_KGDB)
593#define CONFIG_KGDB_BAUDRATE 230400
594#endif
595
596
597
598
599
600
601#if defined(CONFIG_TSEC_ENET)
602#define CONFIG_HAS_ETH0
603#define CONFIG_HAS_ETH1
604#define CONFIG_HAS_ETH2
605#define CONFIG_HAS_ETH3
606#endif
607
608#define CONFIG_IPADDR 192.168.1.254
609
610#define CONFIG_HOSTNAME "unknown"
611#define CONFIG_ROOTPATH "/opt/nfsroot"
612#define CONFIG_BOOTFILE "uImage"
613#define CONFIG_UBOOTPATH u-boot.bin
614
615#define CONFIG_SERVERIP 192.168.1.1
616#define CONFIG_GATEWAYIP 192.168.1.1
617#define CONFIG_NETMASK 255.255.255.0
618
619
620#define CONFIG_LOADADDR 1000000
621
622#define CONFIG_EXTRA_ENV_SETTINGS \
623"netdev=eth0\0" \
624"uboot=" __stringify(CONFIG_UBOOTPATH) "\0" \
625"tftpflash=tftpboot $loadaddr $uboot; " \
626 "protect off " __stringify(CONFIG_SYS_TEXT_BASE) \
627 " +$filesize; " \
628 "erase " __stringify(CONFIG_SYS_TEXT_BASE) \
629 " +$filesize; " \
630 "cp.b $loadaddr " __stringify(CONFIG_SYS_TEXT_BASE) \
631 " $filesize; " \
632 "protect on " __stringify(CONFIG_SYS_TEXT_BASE) \
633 " +$filesize; " \
634 "cmp.b $loadaddr " __stringify(CONFIG_SYS_TEXT_BASE) \
635 " $filesize\0" \
636"consoledev=ttyS0\0" \
637"ramdiskaddr=2000000\0" \
638"ramdiskfile=8536ds/ramdisk.uboot\0" \
639"fdtaddr=1e00000\0" \
640"fdtfile=8536ds/mpc8536ds.dtb\0" \
641"bdev=sda3\0" \
642"hwconfig=usb1:dr_mode=host,phy_type=ulpi\0"
643
644#define CONFIG_HDBOOT \
645 "setenv bootargs root=/dev/$bdev rw " \
646 "console=$consoledev,$baudrate $othbootargs;" \
647 "tftp $loadaddr $bootfile;" \
648 "tftp $fdtaddr $fdtfile;" \
649 "bootm $loadaddr - $fdtaddr"
650
651#define CONFIG_NFSBOOTCOMMAND \
652 "setenv bootargs root=/dev/nfs rw " \
653 "nfsroot=$serverip:$rootpath " \
654 "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \
655 "console=$consoledev,$baudrate $othbootargs;" \
656 "tftp $loadaddr $bootfile;" \
657 "tftp $fdtaddr $fdtfile;" \
658 "bootm $loadaddr - $fdtaddr"
659
660#define CONFIG_RAMBOOTCOMMAND \
661 "setenv bootargs root=/dev/ram rw " \
662 "console=$consoledev,$baudrate $othbootargs;" \
663 "tftp $ramdiskaddr $ramdiskfile;" \
664 "tftp $loadaddr $bootfile;" \
665 "tftp $fdtaddr $fdtfile;" \
666 "bootm $loadaddr $ramdiskaddr $fdtaddr"
667
668#define CONFIG_BOOTCOMMAND CONFIG_HDBOOT
669
670#endif
671