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10#ifndef __CONFIG_H
11#define __CONFIG_H
12
13
14#define CONFIG_LINUX_RESET_VEC 0x100
15
16
17#define CONFIG_FSL_DIU_FB
18
19#ifdef CONFIG_FSL_DIU_FB
20#define CONFIG_SYS_DIU_ADDR (CONFIG_SYS_CCSRBAR + 0x2c000)
21#define CONFIG_VIDEO_LOGO
22#define CONFIG_VIDEO_BMP_LOGO
23#endif
24
25#ifdef RUN_DIAG
26#define CONFIG_SYS_DIAG_ADDR 0xff800000
27#endif
28
29
30
31
32
33#define CONFIG_SYS_SCRATCH_VA 0xc0000000
34
35#define CONFIG_PCI1 1
36#define CONFIG_PCIE1 1
37#define CONFIG_PCIE2 1
38#define CONFIG_FSL_PCI_INIT 1
39#define CONFIG_PCI_INDIRECT_BRIDGE 1
40#define CONFIG_SYS_PCI_64BIT 1
41
42#define CONFIG_ENV_OVERWRITE
43#define CONFIG_INTERRUPTS
44
45#define CONFIG_BAT_RW 1
46#define CONFIG_HIGH_BATS 1
47#define CONFIG_ALTIVEC 1
48
49
50
51
52#define CONFIG_SYS_L2
53#define L2_INIT 0
54#define L2_ENABLE (L2CR_L2E |0x00100000 )
55
56#ifndef CONFIG_SYS_CLK_FREQ
57#define CONFIG_SYS_CLK_FREQ get_board_sys_clk(0)
58#endif
59
60#define CONFIG_SYS_MEMTEST_START 0x00200000
61#define CONFIG_SYS_MEMTEST_END 0x00400000
62
63
64
65
66
67#define CONFIG_SYS_CCSRBAR 0xe0000000
68#define CONFIG_SYS_IMMR CONFIG_SYS_CCSRBAR
69
70#define CONFIG_SYS_CCSRBAR_PHYS_LOW CONFIG_SYS_CCSRBAR
71#define CONFIG_SYS_CCSRBAR_PHYS_HIGH 0x0
72#define CONFIG_SYS_CCSRBAR_PHYS CONFIG_SYS_CCSRBAR_PHYS_LOW
73
74
75#undef CONFIG_FSL_DDR_INTERACTIVE
76#define CONFIG_SPD_EEPROM
77#define CONFIG_DDR_SPD
78
79#define CONFIG_ECC_INIT_VIA_DDRCONTROLLER
80#define CONFIG_MEM_INIT_VALUE 0xDeadBeef
81
82#define CONFIG_SYS_DDR_SDRAM_BASE 0x00000000
83#define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE
84#define CONFIG_SYS_MAX_DDR_BAT_SIZE 0x80000000
85#define CONFIG_VERY_BIG_RAM
86
87#define CONFIG_DIMM_SLOTS_PER_CTLR 1
88#define CONFIG_CHIP_SELECTS_PER_CTRL (2 * CONFIG_DIMM_SLOTS_PER_CTLR)
89
90#define SPD_EEPROM_ADDRESS 0x51
91
92
93#define CONFIG_SYS_SDRAM_SIZE 256
94
95#if 0
96#define CONFIG_SYS_DDR_CS0_BNDS 0x0000000F
97#define CONFIG_SYS_DDR_CS0_CONFIG 0x80010202
98#define CONFIG_SYS_DDR_TIMING_3 0x00000000
99#define CONFIG_SYS_DDR_TIMING_0 0x00260802
100#define CONFIG_SYS_DDR_TIMING_1 0x3935d322
101#define CONFIG_SYS_DDR_TIMING_2 0x14904cc8
102#define CONFIG_SYS_DDR_MODE_1 0x00480432
103#define CONFIG_SYS_DDR_MODE_2 0x00000000
104#define CONFIG_SYS_DDR_INTERVAL 0x06180100
105#define CONFIG_SYS_DDR_DATA_INIT 0xdeadbeef
106#define CONFIG_SYS_DDR_CLK_CTRL 0x03800000
107#define CONFIG_SYS_DDR_OCD_CTRL 0x00000000
108#define CONFIG_SYS_DDR_OCD_STATUS 0x00000000
109#define CONFIG_SYS_DDR_CONTROL 0xe3008000
110#define CONFIG_SYS_DDR_CONTROL2 0x04400010
111
112#define CONFIG_SYS_DDR_ERR_INT_EN 0x00000000
113#define CONFIG_SYS_DDR_ERR_DIS 0x00000000
114#define CONFIG_SYS_DDR_SBE 0x000f0000
115
116#endif
117
118#define CONFIG_ID_EEPROM
119#define CONFIG_SYS_I2C_EEPROM_NXID
120#define CONFIG_ID_EEPROM
121#define CONFIG_SYS_I2C_EEPROM_ADDR 0x57
122#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1
123
124#define CONFIG_SYS_FLASH_BASE 0xf0000000
125#define CONFIG_SYS_FLASH_BASE2 0xf8000000
126
127#define CONFIG_SYS_FLASH_BANKS_LIST {CONFIG_SYS_FLASH_BASE, CONFIG_SYS_FLASH_BASE2}
128
129#define CONFIG_SYS_BR0_PRELIM 0xf8001001
130#define CONFIG_SYS_OR0_PRELIM 0xf8006e65
131
132#define CONFIG_SYS_BR1_PRELIM 0xf0001001
133#define CONFIG_SYS_OR1_PRELIM 0xf8006e65
134#if 0
135#define CONFIG_SYS_BR2_PRELIM 0xf0000000
136#define CONFIG_SYS_OR2_PRELIM 0xf0000000
137#endif
138#define CONFIG_SYS_BR3_PRELIM 0xe8000801
139#define CONFIG_SYS_OR3_PRELIM 0xfff06ff7
140
141#define CONFIG_FSL_PIXIS 1
142#define PIXIS_BASE 0xe8000000
143#define PIXIS_ID 0x0
144#define PIXIS_VER 0x1
145#define PIXIS_PVER 0x2
146#define PIXIS_RST 0x4
147#define PIXIS_AUX 0x6
148#define PIXIS_SPD 0x7
149#define PIXIS_BRDCFG0 0x8
150#define PIXIS_VCTL 0x10
151#define PIXIS_VCFGEN0 0x12
152#define PIXIS_VCFGEN1 0x13
153#define PIXIS_VBOOT 0x16
154#define PIXIS_VSPEED0 0x17
155#define PIXIS_VSPEED1 0x18
156#define PIXIS_VCLKH 0x19
157#define PIXIS_VCLKL 0x1A
158#define CONFIG_SYS_PIXIS_VBOOT_MASK 0xC0
159
160#define CONFIG_SYS_MAX_FLASH_BANKS 2
161#define CONFIG_SYS_MAX_FLASH_SECT 1024
162
163#undef CONFIG_SYS_FLASH_CHECKSUM
164#define CONFIG_SYS_FLASH_ERASE_TOUT 60000
165#define CONFIG_SYS_FLASH_WRITE_TOUT 500
166#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE
167#define CONFIG_SYS_MONITOR_BASE_EARLY 0xfff00000
168
169#define CONFIG_SYS_FLASH_EMPTY_INFO
170
171#if (CONFIG_SYS_MONITOR_BASE < CONFIG_SYS_FLASH_BASE)
172#define CONFIG_SYS_RAMBOOT
173#else
174#undef CONFIG_SYS_RAMBOOT
175#endif
176
177#if defined(CONFIG_SYS_RAMBOOT)
178#undef CONFIG_SPD_EEPROM
179#define CONFIG_SYS_SDRAM_SIZE 256
180#endif
181
182#undef CONFIG_CLOCKS_IN_MHZ
183
184#define CONFIG_SYS_INIT_RAM_LOCK 1
185#ifndef CONFIG_SYS_INIT_RAM_LOCK
186#define CONFIG_SYS_INIT_RAM_ADDR 0xe4010000
187#else
188#define CONFIG_SYS_INIT_RAM_ADDR 0xe4000000
189#endif
190#define CONFIG_SYS_INIT_RAM_SIZE 0x4000
191
192#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
193#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
194
195#define CONFIG_SYS_MONITOR_LEN (512 * 1024)
196#define CONFIG_SYS_MALLOC_LEN (6 * 1024 * 1024)
197
198
199#define CONFIG_SYS_NS16550_SERIAL
200#define CONFIG_SYS_NS16550_REG_SIZE 1
201#define CONFIG_SYS_NS16550_CLK get_bus_freq(0)
202
203#define CONFIG_SYS_BAUDRATE_TABLE \
204 {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 115200}
205
206#define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_CCSRBAR+0x4500)
207#define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_CCSRBAR+0x4600)
208
209
210#define OF_FLAT_TREE_MAX_SIZE 8192
211
212
213
214
215#define CONFIG_SYS_I2C
216#define CONFIG_SYS_I2C_FSL
217#define CONFIG_SYS_FSL_I2C_SPEED 400000
218#define CONFIG_SYS_FSL_I2C_SLAVE 0x7F
219#define CONFIG_SYS_FSL_I2C_OFFSET 0x3000
220#define CONFIG_SYS_I2C_NOPROBES { {0, 0x69} }
221
222
223
224
225
226#define CONFIG_SYS_PCI1_MEM_BUS 0x80000000
227#define CONFIG_SYS_PCI1_MEM_PHYS CONFIG_SYS_PCI1_MEM_BUS
228#define CONFIG_SYS_PCI1_MEM_VIRT CONFIG_SYS_PCI1_MEM_BUS
229#define CONFIG_SYS_PCI1_MEM_SIZE 0x10000000
230#define CONFIG_SYS_PCI1_IO_BUS 0x0000000
231#define CONFIG_SYS_PCI1_IO_PHYS 0xe1000000
232#define CONFIG_SYS_PCI1_IO_VIRT 0xe1000000
233#define CONFIG_SYS_PCI1_IO_SIZE 0x00100000
234
235
236#define CONFIG_SYS_PCIE1_NAME "ULI"
237#define CONFIG_SYS_PCIE1_MEM_BUS 0xa0000000
238#define CONFIG_SYS_PCIE1_MEM_PHYS CONFIG_SYS_PCIE1_MEM_BUS
239#define CONFIG_SYS_PCIE1_MEM_SIZE 0x10000000
240#define CONFIG_SYS_PCIE1_IO_BUS 0x00000000
241#define CONFIG_SYS_PCIE1_IO_PHYS 0xe3000000
242#define CONFIG_SYS_PCIE1_IO_SIZE 0x00100000
243
244
245#define CONFIG_SYS_PCIE2_NAME "Slot 1"
246#define CONFIG_SYS_PCIE2_MEM_BUS 0x90000000
247#define CONFIG_SYS_PCIE2_MEM_PHYS CONFIG_SYS_PCIE2_MEM_BUS
248#define CONFIG_SYS_PCIE2_MEM_SIZE 0x10000000
249#define CONFIG_SYS_PCIE2_IO_BUS 0x00000000
250#define CONFIG_SYS_PCIE2_IO_PHYS 0xe2000000
251#define CONFIG_SYS_PCIE2_IO_SIZE 0x00100000
252
253#if defined(CONFIG_PCI)
254
255#define CONFIG_PCI_SCAN_SHOW
256
257#define CONFIG_ULI526X
258
259
260
261
262#define CONFIG_PCI_OHCI 1
263#define CONFIG_USB_OHCI_NEW 1
264#define CONFIG_SYS_USB_OHCI_SLOT_NAME "ohci_pci"
265#define CONFIG_SYS_USB_OHCI_MAX_ROOT_PORTS 15
266#define CONFIG_SYS_OHCI_SWAP_REG_ACCESS 1
267
268#if !defined(CONFIG_PCI_PNP)
269#define PCI_ENET0_IOADDR 0xe0000000
270#define PCI_ENET0_MEMADDR 0xe0000000
271#define PCI_IDSEL_NUMBER 0x0c
272#endif
273
274#ifdef CONFIG_SCSI_AHCI
275#define CONFIG_SATA_ULI5288
276#define CONFIG_SYS_SCSI_MAX_SCSI_ID 4
277#define CONFIG_SYS_SCSI_MAX_LUN 1
278#define CONFIG_SYS_SCSI_MAX_DEVICE (CONFIG_SYS_SCSI_MAX_SCSI_ID * CONFIG_SYS_SCSI_MAX_LUN)
279#endif
280
281#endif
282
283
284
285
286
287#define CONFIG_SYS_DBAT0L (BATL_PP_RW)
288#define CONFIG_SYS_IBAT0L (BATL_PP_RW)
289
290
291
292
293
294
295
296
297#define CONFIG_SYS_DBAT1L (CONFIG_SYS_PCI1_MEM_PHYS | BATL_PP_RW | BATL_CACHEINHIBIT \
298 | BATL_GUARDEDSTORAGE)
299#define CONFIG_SYS_DBAT1U (CONFIG_SYS_PCI1_MEM_VIRT | BATU_BL_1G | BATU_VS | BATU_VP)
300#define CONFIG_SYS_IBAT1L (CONFIG_SYS_PCI1_MEM_PHYS | BATL_PP_RW | BATL_CACHEINHIBIT)
301#define CONFIG_SYS_IBAT1U CONFIG_SYS_DBAT1U
302
303
304
305
306
307
308#define CONFIG_SYS_DBAT2L (CONFIG_SYS_PCI1_IO_PHYS | BATL_PP_RW | BATL_CACHEINHIBIT \
309 | BATL_GUARDEDSTORAGE)
310#define CONFIG_SYS_DBAT2U (CONFIG_SYS_PCI1_IO_VIRT | BATU_BL_16M | BATU_VS | BATU_VP)
311#define CONFIG_SYS_IBAT2L (CONFIG_SYS_PCI1_IO_PHYS | BATL_PP_RW | BATL_CACHEINHIBIT)
312#define CONFIG_SYS_IBAT2U CONFIG_SYS_DBAT2U
313
314
315
316
317
318
319#define CONFIG_SYS_DBAT3L (CONFIG_SYS_CCSRBAR | BATL_PP_RW | BATL_CACHEINHIBIT \
320 | BATL_GUARDEDSTORAGE)
321#define CONFIG_SYS_DBAT3U (CONFIG_SYS_CCSRBAR | BATU_BL_1M | BATU_VS | BATU_VP)
322#define CONFIG_SYS_IBAT3L (CONFIG_SYS_CCSRBAR | BATL_PP_RW | BATL_CACHEINHIBIT)
323#define CONFIG_SYS_IBAT3U CONFIG_SYS_DBAT3U
324
325#if (CONFIG_SYS_CCSRBAR_DEFAULT != CONFIG_SYS_CCSRBAR)
326#define CONFIG_SYS_CCSR_DEFAULT_DBATL (CONFIG_SYS_CCSRBAR_DEFAULT \
327 | BATL_PP_RW | BATL_CACHEINHIBIT \
328 | BATL_GUARDEDSTORAGE)
329#define CONFIG_SYS_CCSR_DEFAULT_DBATU (CONFIG_SYS_CCSRBAR_DEFAULT \
330 | BATU_BL_1M | BATU_VS | BATU_VP)
331#define CONFIG_SYS_CCSR_DEFAULT_IBATL (CONFIG_SYS_CCSRBAR_DEFAULT \
332 | BATL_PP_RW | BATL_CACHEINHIBIT)
333#define CONFIG_SYS_CCSR_DEFAULT_IBATU CONFIG_SYS_CCSR_DEFAULT_DBATU
334#endif
335
336
337
338
339
340
341
342#define CONFIG_SYS_DBAT4L (CONFIG_SYS_PCIE2_IO_PHYS | BATL_PP_RW | BATL_CACHEINHIBIT \
343 | BATL_GUARDEDSTORAGE)
344#define CONFIG_SYS_DBAT4U (CONFIG_SYS_PCIE2_IO_PHYS | BATU_BL_32M | BATU_VS | BATU_VP)
345#define CONFIG_SYS_IBAT4L (CONFIG_SYS_PCIE2_IO_PHYS | BATL_PP_RW | BATL_CACHEINHIBIT)
346#define CONFIG_SYS_IBAT4U CONFIG_SYS_DBAT4U
347
348
349
350
351
352#define CONFIG_SYS_DBAT5L (CONFIG_SYS_INIT_RAM_ADDR | BATL_PP_RW | BATL_MEMCOHERENCE)
353#define CONFIG_SYS_DBAT5U (CONFIG_SYS_INIT_RAM_ADDR | BATU_BL_128K | BATU_VS | BATU_VP)
354#define CONFIG_SYS_IBAT5L CONFIG_SYS_DBAT5L
355#define CONFIG_SYS_IBAT5U CONFIG_SYS_DBAT5U
356
357
358
359
360
361#define CONFIG_SYS_DBAT6L (CONFIG_SYS_FLASH_BASE | BATL_PP_RW | BATL_CACHEINHIBIT \
362 | BATL_GUARDEDSTORAGE)
363#define CONFIG_SYS_DBAT6U (CONFIG_SYS_FLASH_BASE | BATU_BL_256M | BATU_VS | BATU_VP)
364#define CONFIG_SYS_IBAT6L (CONFIG_SYS_FLASH_BASE | BATL_PP_RW | BATL_MEMCOHERENCE)
365#define CONFIG_SYS_IBAT6U CONFIG_SYS_DBAT6U
366
367
368#define CONFIG_SYS_DBAT6L_EARLY (CONFIG_SYS_MONITOR_BASE_EARLY | BATL_PP_RW \
369 | BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE)
370#define CONFIG_SYS_DBAT6U_EARLY (CONFIG_SYS_TEXT_BASE | BATU_BL_1M | BATU_VS | BATU_VP)
371#define CONFIG_SYS_IBAT6L_EARLY (CONFIG_SYS_MONITOR_BASE_EARLY | BATL_PP_RW \
372 | BATL_MEMCOHERENCE)
373#define CONFIG_SYS_IBAT6U_EARLY CONFIG_SYS_DBAT6U_EARLY
374
375
376
377
378
379#define CONFIG_SYS_DBAT7L (PIXIS_BASE | BATL_PP_RW | BATL_CACHEINHIBIT \
380 | BATL_GUARDEDSTORAGE)
381#define CONFIG_SYS_DBAT7U (PIXIS_BASE | BATU_BL_1M | BATU_VS | BATU_VP)
382#define CONFIG_SYS_IBAT7L (PIXIS_BASE | BATL_PP_RW | BATL_CACHEINHIBIT)
383#define CONFIG_SYS_IBAT7U CONFIG_SYS_DBAT7U
384
385
386
387
388#ifndef CONFIG_SYS_RAMBOOT
389#define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE + CONFIG_SYS_MONITOR_LEN)
390#define CONFIG_ENV_SECT_SIZE 0x20000
391#define CONFIG_ENV_SIZE 0x2000
392#else
393#define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - 0x1000)
394#define CONFIG_ENV_SIZE 0x2000
395#endif
396
397#define CONFIG_LOADS_ECHO 1
398#define CONFIG_SYS_LOADS_BAUD_CHANGE 1
399
400
401
402
403#define CONFIG_BOOTP_BOOTFILESIZE
404
405
406
407
408
409#define CONFIG_WATCHDOG
410#define CONFIG_SYS_WATCHDOG_FREQ 5000
411
412
413
414
415#define CONFIG_SYS_LOAD_ADDR 0x2000000
416
417
418
419
420
421
422#define CONFIG_SYS_BOOTMAPSZ (256 << 20)
423#define CONFIG_SYS_BOOTM_LEN (256 << 20)
424
425#if defined(CONFIG_CMD_KGDB)
426#define CONFIG_KGDB_BAUDRATE 230400
427#endif
428
429
430
431
432#define CONFIG_IPADDR 192.168.1.100
433
434#define CONFIG_HOSTNAME "unknown"
435#define CONFIG_ROOTPATH "/opt/nfsroot"
436#define CONFIG_BOOTFILE "uImage"
437#define CONFIG_UBOOTPATH 8610hpcd/u-boot.bin
438
439#define CONFIG_SERVERIP 192.168.1.1
440#define CONFIG_GATEWAYIP 192.168.1.1
441#define CONFIG_NETMASK 255.255.255.0
442
443
444#define CONFIG_LOADADDR 0x10000000
445
446#if defined(CONFIG_PCI1)
447#define PCI_ENV \
448 "pcireg=md ${a}000 3; echo o;md ${a}c00 25; echo i; md ${a}da0 15;" \
449 "echo e;md ${a}e00 9\0" \
450 "pci1regs=setenv a e0008; run pcireg\0" \
451 "pcierr=md ${a}e00 8; pci d.b $b.0 7 1; pci d.w $b.0 1e 1;" \
452 "pci d.w $b.0 56 1\0" \
453 "pcierrc=mw ${a}e00 ffffffff; pci w.b $b.0 7 ff; pci w.w $b.0 1e ffff;" \
454 "pci w.w $b.0 56 ffff\0" \
455 "pci1err=setenv a e0008; run pcierr\0" \
456 "pci1errc=setenv a e0008; run pcierrc\0"
457#else
458#define PCI_ENV ""
459#endif
460
461#if defined(CONFIG_PCIE1) || defined(CONFIG_PCIE2)
462#define PCIE_ENV \
463 "pciereg=md ${a}000 6; md ${a}020 4; md ${a}bf8 2; echo o;md ${a}c00 25;" \
464 "echo i; md ${a}da0 15; echo e;md ${a}e00 e; echo d; md ${a}f00 c\0" \
465 "pcie1regs=setenv a e000a; run pciereg\0" \
466 "pcie2regs=setenv a e0009; run pciereg\0" \
467 "pcieerr=md ${a}020 1; md ${a}e00; pci d.b $b.0 7 1; pci d.w $b.0 1e 1;"\
468 "pci d.w $b.0 56 1; pci d $b.0 104 1; pci d $b.0 110 1;" \
469 "pci d $b.0 130 1\0" \
470 "pcieerrc=mw ${a}020 ffffffff; mw ${a}e00 ffffffff; pci w.b $b.0 7 ff;"\
471 "pci w.w $b.0 1e ffff; pci w.w $b.0 56 ffff; pci w $b.0 104 ffffffff;" \
472 "pci w $b.0 110 ffffffff; pci w $b.0 130 ffffffff\0" \
473 "pciecfg=pci d $b.0 0 20; pci d $b.0 100 e; pci d $b.0 400 69\0" \
474 "pcie1err=setenv a e000a; run pcieerr\0" \
475 "pcie2err=setenv a e0009; run pcieerr\0" \
476 "pcie1errc=setenv a e000a; run pcieerrc\0" \
477 "pcie2errc=setenv a e0009; run pcieerrc\0"
478#else
479#define PCIE_ENV ""
480#endif
481
482#define DMA_ENV \
483 "dma0=mw ${d}104 ffffffff;mw ${d}110 50000;mw ${d}114 $sad0;mw ${d}118 50000;"\
484 "mw ${d}120 $bc0;mw ${d}100 f03c404; mw ${d}11c $dad0; md ${d}100 9\0" \
485 "dma1=mw ${d}184 ffffffff;mw ${d}190 50000;mw ${d}194 $sad1;mw ${d}198 50000;"\
486 "mw ${d}1a0 $bc1;mw ${d}180 f03c404; mw ${d}19c $dad1; md ${d}180 9\0" \
487 "dma2=mw ${d}204 ffffffff;mw ${d}210 50000;mw ${d}214 $sad2;mw ${d}218 50000;"\
488 "mw ${d}220 $bc2;mw ${d}200 f03c404; mw ${d}21c $dad2; md ${d}200 9\0" \
489 "dma3=mw ${d}284 ffffffff;mw ${d}290 50000;mw ${d}294 $sad3;mw ${d}298 50000;"\
490 "mw ${d}2a0 $bc3;mw ${d}280 f03c404; mw ${d}29c $dad3; md ${d}280 9\0"
491
492#ifdef ENV_DEBUG
493#define CONFIG_EXTRA_ENV_SETTINGS \
494"netdev=eth0\0" \
495"uboot=" __stringify(CONFIG_UBOOTPATH) "\0" \
496"tftpflash=tftpboot $loadaddr $uboot; " \
497 "protect off " __stringify(CONFIG_SYS_TEXT_BASE) \
498 " +$filesize; " \
499 "erase " __stringify(CONFIG_SYS_TEXT_BASE) \
500 " +$filesize; " \
501 "cp.b $loadaddr " __stringify(CONFIG_SYS_TEXT_BASE) \
502 " $filesize; " \
503 "protect on " __stringify(CONFIG_SYS_TEXT_BASE) \
504 " +$filesize; " \
505 "cmp.b $loadaddr " __stringify(CONFIG_SYS_TEXT_BASE) \
506 " $filesize\0" \
507"consoledev=ttyS0\0" \
508"ramdiskaddr=0x18000000\0" \
509"ramdiskfile=8610hpcd/ramdisk.uboot\0" \
510"fdtaddr=0x17c00000\0" \
511"fdtfile=8610hpcd/mpc8610_hpcd.dtb\0" \
512"bdev=sda3\0" \
513"en-wd=mw.b f8100010 0x08; echo -expect:- 08; md.b f8100010 1\0" \
514"dis-wd=mw.b f8100010 0x00; echo -expect:- 00; md.b f8100010 1\0" \
515"maxcpus=1" \
516"eoi=mw e00400b0 0\0" \
517"iack=md e00400a0 1\0" \
518"ddrreg=md ${a}000 8; md ${a}080 8;md ${a}100 d; md ${a}140 4;" \
519 "md ${a}bf0 4; md ${a}e00 3; md ${a}e20 3; md ${a}e40 7;" \
520 "md ${a}f00 5\0" \
521"ddr1regs=setenv a e0002; run ddrreg\0" \
522"gureg=md ${a}000 2c; md ${a}0b0 1; md ${a}0c0 1; md ${a}800 1;" \
523 "md ${a}900 6; md ${a}a00 1; md ${a}b20 3; md ${a}e00 1;" \
524 "md ${a}e60 1; md ${a}ef0 1d\0" \
525"guregs=setenv a e00e0; run gureg\0" \
526"mcmreg=md ${a}000 1b; md ${a}bf8 2; md ${a}e00 5\0" \
527"mcmregs=setenv a e0001; run mcmreg\0" \
528"diuregs=md e002c000 1d\0" \
529"dium=mw e002c01c\0" \
530"diuerr=md e002c014 1\0" \
531"pmregs=md e00e1000 2b\0" \
532"lawregs=md e0000c08 4b\0" \
533"lbcregs=md e0005000 36\0" \
534"dma0regs=md e0021100 12\0" \
535"dma1regs=md e0021180 12\0" \
536"dma2regs=md e0021200 12\0" \
537"dma3regs=md e0021280 12\0" \
538 PCI_ENV \
539 PCIE_ENV \
540 DMA_ENV
541#else
542#define CONFIG_EXTRA_ENV_SETTINGS \
543 "netdev=eth0\0" \
544 "uboot=" __stringify(CONFIG_UBOOTPATH) "\0" \
545 "consoledev=ttyS0\0" \
546 "ramdiskaddr=0x18000000\0" \
547 "ramdiskfile=8610hpcd/ramdisk.uboot\0" \
548 "fdtaddr=0x17c00000\0" \
549 "fdtfile=8610hpcd/mpc8610_hpcd.dtb\0" \
550 "bdev=sda3\0"
551#endif
552
553#define CONFIG_NFSBOOTCOMMAND \
554 "setenv bootargs root=/dev/nfs rw " \
555 "nfsroot=$serverip:$rootpath " \
556 "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \
557 "console=$consoledev,$baudrate $othbootargs;" \
558 "tftp $loadaddr $bootfile;" \
559 "tftp $fdtaddr $fdtfile;" \
560 "bootm $loadaddr - $fdtaddr"
561
562#define CONFIG_RAMBOOTCOMMAND \
563 "setenv bootargs root=/dev/ram rw " \
564 "console=$consoledev,$baudrate $othbootargs;" \
565 "tftp $ramdiskaddr $ramdiskfile;" \
566 "tftp $loadaddr $bootfile;" \
567 "tftp $fdtaddr $fdtfile;" \
568 "bootm $loadaddr $ramdiskaddr $fdtaddr"
569
570#define CONFIG_BOOTCOMMAND \
571 "setenv bootargs root=/dev/$bdev rw " \
572 "console=$consoledev,$baudrate $othbootargs;" \
573 "tftp $loadaddr $bootfile;" \
574 "tftp $fdtaddr $fdtfile;" \
575 "bootm $loadaddr - $fdtaddr"
576
577#endif
578