LXR uboot/include/configs/T4240QDS.h

   1/* SPDX-License-Identifier: GPL-2.0+ */
   2/*
   3 * Copyright 2011-2012 Freescale Semiconductor, Inc.
   4 */
   5
   6/*
   7 * T4240 QDS board configuration file
   8 */
   9#ifndef __CONFIG_H
  10#define __CONFIG_H
  11
  12#define CONFIG_FSL_SATA_V2
  13#define CONFIG_PCIE4
  14
  15#define CONFIG_ICS307_REFCLK_HZ         25000000  /* ICS307 ref clk freq */
  16
  17#ifdef CONFIG_RAMBOOT_PBL
  18#define CONFIG_SYS_FSL_PBL_PBI board/freescale/t4qds/t4_pbi.cfg
  19#if !defined(CONFIG_NAND) && !defined(CONFIG_SDCARD)
  20#define CONFIG_RAMBOOT_TEXT_BASE        CONFIG_SYS_TEXT_BASE
  21#define CONFIG_RESET_VECTOR_ADDRESS     0xfffffffc
  22#else
  23#define CONFIG_SPL_FLUSH_IMAGE
  24#define CONFIG_SPL_TEXT_BASE            0xFFFD8000
  25#define CONFIG_SPL_PAD_TO               0x40000
  26#define CONFIG_SPL_MAX_SIZE             0x28000
  27#define RESET_VECTOR_OFFSET             0x27FFC
  28#define BOOT_PAGE_OFFSET                0x27000
  29
  30#ifdef  CONFIG_NAND
  31#define CONFIG_SYS_NAND_U_BOOT_SIZE     (768 << 10)
  32#define CONFIG_SYS_NAND_U_BOOT_DST      0x00200000
  33#define CONFIG_SYS_NAND_U_BOOT_START    0x00200000
  34#define CONFIG_SYS_NAND_U_BOOT_OFFS     (256 << 10)
  35#define CONFIG_SYS_LDSCRIPT     "arch/powerpc/cpu/mpc85xx/u-boot-nand.lds"
  36#define CONFIG_SYS_FSL_PBL_RCW board/freescale/t4qds/t4_nand_rcw.cfg
  37#define CONFIG_SPL_NAND_BOOT
  38#endif
  39
  40#ifdef  CONFIG_SDCARD
  41#define CONFIG_RESET_VECTOR_ADDRESS     0x200FFC
  42#define CONFIG_SYS_MMC_U_BOOT_SIZE      (768 << 10)
  43#define CONFIG_SYS_MMC_U_BOOT_DST       0x00200000
  44#define CONFIG_SYS_MMC_U_BOOT_START     0x00200000
  45#define CONFIG_SYS_MMC_U_BOOT_OFFS      (260 << 10)
  46#ifndef CONFIG_SPL_BUILD
  47#define CONFIG_SYS_MPC85XX_NO_RESETVEC
  48#endif
  49#define CONFIG_SYS_LDSCRIPT     "arch/powerpc/cpu/mpc85xx/u-boot.lds"
  50#define CONFIG_SYS_FSL_PBL_RCW board/freescale/t4qds/t4_sd_rcw.cfg
  51#define CONFIG_SPL_MMC_BOOT
  52#endif
  53
  54#ifdef CONFIG_SPL_BUILD
  55#define CONFIG_SPL_SKIP_RELOCATE
  56#define CONFIG_SPL_COMMON_INIT_DDR
  57#define CONFIG_SYS_CCSR_DO_NOT_RELOCATE
  58#endif
  59
  60#endif
  61#endif /* CONFIG_RAMBOOT_PBL */
  62
  63#ifdef CONFIG_SRIO_PCIE_BOOT_SLAVE
  64/* Set 1M boot space */
  65#define CONFIG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR (CONFIG_SYS_TEXT_BASE & 0xfff00000)
  66#define CONFIG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR_PHYS \
  67                (0x300000000ull | CONFIG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR)
  68#define CONFIG_RESET_VECTOR_ADDRESS 0xfffffffc
  69#endif
  70
  71#define CONFIG_SRIO_PCIE_BOOT_MASTER
  72#define CONFIG_DDR_ECC
  73
  74#include "t4qds.h"
  75
  76#if defined(CONFIG_SPIFLASH)
  77#define CONFIG_ENV_SPI_BUS              0
  78#define CONFIG_ENV_SPI_CS               0
  79#define CONFIG_ENV_SPI_MAX_HZ           10000000
  80#define CONFIG_ENV_SPI_MODE             0
  81#define CONFIG_ENV_SIZE                 0x2000          /* 8KB */
  82#define CONFIG_ENV_OFFSET               0x100000        /* 1MB */
  83#define CONFIG_ENV_SECT_SIZE            0x10000
  84#elif defined(CONFIG_SDCARD)
  85#define CONFIG_SYS_MMC_ENV_DEV          0
  86#define CONFIG_ENV_SIZE                 0x2000
  87#define CONFIG_ENV_OFFSET               (512 * 0x800)
  88#elif defined(CONFIG_NAND)
  89#define CONFIG_ENV_SIZE                 0x2000
  90#define CONFIG_ENV_OFFSET               (10 * CONFIG_SYS_NAND_BLOCK_SIZE)
  91#elif defined(CONFIG_SRIO_PCIE_BOOT_SLAVE)
  92#define CONFIG_ENV_ADDR         0xffe20000
  93#define CONFIG_ENV_SIZE         0x2000
  94#elif defined(CONFIG_ENV_IS_NOWHERE)
  95#define CONFIG_ENV_SIZE         0x2000
  96#else
  97#define CONFIG_ENV_ADDR         (CONFIG_SYS_MONITOR_BASE - CONFIG_ENV_SECT_SIZE)
  98#define CONFIG_ENV_SIZE         0x2000
  99#define CONFIG_ENV_SECT_SIZE    0x20000 /* 128K (one sector) */
 100#endif
 101
 102#define CONFIG_SYS_CLK_FREQ     get_board_sys_clk()
 103#define CONFIG_DDR_CLK_FREQ     get_board_ddr_clk()
 104
 105#ifndef __ASSEMBLY__
 106unsigned long get_board_sys_clk(void);
 107unsigned long get_board_ddr_clk(void);
 108#endif
 109
 110/* EEPROM */
 111#define CONFIG_ID_EEPROM
 112#define CONFIG_SYS_I2C_EEPROM_NXID
 113#define CONFIG_SYS_EEPROM_BUS_NUM       0
 114#define CONFIG_SYS_I2C_EEPROM_ADDR      0x57
 115#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN  1
 116
 117/*
 118 * DDR Setup
 119 */
 120#define CONFIG_SYS_SPD_BUS_NUM  0
 121#define SPD_EEPROM_ADDRESS1     0x51
 122#define SPD_EEPROM_ADDRESS2     0x52
 123#define SPD_EEPROM_ADDRESS3     0x53
 124#define SPD_EEPROM_ADDRESS4     0x54
 125#define SPD_EEPROM_ADDRESS5     0x55
 126#define SPD_EEPROM_ADDRESS6     0x56
 127#define SPD_EEPROM_ADDRESS      SPD_EEPROM_ADDRESS1     /* for p3041/p5010 */
 128#define CONFIG_SYS_SDRAM_SIZE   4096    /* for fixed parameter use */
 129
 130/*
 131 * IFC Definitions
 132 */
 133#define CONFIG_SYS_NOR0_CSPR_EXT        (0xf)
 134#define CONFIG_SYS_NOR0_CSPR    (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS \
 135                                + 0x8000000) | \
 136                                CSPR_PORT_SIZE_16 | \
 137                                CSPR_MSEL_NOR | \
 138                                CSPR_V)
 139#define CONFIG_SYS_NOR1_CSPR_EXT        (0xf)
 140#define CONFIG_SYS_NOR1_CSPR    (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS) | \
 141                                CSPR_PORT_SIZE_16 | \
 142                                CSPR_MSEL_NOR | \
 143                                CSPR_V)
 144#define CONFIG_SYS_NOR_AMASK    IFC_AMASK(128*1024*1024)
 145/* NOR Flash Timing Params */
 146#define CONFIG_SYS_NOR_CSOR     CSOR_NAND_TRHZ_80
 147
 148#define CONFIG_SYS_NOR_FTIM0    (FTIM0_NOR_TACSE(0x4) | \
 149                                FTIM0_NOR_TEADC(0x5) | \
 150                                FTIM0_NOR_TEAHC(0x5))
 151#define CONFIG_SYS_NOR_FTIM1    (FTIM1_NOR_TACO(0x35) | \
 152                                FTIM1_NOR_TRAD_NOR(0x1A) |\
 153                                FTIM1_NOR_TSEQRAD_NOR(0x13))
 154#define CONFIG_SYS_NOR_FTIM2    (FTIM2_NOR_TCS(0x4) | \
 155                                FTIM2_NOR_TCH(0x4) | \
 156                                FTIM2_NOR_TWPH(0x0E) | \
 157                                FTIM2_NOR_TWP(0x1c))
 158#define CONFIG_SYS_NOR_FTIM3    0x0
 159
 160#define CONFIG_SYS_FLASH_QUIET_TEST
 161#define CONFIG_FLASH_SHOW_PROGRESS      45 /* count down from 45/5: 9..1 */
 162
 163#define CONFIG_SYS_MAX_FLASH_BANKS      2       /* number of banks */
 164#define CONFIG_SYS_MAX_FLASH_SECT       1024    /* sectors per device */
 165#define CONFIG_SYS_FLASH_ERASE_TOUT     60000   /* Flash Erase Timeout (ms) */
 166#define CONFIG_SYS_FLASH_WRITE_TOUT     500     /* Flash Write Timeout (ms) */
 167
 168#define CONFIG_SYS_FLASH_EMPTY_INFO
 169#define CONFIG_SYS_FLASH_BANKS_LIST     {CONFIG_SYS_FLASH_BASE_PHYS \
 170                                        + 0x8000000, CONFIG_SYS_FLASH_BASE_PHYS}
 171
 172#define CONFIG_FSL_QIXIS        /* use common QIXIS code */
 173#define QIXIS_BASE                      0xffdf0000
 174#define QIXIS_LBMAP_SWITCH              6
 175#define QIXIS_LBMAP_MASK                0x0f
 176#define QIXIS_LBMAP_SHIFT               0
 177#define QIXIS_LBMAP_DFLTBANK            0x00
 178#define QIXIS_LBMAP_ALTBANK             0x04
 179#define QIXIS_RST_CTL_RESET             0x83
 180#define QIXIS_RST_FORCE_MEM             0x1
 181#define QIXIS_RCFG_CTL_RECONFIG_IDLE    0x20
 182#define QIXIS_RCFG_CTL_RECONFIG_START   0x21
 183#define QIXIS_RCFG_CTL_WATCHDOG_ENBLE   0x08
 184#define QIXIS_BRDCFG5                   0x55
 185#define QIXIS_MUX_SDHC                  2
 186#define QIXIS_MUX_SDHC_WIDTH8           1
 187#define QIXIS_BASE_PHYS         (0xf00000000ull | QIXIS_BASE)
 188
 189#define CONFIG_SYS_CSPR3_EXT    (0xf)
 190#define CONFIG_SYS_CSPR3        (CSPR_PHYS_ADDR(QIXIS_BASE_PHYS) \
 191                                | CSPR_PORT_SIZE_8 \
 192                                | CSPR_MSEL_GPCM \
 193                                | CSPR_V)
 194#define CONFIG_SYS_AMASK3       IFC_AMASK(4*1024)
 195#define CONFIG_SYS_CSOR3        0x0
 196/* QIXIS Timing parameters for IFC CS3 */
 197#define CONFIG_SYS_CS3_FTIM0            (FTIM0_GPCM_TACSE(0x0e) | \
 198                                        FTIM0_GPCM_TEADC(0x0e) | \
 199                                        FTIM0_GPCM_TEAHC(0x0e))
 200#define CONFIG_SYS_CS3_FTIM1            (FTIM1_GPCM_TACO(0xff) | \
 201                                        FTIM1_GPCM_TRAD(0x3f))
 202#define CONFIG_SYS_CS3_FTIM2            (FTIM2_GPCM_TCS(0x0e) | \
 203                                        FTIM2_GPCM_TCH(0x8) | \
 204                                        FTIM2_GPCM_TWP(0x1f))
 205#define CONFIG_SYS_CS3_FTIM3            0x0
 206
 207/* NAND Flash on IFC */
 208#define CONFIG_NAND_FSL_IFC
 209#define CONFIG_SYS_NAND_BASE            0xff800000
 210#define CONFIG_SYS_NAND_BASE_PHYS       (0xf00000000ull | CONFIG_SYS_NAND_BASE)
 211
 212#define CONFIG_SYS_NAND_CSPR_EXT        (0xf)
 213#define CONFIG_SYS_NAND_CSPR    (CSPR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS) \
 214                                | CSPR_PORT_SIZE_8 /* Port Size = 8 bit */ \
 215                                | CSPR_MSEL_NAND        /* MSEL = NAND */ \
 216                                | CSPR_V)
 217#define CONFIG_SYS_NAND_AMASK   IFC_AMASK(64*1024)
 218
 219#define CONFIG_SYS_NAND_CSOR    (CSOR_NAND_ECC_ENC_EN   /* ECC on encode */ \
 220                                | CSOR_NAND_ECC_DEC_EN  /* ECC on decode */ \
 221                                | CSOR_NAND_ECC_MODE_4  /* 4-bit ECC */ \
 222                                | CSOR_NAND_RAL_3       /* RAL = 2Byes */ \
 223                                | CSOR_NAND_PGS_2K      /* Page Size = 2K */ \
 224                                | CSOR_NAND_SPRZ_64/* Spare size = 64 */ \
 225                                | CSOR_NAND_PB(64))     /*Pages Per Block = 64*/
 226
 227#define CONFIG_SYS_NAND_ONFI_DETECTION
 228
 229/* ONFI NAND Flash mode0 Timing Params */
 230#define CONFIG_SYS_NAND_FTIM0           (FTIM0_NAND_TCCST(0x07) | \
 231                                        FTIM0_NAND_TWP(0x18)   | \
 232                                        FTIM0_NAND_TWCHT(0x07) | \
 233                                        FTIM0_NAND_TWH(0x0a))
 234#define CONFIG_SYS_NAND_FTIM1           (FTIM1_NAND_TADLE(0x32) | \
 235                                        FTIM1_NAND_TWBE(0x39)  | \
 236                                        FTIM1_NAND_TRR(0x0e)   | \
 237                                        FTIM1_NAND_TRP(0x18))
 238#define CONFIG_SYS_NAND_FTIM2           (FTIM2_NAND_TRAD(0x0f) | \
 239                                        FTIM2_NAND_TREH(0x0a) | \
 240                                        FTIM2_NAND_TWHRE(0x1e))
 241#define CONFIG_SYS_NAND_FTIM3           0x0
 242
 243#define CONFIG_SYS_NAND_DDR_LAW         11
 244
 245#define CONFIG_SYS_NAND_BASE_LIST       { CONFIG_SYS_NAND_BASE }
 246#define CONFIG_SYS_MAX_NAND_DEVICE      1
 247
 248#define CONFIG_SYS_NAND_BLOCK_SIZE      (128 * 1024)
 249#define CONFIG_SYS_NAND_MAX_OOBFREE     2
 250#define CONFIG_SYS_NAND_MAX_ECCPOS      256
 251
 252#if defined(CONFIG_NAND)
 253#define CONFIG_SYS_CSPR0_EXT            CONFIG_SYS_NAND_CSPR_EXT
 254#define CONFIG_SYS_CSPR0                CONFIG_SYS_NAND_CSPR
 255#define CONFIG_SYS_AMASK0               CONFIG_SYS_NAND_AMASK
 256#define CONFIG_SYS_CSOR0                CONFIG_SYS_NAND_CSOR
 257#define CONFIG_SYS_CS0_FTIM0            CONFIG_SYS_NAND_FTIM0
 258#define CONFIG_SYS_CS0_FTIM1            CONFIG_SYS_NAND_FTIM1
 259#define CONFIG_SYS_CS0_FTIM2            CONFIG_SYS_NAND_FTIM2
 260#define CONFIG_SYS_CS0_FTIM3            CONFIG_SYS_NAND_FTIM3
 261#define CONFIG_SYS_CSPR1_EXT            CONFIG_SYS_NOR0_CSPR_EXT
 262#define CONFIG_SYS_CSPR1                CONFIG_SYS_NOR0_CSPR
 263#define CONFIG_SYS_AMASK1               CONFIG_SYS_NOR_AMASK
 264#define CONFIG_SYS_CSOR1                CONFIG_SYS_NOR_CSOR
 265#define CONFIG_SYS_CS1_FTIM0            CONFIG_SYS_NOR_FTIM0
 266#define CONFIG_SYS_CS1_FTIM1            CONFIG_SYS_NOR_FTIM1
 267#define CONFIG_SYS_CS1_FTIM2            CONFIG_SYS_NOR_FTIM2
 268#define CONFIG_SYS_CS1_FTIM3            CONFIG_SYS_NOR_FTIM3
 269#define CONFIG_SYS_CSPR2_EXT            CONFIG_SYS_NOR1_CSPR_EXT
 270#define CONFIG_SYS_CSPR2                CONFIG_SYS_NOR1_CSPR
 271#define CONFIG_SYS_AMASK2               CONFIG_SYS_NOR_AMASK
 272#define CONFIG_SYS_CSOR2                CONFIG_SYS_NOR_CSOR
 273#define CONFIG_SYS_CS2_FTIM0            CONFIG_SYS_NOR_FTIM0
 274#define CONFIG_SYS_CS2_FTIM1            CONFIG_SYS_NOR_FTIM1
 275#define CONFIG_SYS_CS2_FTIM2            CONFIG_SYS_NOR_FTIM2
 276#define CONFIG_SYS_CS2_FTIM3            CONFIG_SYS_NOR_FTIM3
 277#else
 278#define CONFIG_SYS_CSPR0_EXT            CONFIG_SYS_NOR0_CSPR_EXT
 279#define CONFIG_SYS_CSPR0                CONFIG_SYS_NOR0_CSPR
 280#define CONFIG_SYS_AMASK0               CONFIG_SYS_NOR_AMASK
 281#define CONFIG_SYS_CSOR0                CONFIG_SYS_NOR_CSOR
 282#define CONFIG_SYS_CS0_FTIM0            CONFIG_SYS_NOR_FTIM0
 283#define CONFIG_SYS_CS0_FTIM1            CONFIG_SYS_NOR_FTIM1
 284#define CONFIG_SYS_CS0_FTIM2            CONFIG_SYS_NOR_FTIM2
 285#define CONFIG_SYS_CS0_FTIM3            CONFIG_SYS_NOR_FTIM3
 286#define CONFIG_SYS_CSPR1_EXT            CONFIG_SYS_NOR1_CSPR_EXT
 287#define CONFIG_SYS_CSPR1                CONFIG_SYS_NOR1_CSPR
 288#define CONFIG_SYS_AMASK1               CONFIG_SYS_NOR_AMASK
 289#define CONFIG_SYS_CSOR1                CONFIG_SYS_NOR_CSOR
 290#define CONFIG_SYS_CS1_FTIM0            CONFIG_SYS_NOR_FTIM0
 291#define CONFIG_SYS_CS1_FTIM1            CONFIG_SYS_NOR_FTIM1
 292#define CONFIG_SYS_CS1_FTIM2            CONFIG_SYS_NOR_FTIM2
 293#define CONFIG_SYS_CS1_FTIM3            CONFIG_SYS_NOR_FTIM3
 294#define CONFIG_SYS_CSPR2_EXT            CONFIG_SYS_NAND_CSPR_EXT
 295#define CONFIG_SYS_CSPR2                CONFIG_SYS_NAND_CSPR
 296#define CONFIG_SYS_AMASK2               CONFIG_SYS_NAND_AMASK
 297#define CONFIG_SYS_CSOR2                CONFIG_SYS_NAND_CSOR
 298#define CONFIG_SYS_CS2_FTIM0            CONFIG_SYS_NAND_FTIM0
 299#define CONFIG_SYS_CS2_FTIM1            CONFIG_SYS_NAND_FTIM1
 300#define CONFIG_SYS_CS2_FTIM2            CONFIG_SYS_NAND_FTIM2
 301#define CONFIG_SYS_CS2_FTIM3            CONFIG_SYS_NAND_FTIM3
 302#endif
 303
 304#if defined(CONFIG_RAMBOOT_PBL)
 305#define CONFIG_SYS_RAMBOOT
 306#endif
 307
 308/* I2C */
 309#define CONFIG_SYS_FSL_I2C_SPEED        100000  /* I2C speed */
 310#define CONFIG_SYS_FSL_I2C2_SPEED       100000  /* I2C2 speed */
 311#define I2C_MUX_PCA_ADDR_PRI            0x77 /* I2C bus multiplexer,primary */
 312#define I2C_MUX_PCA_ADDR_SEC            0x76 /* I2C bus multiplexer,secondary */
 313
 314#define I2C_MUX_CH_DEFAULT      0x8
 315#define I2C_MUX_CH_VOL_MONITOR  0xa
 316#define I2C_MUX_CH_VSC3316_FS   0xc
 317#define I2C_MUX_CH_VSC3316_BS   0xd
 318
 319/* Voltage monitor on channel 2*/
 320#define I2C_VOL_MONITOR_ADDR            0x40
 321#define I2C_VOL_MONITOR_BUS_V_OFFSET    0x2
 322#define I2C_VOL_MONITOR_BUS_V_OVF       0x1
 323#define I2C_VOL_MONITOR_BUS_V_SHIFT     3
 324
 325/* VSC Crossbar switches */
 326#define CONFIG_VSC_CROSSBAR
 327#define VSC3316_FSM_TX_ADDR     0x70
 328#define VSC3316_FSM_RX_ADDR     0x71
 329
 330/*
 331 * RapidIO
 332 */
 333
 334/*
 335 * for slave u-boot IMAGE instored in master memory space,
 336 * PHYS must be aligned based on the SIZE
 337 */
 338#define CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_PHYS 0xfef200000ull
 339#define CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_BUS1 0xfff00000ull
 340#define CONFIG_SRIO_PCIE_BOOT_IMAGE_SIZE 0x100000       /* 1M */
 341#define CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_BUS2 0x3fff00000ull
 342/*
 343 * for slave UCODE and ENV instored in master memory space,
 344 * PHYS must be aligned based on the SIZE
 345 */
 346#define CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_MEM_PHYS 0xfef100000ull
 347#define CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_MEM_BUS 0x3ffe00000ull
 348#define CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_SIZE 0x40000    /* 256K */
 349
 350/* slave core release by master*/
 351#define CONFIG_SRIO_PCIE_BOOT_BRR_OFFSET 0xe00e4
 352#define CONFIG_SRIO_PCIE_BOOT_RELEASE_MASK 0x00000001 /* release core 0 */
 353
 354/*
 355 * SRIO_PCIE_BOOT - SLAVE
 356 */
 357#ifdef CONFIG_SRIO_PCIE_BOOT_SLAVE
 358#define CONFIG_SYS_SRIO_PCIE_BOOT_UCODE_ENV_ADDR 0xFFE00000
 359#define CONFIG_SYS_SRIO_PCIE_BOOT_UCODE_ENV_ADDR_PHYS \
 360                (0x300000000ull | CONFIG_SYS_SRIO_PCIE_BOOT_UCODE_ENV_ADDR)
 361#endif
 362/*
 363 * eSPI - Enhanced SPI
 364 */
 365#define CONFIG_SF_DEFAULT_SPEED         10000000
 366#define CONFIG_SF_DEFAULT_MODE          0
 367
 368/* Qman/Bman */
 369#ifndef CONFIG_NOBQFMAN
 370#define CONFIG_SYS_BMAN_NUM_PORTALS     50
 371#define CONFIG_SYS_BMAN_MEM_BASE        0xf4000000
 372#define CONFIG_SYS_BMAN_MEM_PHYS        0xff4000000ull
 373#define CONFIG_SYS_BMAN_MEM_SIZE        0x02000000
 374#define CONFIG_SYS_BMAN_SP_CENA_SIZE    0x4000
 375#define CONFIG_SYS_BMAN_SP_CINH_SIZE    0x1000
 376#define CONFIG_SYS_BMAN_CENA_BASE       CONFIG_SYS_BMAN_MEM_BASE
 377#define CONFIG_SYS_BMAN_CENA_SIZE       (CONFIG_SYS_BMAN_MEM_SIZE >> 1)
 378#define CONFIG_SYS_BMAN_CINH_BASE       (CONFIG_SYS_BMAN_MEM_BASE + \
 379                                        CONFIG_SYS_BMAN_CENA_SIZE)
 380#define CONFIG_SYS_BMAN_CINH_SIZE       (CONFIG_SYS_BMAN_MEM_SIZE >> 1)
 381#define CONFIG_SYS_BMAN_SWP_ISDR_REG    0xE08
 382#define CONFIG_SYS_QMAN_NUM_PORTALS     50
 383#define CONFIG_SYS_QMAN_MEM_BASE        0xf6000000
 384#define CONFIG_SYS_QMAN_MEM_PHYS        0xff6000000ull
 385#define CONFIG_SYS_QMAN_MEM_SIZE        0x02000000
 386#define CONFIG_SYS_QMAN_SP_CENA_SIZE    0x4000
 387#define CONFIG_SYS_QMAN_SP_CINH_SIZE    0x1000
 388#define CONFIG_SYS_QMAN_CENA_BASE       CONFIG_SYS_QMAN_MEM_BASE
 389#define CONFIG_SYS_QMAN_CENA_SIZE       (CONFIG_SYS_QMAN_MEM_SIZE >> 1)
 390#define CONFIG_SYS_QMAN_CINH_BASE       (CONFIG_SYS_QMAN_MEM_BASE + \
 391                                        CONFIG_SYS_QMAN_CENA_SIZE)
 392#define CONFIG_SYS_QMAN_CINH_SIZE       (CONFIG_SYS_QMAN_MEM_SIZE >> 1)
 393#define CONFIG_SYS_QMAN_SWP_ISDR_REG    0xE08
 394
 395#define CONFIG_SYS_DPAA_FMAN
 396#define CONFIG_SYS_DPAA_PME
 397#define CONFIG_SYS_PMAN
 398#define CONFIG_SYS_DPAA_DCE
 399#define CONFIG_SYS_DPAA_RMAN
 400#define CONFIG_SYS_INTERLAKEN
 401
 402/* Default address of microcode for the Linux Fman driver */
 403#if defined(CONFIG_SPIFLASH)
 404/*
 405 * env is stored at 0x100000, sector size is 0x10000, ucode is stored after
 406 * env, so we got 0x110000.
 407 */
 408#define CONFIG_SYS_QE_FW_IN_SPIFLASH
 409#define CONFIG_SYS_FMAN_FW_ADDR 0x110000
 410#elif defined(CONFIG_SDCARD)
 411/*
 412 * PBL SD boot image should stored at 0x1000(8 blocks), the size of the image is
 413 * about 1MB (2048 blocks), Env is stored after the image, and the env size is
 414 * 0x2000 (16 blocks), 8 + 2048 + 16 = 2072, enlarge it to 2080.
 415 */
 416#define CONFIG_SYS_QE_FMAN_FW_IN_MMC
 417#define CONFIG_SYS_FMAN_FW_ADDR (512 * 0x820)
 418#elif defined(CONFIG_NAND)
 419#define CONFIG_SYS_QE_FMAN_FW_IN_NAND
 420#define CONFIG_SYS_FMAN_FW_ADDR (11 * CONFIG_SYS_NAND_BLOCK_SIZE)
 421#elif defined(CONFIG_SRIO_PCIE_BOOT_SLAVE)
 422/*
 423 * Slave has no ucode locally, it can fetch this from remote. When implementing
 424 * in two corenet boards, slave's ucode could be stored in master's memory
 425 * space, the address can be mapped from slave TLB->slave LAW->
 426 * slave SRIO or PCIE outbound window->master inbound window->
 427 * master LAW->the ucode address in master's memory space.
 428 */
 429#define CONFIG_SYS_QE_FMAN_FW_IN_REMOTE
 430#define CONFIG_SYS_FMAN_FW_ADDR 0xFFE00000
 431#else
 432#define CONFIG_SYS_QE_FMAN_FW_IN_NOR
 433#define CONFIG_SYS_FMAN_FW_ADDR         0xEFF00000
 434#endif
 435#define CONFIG_SYS_QE_FMAN_FW_LENGTH    0x10000
 436#define CONFIG_SYS_FDT_PAD              (0x3000 + CONFIG_SYS_QE_FMAN_FW_LENGTH)
 437#endif /* CONFIG_NOBQFMAN */
 438
 439#ifdef CONFIG_SYS_DPAA_FMAN
 440#define CONFIG_FMAN_ENET
 441#define CONFIG_PHYLIB_10G
 442#define CONFIG_PHY_VITESSE
 443#define CONFIG_PHY_TERANETICS
 444#define SGMII_CARD_PORT1_PHY_ADDR 0x1C
 445#define SGMII_CARD_PORT2_PHY_ADDR 0x1D
 446#define SGMII_CARD_PORT3_PHY_ADDR 0x1E
 447#define SGMII_CARD_PORT4_PHY_ADDR 0x1F
 448#define FM1_10GEC1_PHY_ADDR     0x0
 449#define FM1_10GEC2_PHY_ADDR     0x1
 450#define FM2_10GEC1_PHY_ADDR     0x2
 451#define FM2_10GEC2_PHY_ADDR     0x3
 452#endif
 453
 454/* SATA */
 455#ifdef CONFIG_FSL_SATA_V2
 456#define CONFIG_SYS_SATA_MAX_DEVICE      2
 457#define CONFIG_SATA1
 458#define CONFIG_SYS_SATA1                CONFIG_SYS_MPC85xx_SATA1_ADDR
 459#define CONFIG_SYS_SATA1_FLAGS          FLAGS_DMA
 460#define CONFIG_SATA2
 461#define CONFIG_SYS_SATA2                CONFIG_SYS_MPC85xx_SATA2_ADDR
 462#define CONFIG_SYS_SATA2_FLAGS          FLAGS_DMA
 463
 464#define CONFIG_LBA48
 465#endif
 466
 467#ifdef CONFIG_FMAN_ENET
 468#define CONFIG_ETHPRIME         "FM1@DTSEC1"
 469#endif
 470
 471/*
 472* USB
 473*/
 474#define CONFIG_USB_EHCI_FSL
 475#define CONFIG_EHCI_HCD_INIT_AFTER_RESET
 476#define CONFIG_HAS_FSL_DR_USB
 477
 478#ifdef CONFIG_MMC
 479#define CONFIG_SYS_FSL_ESDHC_ADDR       CONFIG_SYS_MPC85xx_ESDHC_ADDR
 480#define CONFIG_SYS_FSL_ESDHC_BROKEN_TIMEOUT
 481#define CONFIG_SYS_FSL_MMC_HAS_CAPBLT_VS33
 482#define CONFIG_ESDHC_DETECT_QUIRK \
 483        (!(readb(QIXIS_BASE + QIXIS_BRDCFG5) & QIXIS_MUX_SDHC) || \
 484        IS_SVR_REV(get_svr(), 1, 0))
 485#define CONFIG_ESDHC_DETECT_8_BIT_QUIRK \
 486        (!(readb(QIXIS_BASE + QIXIS_BRDCFG5) & QIXIS_MUX_SDHC_WIDTH8))
 487#endif
 488
 489
 490#define __USB_PHY_TYPE  utmi
 491
 492/*
 493 * T4240 has 3 DDR controllers. Default to 3-way interleaving. It can be
 494 * 3way_1KB, 3way_4KB, 3way_8KB. T4160 has 2 DDR controllers. Default to 2-way
 495 * interleaving. It can be cacheline, page, bank, superbank.
 496 * See doc/README.fsl-ddr for details.
 497 */
 498#ifdef CONFIG_ARCH_T4240
 499#define CTRL_INTLV_PREFERED 3way_4KB
 500#else
 501#define CTRL_INTLV_PREFERED cacheline
 502#endif
 503
 504#define CONFIG_EXTRA_ENV_SETTINGS                               \
 505        "hwconfig=fsl_ddr:"                                     \
 506        "ctlr_intlv=" __stringify(CTRL_INTLV_PREFERED) ","      \
 507        "bank_intlv=auto;"                                      \
 508        "usb1:dr_mode=host,phy_type=" __stringify(__USB_PHY_TYPE) "\0"\
 509        "netdev=eth0\0"                                         \
 510        "uboot=" __stringify(CONFIG_UBOOTPATH) "\0"                     \
 511        "ubootaddr=" __stringify(CONFIG_SYS_TEXT_BASE) "\0"             \
 512        "tftpflash=tftpboot $loadaddr $uboot && "               \
 513        "protect off $ubootaddr +$filesize && "                 \
 514        "erase $ubootaddr +$filesize && "                       \
 515        "cp.b $loadaddr $ubootaddr $filesize && "               \
 516        "protect on $ubootaddr +$filesize && "                  \
 517        "cmp.b $loadaddr $ubootaddr $filesize\0"                \
 518        "consoledev=ttyS0\0"                                    \
 519        "ramdiskaddr=2000000\0"                                 \
 520        "ramdiskfile=t4240qds/ramdisk.uboot\0"                  \
 521        "fdtaddr=1e00000\0"                                     \
 522        "fdtfile=t4240qds/t4240qds.dtb\0"                               \
 523        "bdev=sda3\0"
 524
 525#define CONFIG_HVBOOT                           \
 526        "setenv bootargs config-addr=0x60000000; "      \
 527        "bootm 0x01000000 - 0x00f00000"
 528
 529#define CONFIG_ALU                              \
 530        "setenv bootargs root=/dev/$bdev rw "           \
 531        "console=$consoledev,$baudrate $othbootargs;"   \
 532        "cpu 1 release 0x01000000 - - -;"               \
 533        "cpu 2 release 0x01000000 - - -;"               \
 534        "cpu 3 release 0x01000000 - - -;"               \
 535        "cpu 4 release 0x01000000 - - -;"               \
 536        "cpu 5 release 0x01000000 - - -;"               \
 537        "cpu 6 release 0x01000000 - - -;"               \
 538        "cpu 7 release 0x01000000 - - -;"               \
 539        "go 0x01000000"
 540
 541#define CONFIG_LINUX                            \
 542        "setenv bootargs root=/dev/ram rw "             \
 543        "console=$consoledev,$baudrate $othbootargs;"   \
 544        "setenv ramdiskaddr 0x02000000;"                \
 545        "setenv fdtaddr 0x00c00000;"                    \
 546        "setenv loadaddr 0x1000000;"                    \
 547        "bootm $loadaddr $ramdiskaddr $fdtaddr"
 548
 549#define CONFIG_HDBOOT                                   \
 550        "setenv bootargs root=/dev/$bdev rw "           \
 551        "console=$consoledev,$baudrate $othbootargs;"   \
 552        "tftp $loadaddr $bootfile;"                     \
 553        "tftp $fdtaddr $fdtfile;"                       \
 554        "bootm $loadaddr - $fdtaddr"
 555
 556#define CONFIG_NFSBOOTCOMMAND                   \
 557        "setenv bootargs root=/dev/nfs rw "     \
 558        "nfsroot=$serverip:$rootpath "          \
 559        "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \
 560        "console=$consoledev,$baudrate $othbootargs;"   \
 561        "tftp $loadaddr $bootfile;"             \
 562        "tftp $fdtaddr $fdtfile;"               \
 563        "bootm $loadaddr - $fdtaddr"
 564
 565#define CONFIG_RAMBOOTCOMMAND                           \
 566        "setenv bootargs root=/dev/ram rw "             \
 567        "console=$consoledev,$baudrate $othbootargs;"   \
 568        "tftp $ramdiskaddr $ramdiskfile;"               \
 569        "tftp $loadaddr $bootfile;"                     \
 570        "tftp $fdtaddr $fdtfile;"                       \
 571        "bootm $loadaddr $ramdiskaddr $fdtaddr"
 572
 573#define CONFIG_BOOTCOMMAND              CONFIG_LINUX
 574
 575#include <asm/fsl_secure_boot.h>
 576
 577#endif  /* __CONFIG_H */
 578