1/* SPDX-License-Identifier: GPL-2.0+ */ 2/* 3 * Configuation settings for the Hitachi Solution Engine 7720 4 * 5 * Copyright (C) 2007 Yoshihiro Shimoda <shimoda.yoshihiro@renesas.com> 6 */ 7 8#ifndef __MS7720SE_H 9#define __MS7720SE_H 10 11#define CONFIG_CPU_SH7720 1 12 13#define CONFIG_BOOTFILE "/boot/zImage" 14#define CONFIG_LOADADDR 0x8E000000 15 16#define CONFIG_DISPLAY_BOARDINFO 17#undef CONFIG_SHOW_BOOT_PROGRESS 18 19/* MEMORY */ 20#define MS7720SE_SDRAM_BASE 0x8C000000 21#define MS7720SE_FLASH_BASE_1 0xA0000000 22#define MS7720SE_FLASH_BANK_SIZE (8 * 1024 * 1024) 23 24#define CONFIG_SYS_PBSIZE 256 /* Buffer size for Console output */ 25/* List of legal baudrate settings for this board */ 26#define CONFIG_SYS_BAUDRATE_TABLE { 115200 } 27 28/* SCIF */ 29#define CONFIG_CONS_SCIF0 1 30 31#define CONFIG_SYS_MEMTEST_START MS7720SE_SDRAM_BASE 32#define CONFIG_SYS_MEMTEST_END (CONFIG_SYS_MEMTEST_START + (60 * 1024 * 1024)) 33 34#define CONFIG_SYS_SDRAM_BASE MS7720SE_SDRAM_BASE 35#define CONFIG_SYS_SDRAM_SIZE (64 * 1024 * 1024) 36 37#define CONFIG_SYS_LOAD_ADDR (CONFIG_SYS_SDRAM_BASE + 32 * 1024 * 1024) 38#define CONFIG_SYS_MONITOR_BASE MS7720SE_FLASH_BASE_1 39#define CONFIG_SYS_MONITOR_LEN (128 * 1024) 40#define CONFIG_SYS_MALLOC_LEN (256 * 1024) 41#define CONFIG_SYS_BOOTMAPSZ (8 * 1024 * 1024) 42 43/* FLASH */ 44#undef CONFIG_SYS_FLASH_QUIET_TEST 45#define CONFIG_SYS_FLASH_EMPTY_INFO /* print 'E' for empty sector on flinfo */ 46 47#define CONFIG_SYS_FLASH_BASE MS7720SE_FLASH_BASE_1 48 49#define CONFIG_SYS_MAX_FLASH_SECT 150 50#define CONFIG_SYS_MAX_FLASH_BANKS 1 51#define CONFIG_SYS_FLASH_BANKS_LIST { CONFIG_SYS_FLASH_BASE } 52 53#define CONFIG_ENV_SECT_SIZE (64 * 1024) 54#define CONFIG_ENV_SIZE CONFIG_ENV_SECT_SIZE 55#define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE + CONFIG_SYS_MONITOR_LEN) 56#define CONFIG_SYS_FLASH_ERASE_TOUT 120000 57#define CONFIG_SYS_FLASH_WRITE_TOUT 500 58 59/* Board Clock */ 60#define CONFIG_SYS_CLK_FREQ 33333333 61#define CONFIG_SH_SCIF_CLK_FREQ CONFIG_SYS_CLK_FREQ 62 63/* PCMCIA */ 64#define CONFIG_IDE_PCMCIA 1 65#define CONFIG_MARUBUN_PCCARD 1 66#define CONFIG_PCMCIA_SLOT_A 1 67#define CONFIG_SYS_IDE_MAXDEVICE 1 68#define CONFIG_SYS_MARUBUN_MRSHPC 0xb83fffe0 69#define CONFIG_SYS_MARUBUN_MW1 0xb8400000 70#define CONFIG_SYS_MARUBUN_MW2 0xb8500000 71#define CONFIG_SYS_MARUBUN_IO 0xb8600000 72 73#define CONFIG_SYS_PIO_MODE 1 74#define CONFIG_SYS_IDE_MAXBUS 1 75#define CONFIG_SYS_ATA_BASE_ADDR CONFIG_SYS_MARUBUN_IO /* base address */ 76#define CONFIG_SYS_ATA_IDE0_OFFSET 0x01F0 /* ide0 offste */ 77#define CONFIG_SYS_ATA_DATA_OFFSET 0 /* data reg offset */ 78#define CONFIG_SYS_ATA_REG_OFFSET 0 /* reg offset */ 79#define CONFIG_SYS_ATA_ALT_OFFSET 0x200 /* alternate register offset */ 80#define CONFIG_IDE_SWAP_IO 81 82#endif /* __MS7720SE_H */ 83