1/* SPDX-License-Identifier: GPL-2.0+ */ 2/* 3 * Copyright (C) 2012 Altera Corporation <www.altera.com> 4 */ 5#ifndef __CONFIG_SOCFPGA_COMMON_H__ 6#define __CONFIG_SOCFPGA_COMMON_H__ 7 8/* 9 * High level configuration 10 */ 11#define CONFIG_CLOCKS 12 13#define CONFIG_SYS_BOOTMAPSZ (64 * 1024 * 1024) 14 15#define CONFIG_TIMESTAMP /* Print image info with timestamp */ 16 17/* add target to build it automatically upon "make" */ 18#define CONFIG_BUILD_TARGET "u-boot-with-spl.sfp" 19 20/* 21 * Memory configurations 22 */ 23#define PHYS_SDRAM_1 0x0 24#define CONFIG_SYS_MALLOC_LEN (64 * 1024 * 1024) 25#define CONFIG_SYS_MEMTEST_START PHYS_SDRAM_1 26#define CONFIG_SYS_MEMTEST_END PHYS_SDRAM_1_SIZE 27#if defined(CONFIG_TARGET_SOCFPGA_GEN5) 28#define CONFIG_SYS_INIT_RAM_ADDR 0xFFFF0000 29#define CONFIG_SYS_INIT_RAM_SIZE 0x10000 30#elif defined(CONFIG_TARGET_SOCFPGA_ARRIA10) 31#define CONFIG_SYS_INIT_RAM_ADDR 0xFFE00000 32#define CONFIG_SYS_INIT_RAM_SIZE 0x40000 /* 256KB */ 33#endif 34 35/* 36 * Some boards (e.g. socfpga_sr1500) use 8 bytes at the end of the internal 37 * SRAM as bootcounter storage. Make sure to not put the stack directly 38 * at this address to not overwrite the bootcounter by checking, if the 39 * bootcounter address is located in the internal SRAM. 40 */ 41#if ((CONFIG_SYS_BOOTCOUNT_ADDR > CONFIG_SYS_INIT_RAM_ADDR) && \ 42 (CONFIG_SYS_BOOTCOUNT_ADDR < (CONFIG_SYS_INIT_RAM_ADDR + \ 43 CONFIG_SYS_INIT_RAM_SIZE))) 44#define CONFIG_SYS_INIT_SP_ADDR CONFIG_SYS_BOOTCOUNT_ADDR 45#else 46#define CONFIG_SYS_INIT_SP_ADDR \ 47 (CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_RAM_SIZE) 48#endif 49 50#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM_1 51 52/* 53 * U-Boot general configurations 54 */ 55#define CONFIG_SYS_CBSIZE 1024 /* Console I/O buffer size */ 56 /* Print buffer size */ 57#define CONFIG_SYS_MAXARGS 32 /* Max number of command args */ 58#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE 59 /* Boot argument buffer size */ 60 61#ifndef CONFIG_SYS_HOSTNAME 62#define CONFIG_SYS_HOSTNAME CONFIG_SYS_BOARD 63#endif 64 65/* 66 * Cache 67 */ 68#define CONFIG_SYS_L2_PL310 69#define CONFIG_SYS_PL310_BASE SOCFPGA_MPUL2_ADDRESS 70 71/* 72 * EPCS/EPCQx1 Serial Flash Controller 73 */ 74#ifdef CONFIG_ALTERA_SPI 75#define CONFIG_SF_DEFAULT_SPEED 30000000 76/* 77 * The base address is configurable in QSys, each board must specify the 78 * base address based on it's particular FPGA configuration. Please note 79 * that the address here is incremented by 0x400 from the Base address 80 * selected in QSys, since the SPI registers are at offset +0x400. 81 * #define CONFIG_SYS_SPI_BASE 0xff240400 82 */ 83#endif 84 85/* 86 * Ethernet on SoC (EMAC) 87 */ 88#ifdef CONFIG_CMD_NET 89#define CONFIG_DW_ALTDESCRIPTOR 90#endif 91 92/* 93 * FPGA Driver 94 */ 95#ifdef CONFIG_CMD_FPGA 96#define CONFIG_FPGA_COUNT 1 97#endif 98 99/* 100 * L4 OSC1 Timer 0 101 */ 102#ifndef CONFIG_TIMER 103/* This timer uses eosc1, whose clock frequency is fixed at any condition. */ 104#define CONFIG_SYS_TIMERBASE SOCFPGA_OSC1TIMER0_ADDRESS 105#define CONFIG_SYS_TIMER_COUNTS_DOWN 106#define CONFIG_SYS_TIMER_COUNTER (CONFIG_SYS_TIMERBASE + 0x4) 107#define CONFIG_SYS_TIMER_RATE 25000000 108#endif 109 110/* 111 * L4 Watchdog 112 */ 113#ifdef CONFIG_HW_WATCHDOG 114#define CONFIG_DESIGNWARE_WATCHDOG 115#define CONFIG_DW_WDT_BASE SOCFPGA_L4WD0_ADDRESS 116#define CONFIG_DW_WDT_CLOCK_KHZ 25000 117#define CONFIG_WATCHDOG_TIMEOUT_MSECS 30000 118#endif 119 120/* 121 * MMC Driver 122 */ 123#ifdef CONFIG_CMD_MMC 124#define CONFIG_BOUNCE_BUFFER 125/* FIXME */ 126/* using smaller max blk cnt to avoid flooding the limited stack we have */ 127#define CONFIG_SYS_MMC_MAX_BLK_COUNT 256 /* FIXME -- SPL only? */ 128#endif 129 130/* 131 * NAND Support 132 */ 133#ifdef CONFIG_NAND_DENALI 134#define CONFIG_SYS_MAX_NAND_DEVICE 1 135#define CONFIG_SYS_NAND_ONFI_DETECTION 136#define CONFIG_SYS_NAND_REGS_BASE SOCFPGA_NANDREGS_ADDRESS 137#define CONFIG_SYS_NAND_DATA_BASE SOCFPGA_NANDDATA_ADDRESS 138#endif 139 140/* 141 * I2C support 142 */ 143#ifndef CONFIG_DM_I2C 144#define CONFIG_SYS_I2C 145#define CONFIG_SYS_I2C_BASE SOCFPGA_I2C0_ADDRESS 146#define CONFIG_SYS_I2C_BASE1 SOCFPGA_I2C1_ADDRESS 147#define CONFIG_SYS_I2C_BASE2 SOCFPGA_I2C2_ADDRESS 148#define CONFIG_SYS_I2C_BASE3 SOCFPGA_I2C3_ADDRESS 149/* Using standard mode which the speed up to 100Kb/s */ 150#define CONFIG_SYS_I2C_SPEED 100000 151#define CONFIG_SYS_I2C_SPEED1 100000 152#define CONFIG_SYS_I2C_SPEED2 100000 153#define CONFIG_SYS_I2C_SPEED3 100000 154/* Address of device when used as slave */ 155#define CONFIG_SYS_I2C_SLAVE 0x02 156#define CONFIG_SYS_I2C_SLAVE1 0x02 157#define CONFIG_SYS_I2C_SLAVE2 0x02 158#define CONFIG_SYS_I2C_SLAVE3 0x02 159#ifndef __ASSEMBLY__ 160/* Clock supplied to I2C controller in unit of MHz */ 161unsigned int cm_get_l4_sp_clk_hz(void); 162#define IC_CLK (cm_get_l4_sp_clk_hz() / 1000000) 163#endif 164#endif /* CONFIG_DM_I2C */ 165 166/* 167 * QSPI support 168 */ 169/* Enable multiple SPI NOR flash manufacturers */ 170#ifndef CONFIG_SPL_BUILD 171#define CONFIG_SPI_FLASH_MTD 172#endif 173/* QSPI reference clock */ 174#ifndef __ASSEMBLY__ 175unsigned int cm_get_qspi_controller_clk_hz(void); 176#define CONFIG_CQSPI_REF_CLK cm_get_qspi_controller_clk_hz() 177#endif 178 179/* 180 * Designware SPI support 181 */ 182 183/* 184 * Serial Driver 185 */ 186#define CONFIG_SYS_NS16550_SERIAL 187 188/* 189 * USB 190 */ 191 192/* 193 * USB Gadget (DFU, UMS) 194 */ 195#if defined(CONFIG_CMD_DFU) || defined(CONFIG_CMD_USB_MASS_STORAGE) 196#define CONFIG_SYS_DFU_DATA_BUF_SIZE (16 * 1024 * 1024) 197#define DFU_DEFAULT_POLL_TIMEOUT 300 198 199/* USB IDs */ 200#define CONFIG_G_DNL_UMS_VENDOR_NUM 0x0525 201#define CONFIG_G_DNL_UMS_PRODUCT_NUM 0xA4A5 202#endif 203 204/* 205 * U-Boot environment 206 */ 207#if !defined(CONFIG_ENV_SIZE) 208#define CONFIG_ENV_SIZE (8 * 1024) 209#endif 210 211/* Environment for SDMMC boot */ 212#if defined(CONFIG_ENV_IS_IN_MMC) && !defined(CONFIG_ENV_OFFSET) 213#define CONFIG_SYS_MMC_ENV_DEV 0 /* device 0 */ 214#define CONFIG_ENV_OFFSET (34 * 512) /* just after the GPT */ 215#endif 216 217/* Environment for QSPI boot */ 218#if defined(CONFIG_ENV_IS_IN_SPI_FLASH) && !defined(CONFIG_ENV_OFFSET) 219#define CONFIG_ENV_OFFSET 0x00100000 220#define CONFIG_ENV_SECT_SIZE (64 * 1024) 221#endif 222 223/* 224 * mtd partitioning for serial NOR flash 225 * 226 * device nor0 <ff705000.spi.0>, # parts = 6 227 * #: name size offset mask_flags 228 * 0: u-boot 0x00100000 0x00000000 0 229 * 1: env1 0x00040000 0x00100000 0 230 * 2: env2 0x00040000 0x00140000 0 231 * 3: UBI 0x03e80000 0x00180000 0 232 * 4: boot 0x00e80000 0x00180000 0 233 * 5: rootfs 0x01000000 0x01000000 0 234 * 235 */ 236 237/* 238 * SPL 239 * 240 * SRAM Memory layout for gen 5: 241 * 242 * 0xFFFF_0000 ...... Start of SRAM 243 * 0xFFFF_xxxx ...... Top of stack (grows down) 244 * 0xFFFF_yyyy ...... Malloc area 245 * 0xFFFF_zzzz ...... Global Data 246 * 0xFFFF_FF00 ...... End of SRAM 247 * 248 * SRAM Memory layout for Arria 10: 249 * 0xFFE0_0000 ...... Start of SRAM (bottom) 250 * 0xFFEx_xxxx ...... Top of stack (grows down to bottom) 251 * 0xFFEy_yyyy ...... Global Data 252 * 0xFFEz_zzzz ...... Malloc area (grows up to top) 253 * 0xFFE3_FFFF ...... End of SRAM (top) 254 */ 255#define CONFIG_SPL_TEXT_BASE CONFIG_SYS_INIT_RAM_ADDR 256#define CONFIG_SPL_MAX_SIZE CONFIG_SYS_INIT_RAM_SIZE 257 258#if defined(CONFIG_TARGET_SOCFPGA_ARRIA10) 259/* SPL memory allocation configuration, this is for FAT implementation */ 260#ifndef CONFIG_SYS_SPL_MALLOC_START 261#define CONFIG_SYS_SPL_MALLOC_SIZE 0x00010000 262#define CONFIG_SYS_SPL_MALLOC_START (CONFIG_SYS_INIT_RAM_SIZE - \ 263 CONFIG_SYS_SPL_MALLOC_SIZE + \ 264 CONFIG_SYS_INIT_RAM_ADDR) 265#endif 266#endif 267 268/* SPL SDMMC boot support */ 269#ifdef CONFIG_SPL_MMC_SUPPORT 270#if defined(CONFIG_SPL_FAT_SUPPORT) || defined(CONFIG_SPL_EXT_SUPPORT) 271#define CONFIG_SPL_FS_LOAD_PAYLOAD_NAME "u-boot-dtb.img" 272#define CONFIG_SYS_MMCSD_FS_BOOT_PARTITION 1 273#endif 274#else 275#ifndef CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_PARTITION 276#define CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_PARTITION 1 277#endif 278#endif 279 280/* SPL QSPI boot support */ 281#ifdef CONFIG_SPL_SPI_SUPPORT 282#define CONFIG_SYS_SPI_U_BOOT_OFFS 0x40000 283#endif 284 285/* SPL NAND boot support */ 286#ifdef CONFIG_SPL_NAND_SUPPORT 287#define CONFIG_SYS_NAND_BAD_BLOCK_POS 0 288#define CONFIG_SYS_NAND_U_BOOT_OFFS 0x40000 289#endif 290 291/* 292 * Stack setup 293 */ 294#if defined(CONFIG_TARGET_SOCFPGA_GEN5) 295#define CONFIG_SPL_STACK CONFIG_SYS_INIT_SP_ADDR 296#elif defined(CONFIG_TARGET_SOCFPGA_ARRIA10) 297#define CONFIG_SPL_STACK CONFIG_SYS_SPL_MALLOC_START 298#endif 299 300/* Extra Environment */ 301#ifndef CONFIG_SPL_BUILD 302 303#ifdef CONFIG_CMD_DHCP 304#define BOOT_TARGET_DEVICES_DHCP(func) func(DHCP, dhcp, na) 305#else 306#define BOOT_TARGET_DEVICES_DHCP(func) 307#endif 308 309#if defined(CONFIG_CMD_PXE) && defined(CONFIG_CMD_DHCP) 310#define BOOT_TARGET_DEVICES_PXE(func) func(PXE, pxe, na) 311#else 312#define BOOT_TARGET_DEVICES_PXE(func) 313#endif 314 315#ifdef CONFIG_CMD_MMC 316#define BOOT_TARGET_DEVICES_MMC(func) func(MMC, mmc, 0) 317#else 318#define BOOT_TARGET_DEVICES_MMC(func) 319#endif 320 321#define BOOT_TARGET_DEVICES(func) \ 322 BOOT_TARGET_DEVICES_MMC(func) \ 323 BOOT_TARGET_DEVICES_PXE(func) \ 324 BOOT_TARGET_DEVICES_DHCP(func) 325 326#include <config_distro_bootcmd.h> 327 328#ifndef CONFIG_EXTRA_ENV_SETTINGS 329#define CONFIG_EXTRA_ENV_SETTINGS \ 330 "fdtfile=" CONFIG_DEFAULT_FDT_FILE "\0" \ 331 "bootm_size=0xa000000\0" \ 332 "kernel_addr_r="__stringify(CONFIG_SYS_LOAD_ADDR)"\0" \ 333 "fdt_addr_r=0x02000000\0" \ 334 "scriptaddr=0x02100000\0" \ 335 "pxefile_addr_r=0x02200000\0" \ 336 "ramdisk_addr_r=0x02300000\0" \ 337 BOOTENV 338 339#endif 340#endif 341 342#endif /* __CONFIG_SOCFPGA_COMMON_H__ */ 343