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10#ifndef __CONFIG_H
11#define __CONFIG_H
12
13
14
15
16#define CONFIG_SYS_BOARD_NAME "XPedite5170"
17#define CONFIG_SYS_FORM_3U_VPX 1
18#define CONFIG_LINUX_RESET_VEC 0x100
19#define CONFIG_BAT_RW 1
20#define CONFIG_HIGH_BATS 1
21#define CONFIG_ALTIVEC 1
22
23#define CONFIG_PCI_SCAN_SHOW 1
24#define CONFIG_PCIE1 1
25#define CONFIG_PCIE2 1
26#define CONFIG_FSL_PCI_INIT 1
27#define CONFIG_PCI_INDIRECT_BRIDGE 1
28#define CONFIG_SYS_PCI_64BIT 1
29
30
31
32
33#define CONFIG_SPD_EEPROM
34#define CONFIG_DDR_SPD
35#define CONFIG_MEM_INIT_VALUE 0xdeadbeef
36#define SPD_EEPROM_ADDRESS1 0x54
37#define SPD_EEPROM_ADDRESS2 0x54
38#define SPD_EEPROM_OFFSET 0x200
39#define CONFIG_DIMM_SLOTS_PER_CTLR 1
40#define CONFIG_CHIP_SELECTS_PER_CTRL 1
41#define CONFIG_DDR_ECC
42#define CONFIG_ECC_INIT_VIA_DDRCONTROLLER
43#define CONFIG_SYS_DDR_SDRAM_BASE 0x00000000
44#define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE
45#define CONFIG_VERY_BIG_RAM
46#define CONFIG_SYS_MAX_DDR_BAT_SIZE 0x80000000
47
48
49
50
51
52#define CONFIG_SYS_SCRATCH_VA 0xe0000000
53
54#ifndef __ASSEMBLY__
55extern unsigned long get_board_sys_clk(unsigned long dummy);
56#endif
57
58#define CONFIG_SYS_CLK_FREQ get_board_sys_clk(0)
59
60
61
62
63#define CONFIG_SYS_L2
64#define L2_INIT 0
65#define L2_ENABLE (L2CR_L2E)
66
67
68
69
70
71#define CONFIG_SYS_CCSRBAR 0xef000000
72#define CONFIG_SYS_CCSRBAR_PHYS CONFIG_SYS_CCSRBAR
73#define CONFIG_SYS_CCSRBAR_PHYS_LOW CONFIG_SYS_CCSRBAR
74#define CONFIG_SYS_CCSRBAR_PHYS_HIGH 0x0
75#define CONFIG_SYS_IMMR CONFIG_SYS_CCSRBAR
76
77
78
79
80#define CONFIG_SYS_MEMTEST_START 0x10000000
81#define CONFIG_SYS_MEMTEST_END 0x20000000
82#define CONFIG_POST (CONFIG_SYS_POST_MEMORY |\
83 CONFIG_SYS_POST_I2C)
84
85#define I2C_ADDR_IGNORE_LIST {0x50}
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101#define CONFIG_SYS_LBC_LCRR (LCRR_CLKDIV_4 | LCRR_EADC_3)
102
103
104
105
106#define CONFIG_SYS_NAND_BASE 0xef800000
107#define CONFIG_SYS_NAND_BASE2 0xef840000
108#define CONFIG_SYS_NAND_BASE_LIST {CONFIG_SYS_NAND_BASE, CONFIG_SYS_NAND_BASE2}
109#define CONFIG_SYS_MAX_NAND_DEVICE 2
110#define CONFIG_NAND_ACTL
111#define CONFIG_SYS_NAND_ACTL_ALE (1 << 14)
112#define CONFIG_SYS_NAND_ACTL_CLE (1 << 15)
113#define CONFIG_SYS_NAND_ACTL_NCE 0
114#define CONFIG_SYS_NAND_ACTL_DELAY 25
115#define CONFIG_JFFS2_NAND
116
117
118
119
120#define CONFIG_SYS_FLASH_BASE 0xf8000000
121#define CONFIG_SYS_FLASH_BASE2 0xf0000000
122#define CONFIG_SYS_FLASH_BANKS_LIST {CONFIG_SYS_FLASH_BASE, CONFIG_SYS_FLASH_BASE2}
123#define CONFIG_SYS_MAX_FLASH_BANKS 2
124#define CONFIG_SYS_MAX_FLASH_SECT 1024
125#define CONFIG_SYS_FLASH_ERASE_TOUT 60000
126#define CONFIG_SYS_FLASH_WRITE_TOUT 500
127#define CONFIG_SYS_FLASH_AUTOPROTECT_LIST { {0xfff00000, 0xc0000}, \
128 {0xf7f00000, 0xc0000} }
129#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE
130#define CONFIG_SYS_MONITOR_BASE_EARLY 0xfff00000
131
132
133
134
135
136#define CONFIG_SYS_BR0_PRELIM (CONFIG_SYS_FLASH_BASE |\
137 BR_PS_16 |\
138 BR_V)
139#define CONFIG_SYS_OR0_PRELIM (OR_AM_128MB |\
140 OR_GPCM_CSNT |\
141 OR_GPCM_XACS |\
142 OR_GPCM_ACS_DIV2 |\
143 OR_GPCM_SCY_8 |\
144 OR_GPCM_TRLX |\
145 OR_GPCM_EHTR |\
146 OR_GPCM_EAD)
147
148
149#define CONFIG_SYS_BR1_PRELIM (CONFIG_SYS_FLASH_BASE2 |\
150 BR_PS_16 |\
151 BR_V)
152#define CONFIG_SYS_OR1_PRELIM CONFIG_SYS_OR0_PRELIM
153
154
155#define CONFIG_SYS_BR2_PRELIM (CONFIG_SYS_NAND_BASE |\
156 BR_PS_8 |\
157 BR_V)
158#define CONFIG_SYS_OR2_PRELIM (OR_AM_256KB |\
159 OR_GPCM_BCTLD |\
160 OR_GPCM_CSNT |\
161 OR_GPCM_ACS_DIV4 |\
162 OR_GPCM_SCY_4 |\
163 OR_GPCM_TRLX |\
164 OR_GPCM_EHTR)
165
166
167#define CONFIG_SYS_BR3_PRELIM (CONFIG_SYS_NAND_BASE2 |\
168 BR_PS_8 |\
169 BR_V)
170#define CONFIG_SYS_OR3_PRELIM CONFIG_SYS_OR2_PRELIM
171
172
173
174
175#define CONFIG_SYS_INIT_RAM_LOCK 1
176#define CONFIG_SYS_INIT_RAM_ADDR 0xe0000000
177#define CONFIG_SYS_INIT_RAM_SIZE 0x00004000
178
179#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
180#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
181
182#define CONFIG_SYS_MONITOR_LEN (512 * 1024)
183#define CONFIG_SYS_MALLOC_LEN (1024 * 1024)
184
185
186
187
188#define CONFIG_SYS_NS16550_SERIAL
189#define CONFIG_SYS_NS16550_REG_SIZE 1
190#define CONFIG_SYS_NS16550_CLK get_bus_freq(0)
191#define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_CCSRBAR+0x4500)
192#define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_CCSRBAR+0x4600)
193#define CONFIG_SYS_BAUDRATE_TABLE \
194 {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 115200}
195#define CONFIG_LOADS_ECHO 1
196#define CONFIG_SYS_LOADS_BAUD_CHANGE 1
197
198
199
200
201#define CONFIG_SYS_I2C
202#define CONFIG_SYS_I2C_FSL
203#define CONFIG_SYS_FSL_I2C_SPEED 100000
204#define CONFIG_SYS_FSL_I2C_SLAVE 0x7F
205#define CONFIG_SYS_FSL_I2C_OFFSET 0x3000
206#define CONFIG_SYS_FSL_I2C2_SPEED 100000
207#define CONFIG_SYS_FSL_I2C2_SLAVE 0x7F
208#define CONFIG_SYS_FSL_I2C2_OFFSET 0x3100
209
210
211#define CONFIG_SYS_I2C_PEX8518_ADDR 0x70
212
213
214#define CONFIG_SYS_I2C_LM90_ADDR 0x4c
215
216
217#define CONFIG_SYS_I2C_EEPROM_ADDR 0x54
218#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 2
219#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 6
220#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 10
221
222
223#define CONFIG_RTC_M41T11 1
224#define CONFIG_SYS_I2C_RTC_ADDR 0x68
225#define CONFIG_SYS_M41T11_BASE_YEAR 2000
226
227
228#define CONFIG_PCA953X
229#define CONFIG_SYS_I2C_PCA953X_ADDR0 0x18
230#define CONFIG_SYS_I2C_PCA953X_ADDR1 0x1c
231#define CONFIG_SYS_I2C_PCA953X_ADDR2 0x1e
232#define CONFIG_SYS_I2C_PCA953X_ADDR3 0x1f
233#define CONFIG_SYS_I2C_PCA953X_ADDR CONFIG_SYS_I2C_PCA953X_ADDR0
234#define CONFIG_SYS_I2C_PCA9553_ADDR 0x62
235
236
237
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239
240
241#define CONFIG_SYS_PCA953X_C0_SER0_EN 0x01
242#define CONFIG_SYS_PCA953X_C0_SER0_MODE 0x02
243#define CONFIG_SYS_PCA953X_C0_SER1_EN 0x04
244#define CONFIG_SYS_PCA953X_C0_SER1_MODE 0x08
245#define CONFIG_SYS_PCA953X_C0_FLASH_PASS_CS 0x10
246#define CONFIG_SYS_PCA953X_NVM_WP 0x20
247
248
249#define CONFIG_SYS_PCA953X_XMC0_ROOT0 0x01
250#define CONFIG_SYS_PCA953X_PLUG_GPIO0 0x02
251#define CONFIG_SYS_PCA953X_XMC0_WAKE 0x04
252#define CONFIG_SYS_PCA953X_XMC0_BIST 0x08
253#define CONFIG_SYS_PCA953X_XMC_PRESENT 0x10
254#define CONFIG_SYS_PCA953X_PMC_PRESENT 0x20
255#define CONFIG_SYS_PCA953X_PMC0_MONARCH 0x40
256#define CONFIG_SYS_PCA953X_PMC0_EREADY 0x80
257
258
259#define CONFIG_SYS_PCA953X_P0_GA0 0x01
260#define CONFIG_SYS_PCA953X_P0_GA1 0x02
261#define CONFIG_SYS_PCA953X_P0_GA2 0x04
262#define CONFIG_SYS_PCA953X_P0_GA3 0x08
263#define CONFIG_SYS_PCA953X_P0_GA4 0x10
264#define CONFIG_SYS_PCA953X_P0_GAP 0x20
265#define CONFIG_SYS_PCA953X_P1_SYSEN 0x80
266
267
268#define CONFIG_SYS_PCA953X_VPX_GPIO0 0x01
269#define CONFIG_SYS_PCA953X_VPX_GPIO1 0x02
270#define CONFIG_SYS_PCA953X_VPX_GPIO2 0x04
271#define CONFIG_SYS_PCA953X_VPX_GPIO3 0x08
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276
277
278#define CONFIG_SYS_PCIE1_MEM_BUS 0x80000000
279#define CONFIG_SYS_PCIE1_MEM_PHYS CONFIG_SYS_PCIE1_MEM_BUS
280#define CONFIG_SYS_PCIE1_MEM_SIZE 0x40000000
281#define CONFIG_SYS_PCIE1_IO_BUS 0x00000000
282#define CONFIG_SYS_PCIE1_IO_PHYS 0xe8000000
283#define CONFIG_SYS_PCIE1_IO_SIZE 0x00800000
284
285
286#define CONFIG_SYS_PCIE2_MEM_BUS 0xc0000000
287#define CONFIG_SYS_PCIE2_MEM_PHYS CONFIG_SYS_PCIE2_MEM_BUS
288#define CONFIG_SYS_PCIE2_MEM_SIZE 0x10000000
289#define CONFIG_SYS_PCIE2_IO_BUS 0x00000000
290#define CONFIG_SYS_PCIE2_IO_PHYS 0xe8800000
291#define CONFIG_SYS_PCIE2_IO_SIZE 0x00800000
292
293
294
295
296#define CONFIG_ETHPRIME "eTSEC1"
297
298#define CONFIG_TSEC1 1
299#define CONFIG_TSEC1_NAME "eTSEC1"
300#define TSEC1_FLAGS (TSEC_GIGABIT | TSEC_REDUCED)
301#define TSEC1_PHY_ADDR 1
302#define TSEC1_PHYIDX 0
303#define CONFIG_HAS_ETH0
304
305#define CONFIG_TSEC2 1
306#define CONFIG_TSEC2_NAME "eTSEC2"
307#define TSEC2_FLAGS (TSEC_GIGABIT | TSEC_REDUCED)
308#define TSEC2_PHY_ADDR 2
309#define TSEC2_PHYIDX 0
310#define CONFIG_HAS_ETH1
311
312
313
314
315#if (CONFIG_SYS_CCSRBAR_DEFAULT != CONFIG_SYS_CCSRBAR)
316#define CONFIG_SYS_CCSR_DEFAULT_DBATL (CONFIG_SYS_CCSRBAR_DEFAULT |\
317 BATL_PP_RW |\
318 BATL_CACHEINHIBIT |\
319 BATL_GUARDEDSTORAGE)
320#define CONFIG_SYS_CCSR_DEFAULT_DBATU (CONFIG_SYS_CCSRBAR_DEFAULT |\
321 BATU_BL_1M |\
322 BATU_VS |\
323 BATU_VP)
324#define CONFIG_SYS_CCSR_DEFAULT_IBATL (CONFIG_SYS_CCSRBAR_DEFAULT |\
325 BATL_PP_RW |\
326 BATL_CACHEINHIBIT)
327#define CONFIG_SYS_CCSR_DEFAULT_IBATU CONFIG_SYS_CCSR_DEFAULT_DBATU
328#endif
329
330
331
332
333
334#define CONFIG_SYS_DBAT0L (BATL_PP_RW | BATL_MEMCOHERENCE)
335#define CONFIG_SYS_DBAT0U (BATU_BL_2G | BATU_VS | BATU_VP)
336#define CONFIG_SYS_IBAT0L (BATL_PP_RW | BATL_MEMCOHERENCE)
337#define CONFIG_SYS_IBAT0U CONFIG_SYS_DBAT0U
338
339
340
341
342
343#define CONFIG_SYS_DBAT1L (CONFIG_SYS_PCIE1_MEM_PHYS |\
344 BATL_PP_RW |\
345 BATL_CACHEINHIBIT |\
346 BATL_GUARDEDSTORAGE)
347#define CONFIG_SYS_DBAT1U (CONFIG_SYS_PCIE1_MEM_PHYS |\
348 BATU_BL_1G |\
349 BATU_VS |\
350 BATU_VP)
351#define CONFIG_SYS_IBAT1L (CONFIG_SYS_PCIE1_MEM_PHYS |\
352 BATL_PP_RW |\
353 BATL_CACHEINHIBIT)
354#define CONFIG_SYS_IBAT1U CONFIG_SYS_DBAT1U
355
356
357
358
359
360#define CONFIG_SYS_DBAT2L (CONFIG_SYS_PCIE2_MEM_PHYS |\
361 BATL_PP_RW |\
362 BATL_CACHEINHIBIT |\
363 BATL_GUARDEDSTORAGE)
364#define CONFIG_SYS_DBAT2U (CONFIG_SYS_PCIE2_MEM_PHYS |\
365 BATU_BL_512M |\
366 BATU_VS |\
367 BATU_VP)
368#define CONFIG_SYS_IBAT2L (CONFIG_SYS_PCIE2_MEM_PHYS |\
369 BATL_PP_RW |\
370 BATL_CACHEINHIBIT)
371#define CONFIG_SYS_IBAT2U CONFIG_SYS_DBAT2U
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373
374
375
376
377#define CONFIG_SYS_DBAT3L (CONFIG_SYS_CCSRBAR |\
378 BATL_PP_RW |\
379 BATL_CACHEINHIBIT |\
380 BATL_GUARDEDSTORAGE)
381#define CONFIG_SYS_DBAT3U (CONFIG_SYS_CCSRBAR |\
382 BATU_BL_1M |\
383 BATU_VS |\
384 BATU_VP)
385#define CONFIG_SYS_IBAT3L (CONFIG_SYS_CCSRBAR |\
386 BATL_PP_RW |\
387 BATL_CACHEINHIBIT)
388#define CONFIG_SYS_IBAT3U CONFIG_SYS_DBAT3U
389
390
391
392
393
394
395#define CONFIG_SYS_DBAT4L (CONFIG_SYS_PCIE1_IO_PHYS |\
396 BATL_PP_RW |\
397 BATL_CACHEINHIBIT |\
398 BATL_GUARDEDSTORAGE)
399#define CONFIG_SYS_DBAT4U (CONFIG_SYS_PCIE1_IO_PHYS |\
400 BATU_BL_32M |\
401 BATU_VS |\
402 BATU_VP)
403#define CONFIG_SYS_IBAT4L (CONFIG_SYS_PCIE1_IO_PHYS |\
404 BATL_PP_RW |\
405 BATL_CACHEINHIBIT)
406#define CONFIG_SYS_IBAT4U CONFIG_SYS_DBAT4U
407
408
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410
411
412#define CONFIG_SYS_DBAT5L (CONFIG_SYS_INIT_RAM_ADDR |\
413 BATL_PP_RW |\
414 BATL_MEMCOHERENCE)
415#define CONFIG_SYS_DBAT5U (CONFIG_SYS_INIT_RAM_ADDR |\
416 BATU_BL_128K |\
417 BATU_VS |\
418 BATU_VP)
419#define CONFIG_SYS_IBAT5L CONFIG_SYS_DBAT5L
420#define CONFIG_SYS_IBAT5U CONFIG_SYS_DBAT5U
421
422
423
424
425
426#define CONFIG_SYS_DBAT6L (CONFIG_SYS_FLASH_BASE2 |\
427 BATL_PP_RW |\
428 BATL_CACHEINHIBIT |\
429 BATL_GUARDEDSTORAGE)
430#define CONFIG_SYS_DBAT6U (CONFIG_SYS_FLASH_BASE |\
431 BATU_BL_256M |\
432 BATU_VS |\
433 BATU_VP)
434#define CONFIG_SYS_IBAT6L (CONFIG_SYS_FLASH_BASE |\
435 BATL_PP_RW |\
436 BATL_MEMCOHERENCE)
437#define CONFIG_SYS_IBAT6U CONFIG_SYS_DBAT6U
438
439
440#define CONFIG_SYS_DBAT6L_EARLY (CONFIG_SYS_MONITOR_BASE_EARLY |\
441 BATL_PP_RW |\
442 BATL_CACHEINHIBIT |\
443 BATL_GUARDEDSTORAGE)
444#define CONFIG_SYS_DBAT6U_EARLY (CONFIG_SYS_TEXT_BASE |\
445 BATU_BL_1M |\
446 BATU_VS |\
447 BATU_VP)
448#define CONFIG_SYS_IBAT6L_EARLY (CONFIG_SYS_MONITOR_BASE_EARLY |\
449 BATL_PP_RW |\
450 BATL_MEMCOHERENCE)
451#define CONFIG_SYS_IBAT6U_EARLY CONFIG_SYS_DBAT6U_EARLY
452
453
454
455
456
457
458#define CONFIG_SYS_DBAT7L (CONFIG_SYS_NAND_BASE |\
459 BATL_PP_RW |\
460 BATL_CACHEINHIBIT |\
461 BATL_GUARDEDSTORAGE)
462#define CONFIG_SYS_DBAT7U (CONFIG_SYS_NAND_BASE |\
463 BATU_BL_512K |\
464 BATU_VS |\
465 BATU_VP)
466#define CONFIG_SYS_IBAT7L (CONFIG_SYS_NAND_BASE |\
467 BATL_PP_RW |\
468 BATL_CACHEINHIBIT)
469#define CONFIG_SYS_IBAT7U CONFIG_SYS_DBAT7U
470
471
472
473
474#define CONFIG_SYS_LOAD_ADDR 0x2000000
475#define CONFIG_LOADADDR 0x1000000
476#define CONFIG_PREBOOT
477#define CONFIG_INTEGRITY
478
479
480
481
482
483
484#define CONFIG_SYS_BOOTMAPSZ (16 << 20)
485#define CONFIG_SYS_BOOTM_LEN (16 << 20)
486
487
488
489
490#define CONFIG_ENV_SECT_SIZE 0x20000
491#define CONFIG_ENV_SIZE 0x8000
492#define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE + CONFIG_SYS_MONITOR_LEN)
493
494
495
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506
507
508#define CONFIG_UBOOT1_ENV_ADDR __stringify(0xfff00000)
509#define CONFIG_UBOOT2_ENV_ADDR __stringify(0xf7f00000)
510#define CONFIG_FDT1_ENV_ADDR __stringify(0xfffc0000)
511#define CONFIG_FDT2_ENV_ADDR __stringify(0xf7fc0000)
512#define CONFIG_OS1_ENV_ADDR __stringify(0xfef00000)
513#define CONFIG_OS2_ENV_ADDR __stringify(0xf6f00000)
514
515#define CONFIG_PROG_UBOOT1 \
516 "$download_cmd $loadaddr $ubootfile; " \
517 "if test $? -eq 0; then " \
518 "protect off "CONFIG_UBOOT1_ENV_ADDR" +80000; " \
519 "erase "CONFIG_UBOOT1_ENV_ADDR" +80000; " \
520 "cp.w $loadaddr "CONFIG_UBOOT1_ENV_ADDR" 40000; " \
521 "protect on "CONFIG_UBOOT1_ENV_ADDR" +80000; " \
522 "cmp.b $loadaddr "CONFIG_UBOOT1_ENV_ADDR" 80000; " \
523 "if test $? -ne 0; then " \
524 "echo PROGRAM FAILED; " \
525 "else; " \
526 "echo PROGRAM SUCCEEDED; " \
527 "fi; " \
528 "else; " \
529 "echo DOWNLOAD FAILED; " \
530 "fi;"
531
532#define CONFIG_PROG_UBOOT2 \
533 "$download_cmd $loadaddr $ubootfile; " \
534 "if test $? -eq 0; then " \
535 "protect off "CONFIG_UBOOT2_ENV_ADDR" +80000; " \
536 "erase "CONFIG_UBOOT2_ENV_ADDR" +80000; " \
537 "cp.w $loadaddr "CONFIG_UBOOT2_ENV_ADDR" 40000; " \
538 "protect on "CONFIG_UBOOT2_ENV_ADDR" +80000; " \
539 "cmp.b $loadaddr "CONFIG_UBOOT2_ENV_ADDR" 80000; " \
540 "if test $? -ne 0; then " \
541 "echo PROGRAM FAILED; " \
542 "else; " \
543 "echo PROGRAM SUCCEEDED; " \
544 "fi; " \
545 "else; " \
546 "echo DOWNLOAD FAILED; " \
547 "fi;"
548
549#define CONFIG_BOOT_OS_NET \
550 "$download_cmd $osaddr $osfile; " \
551 "if test $? -eq 0; then " \
552 "if test -n $fdtaddr; then " \
553 "$download_cmd $fdtaddr $fdtfile; " \
554 "if test $? -eq 0; then " \
555 "bootm $osaddr - $fdtaddr; " \
556 "else; " \
557 "echo FDT DOWNLOAD FAILED; " \
558 "fi; " \
559 "else; " \
560 "bootm $osaddr; " \
561 "fi; " \
562 "else; " \
563 "echo OS DOWNLOAD FAILED; " \
564 "fi;"
565
566#define CONFIG_PROG_OS1 \
567 "$download_cmd $osaddr $osfile; " \
568 "if test $? -eq 0; then " \
569 "erase "CONFIG_OS1_ENV_ADDR" +$filesize; " \
570 "cp.b $osaddr "CONFIG_OS1_ENV_ADDR" $filesize; " \
571 "cmp.b $osaddr "CONFIG_OS1_ENV_ADDR" $filesize; " \
572 "if test $? -ne 0; then " \
573 "echo OS PROGRAM FAILED; " \
574 "else; " \
575 "echo OS PROGRAM SUCCEEDED; " \
576 "fi; " \
577 "else; " \
578 "echo OS DOWNLOAD FAILED; " \
579 "fi;"
580
581#define CONFIG_PROG_OS2 \
582 "$download_cmd $osaddr $osfile; " \
583 "if test $? -eq 0; then " \
584 "erase "CONFIG_OS2_ENV_ADDR" +$filesize; " \
585 "cp.b $osaddr "CONFIG_OS2_ENV_ADDR" $filesize; " \
586 "cmp.b $osaddr "CONFIG_OS2_ENV_ADDR" $filesize; " \
587 "if test $? -ne 0; then " \
588 "echo OS PROGRAM FAILED; " \
589 "else; " \
590 "echo OS PROGRAM SUCCEEDED; " \
591 "fi; " \
592 "else; " \
593 "echo OS DOWNLOAD FAILED; " \
594 "fi;"
595
596#define CONFIG_PROG_FDT1 \
597 "$download_cmd $fdtaddr $fdtfile; " \
598 "if test $? -eq 0; then " \
599 "erase "CONFIG_FDT1_ENV_ADDR" +$filesize;" \
600 "cp.b $fdtaddr "CONFIG_FDT1_ENV_ADDR" $filesize; " \
601 "cmp.b $fdtaddr "CONFIG_FDT1_ENV_ADDR" $filesize; " \
602 "if test $? -ne 0; then " \
603 "echo FDT PROGRAM FAILED; " \
604 "else; " \
605 "echo FDT PROGRAM SUCCEEDED; " \
606 "fi; " \
607 "else; " \
608 "echo FDT DOWNLOAD FAILED; " \
609 "fi;"
610
611#define CONFIG_PROG_FDT2 \
612 "$download_cmd $fdtaddr $fdtfile; " \
613 "if test $? -eq 0; then " \
614 "erase "CONFIG_FDT2_ENV_ADDR" +$filesize;" \
615 "cp.b $fdtaddr "CONFIG_FDT2_ENV_ADDR" $filesize; " \
616 "cmp.b $fdtaddr "CONFIG_FDT2_ENV_ADDR" $filesize; " \
617 "if test $? -ne 0; then " \
618 "echo FDT PROGRAM FAILED; " \
619 "else; " \
620 "echo FDT PROGRAM SUCCEEDED; " \
621 "fi; " \
622 "else; " \
623 "echo FDT DOWNLOAD FAILED; " \
624 "fi;"
625
626#define CONFIG_EXTRA_ENV_SETTINGS \
627 "autoload=yes\0" \
628 "download_cmd=tftp\0" \
629 "console_args=console=ttyS0,115200\0" \
630 "root_args=root=/dev/nfs rw\0" \
631 "misc_args=ip=on\0" \
632 "set_bootargs=setenv bootargs ${console_args} ${root_args} ${misc_args}\0" \
633 "bootfile=/home/user/file\0" \
634 "osfile=/home/user/board.uImage\0" \
635 "fdtfile=/home/user/board.dtb\0" \
636 "ubootfile=/home/user/u-boot.bin\0" \
637 "fdtaddr=0x1e00000\0" \
638 "osaddr=0x1000000\0" \
639 "loadaddr=0x1000000\0" \
640 "prog_uboot1="CONFIG_PROG_UBOOT1"\0" \
641 "prog_uboot2="CONFIG_PROG_UBOOT2"\0" \
642 "prog_os1="CONFIG_PROG_OS1"\0" \
643 "prog_os2="CONFIG_PROG_OS2"\0" \
644 "prog_fdt1="CONFIG_PROG_FDT1"\0" \
645 "prog_fdt2="CONFIG_PROG_FDT2"\0" \
646 "bootcmd_net=run set_bootargs; "CONFIG_BOOT_OS_NET"\0" \
647 "bootcmd_flash1=run set_bootargs; " \
648 "bootm "CONFIG_OS1_ENV_ADDR" - "CONFIG_FDT1_ENV_ADDR"\0"\
649 "bootcmd_flash2=run set_bootargs; " \
650 "bootm "CONFIG_OS2_ENV_ADDR" - "CONFIG_FDT2_ENV_ADDR"\0"\
651 "bootcmd=run bootcmd_flash1\0"
652#endif
653