LXR uboot/arch/arm/include/asm/arch-mx7ulp/scg.h

   1/* SPDX-License-Identifier: GPL-2.0+ */
   2/*
   3 * Copyright (C) 2016 Freescale Semiconductor, Inc.
   4 */
   5
   6#ifndef _ASM_ARCH_SCG_H
   7#define _ASM_ARCH_SCG_H
   8
   9#include <common.h>
  10
  11#ifdef CONFIG_CLK_DEBUG
  12#define clk_debug(fmt, args...) printf(fmt, ##args)
  13#else
  14#define clk_debug(fmt, args...)
  15#endif
  16
  17#define SCG_CCR_SCS_SHIFT               (24)
  18#define SCG_CCR_SCS_MASK                ((0xFUL) << SCG_CCR_SCS_SHIFT)
  19#define SCG_CCR_DIVCORE_SHIFT           (16)
  20#define SCG_CCR_DIVCORE_MASK            ((0xFUL) << SCG_CCR_DIVCORE_SHIFT)
  21#define SCG_CCR_DIVPLAT_SHIFT           (12)
  22#define SCG_CCR_DIVPLAT_MASK            ((0xFUL) << SCG_CCR_DIVPLAT_SHIFT)
  23#define SCG_CCR_DIVEXT_SHIFT            (8)
  24#define SCG_CCR_DIVEXT_MASK             ((0xFUL) << SCG_CCR_DIVEXT_SHIFT)
  25#define SCG_CCR_DIVBUS_SHIFT            (4)
  26#define SCG_CCR_DIVBUS_MASK             ((0xFUL) << SCG_CCR_DIVBUS_SHIFT)
  27#define SCG_CCR_DIVSLOW_SHIFT           (0)
  28#define SCG_CCR_DIVSLOW_MASK            ((0xFUL) << SCG_CCR_DIVSLOW_SHIFT)
  29
  30/* SCG DDR Clock Control Register */
  31#define SCG_DDRCCR_DDRCS_SHIFT          (24)
  32#define SCG_DDRCCR_DDRCS_MASK           ((0x1UL) << SCG_DDRCCR_DDRCS_SHIFT)
  33
  34#define SCG_DDRCCR_DDRDIV_SHIFT         (0)
  35#define SCG_DDRCCR_DDRDIV_MASK          ((0x7UL) << SCG_DDRCCR_DDRDIV_SHIFT)
  36
  37/* SCG NIC Clock Control Register */
  38#define SCG_NICCCR_NICCS_SHIFT          (28)
  39#define SCG_NICCCR_NICCS_MASK           ((0x1UL) << SCG_NICCCR_NICCS_SHIFT)
  40
  41#define SCG_NICCCR_NIC0_DIV_SHIFT       (24)
  42#define SCG_NICCCR_NIC0_DIV_MASK        ((0xFUL) << SCG_NICCCR_NIC0_DIV_SHIFT)
  43
  44#define SCG_NICCCR_GPU_DIV_SHIFT        (20)
  45#define SCG_NICCCR_GPU_DIV_MASK         ((0xFUL) << SCG_NICCCR_GPU_DIV_SHIFT)
  46
  47#define SCG_NICCCR_NIC1_DIV_SHIFT       (16)
  48#define SCG_NICCCR_NIC1_DIV_MASK        ((0xFUL) << SCG_NICCCR_NIC1_DIV_SHIFT)
  49
  50#define SCG_NICCCR_NIC1_DIVEXT_SHIFT    (8)
  51#define SCG_NICCCR_NIC1_DIVEXT_MASK   ((0xFUL) << SCG_NICCCR_NIC1_DIVEXT_SHIFT)
  52
  53#define SCG_NICCCR_NIC1_DIVBUS_SHIFT    (4)
  54#define SCG_NICCCR_NIC1_DIVBUS_MASK   ((0xFUL) << SCG_NICCCR_NIC1_DIVBUS_SHIFT)
  55
  56/* SCG NIC clock status register */
  57#define SCG_NICCSR_NICCS_SHIFT          (28)
  58#define SCG_NICCSR_NICCS_MASK           ((0x1UL) << SCG_NICCSR_NICCS_SHIFT)
  59
  60#define SCG_NICCSR_NIC0DIV_SHIFT        (24)
  61#define SCG_NICCSR_NIC0DIV_MASK         ((0xFUL) << SCG_NICCSR_NIC0DIV_SHIFT)
  62#define SCG_NICCSR_GPUDIV_SHIFT         (20)
  63#define SCG_NICCSR_GPUDIV_MASK          ((0xFUL) << SCG_NICCSR_GPUDIV_SHIFT)
  64#define SCG_NICCSR_NIC1DIV_SHIFT        (16)
  65#define SCG_NICCSR_NIC1DIV_MASK         ((0xFUL) << SCG_NICCSR_NIC1DIV_SHIFT)
  66#define SCG_NICCSR_NIC1EXTDIV_SHIFT     (8)
  67#define SCG_NICCSR_NIC1EXTDIV_MASK      ((0xFUL) << SCG_NICCSR_NIC1EXTDIV_SHIFT)
  68#define SCG_NICCSR_NIC1BUSDIV_SHIFT     (4)
  69#define SCG_NICCSR_NIC1BUSDIV_MASK      ((0xFUL) << SCG_NICCSR_NIC1BUSDIV_SHIFT)
  70
  71/* SCG Slow IRC Control Status Register */
  72#define SCG_SIRC_CSR_SIRCVLD_SHIFT      (24)
  73#define SCG_SIRC_CSR_SIRCVLD_MASK       ((0x1UL) << SCG_SIRC_CSR_SIRCVLD_SHIFT)
  74
  75#define SCG_SIRC_CSR_SIRCEN_SHIFT       (0)
  76#define SCG_SIRC_CSR_SIRCEN_MASK        ((0x1UL) << SCG_SIRC_CSR_SIRCEN_SHIFT)
  77
  78/* SCG Slow IRC Configuration Register */
  79#define SCG_SIRCCFG_RANGE_SHIFT         (0)
  80#define SCG_SIRCCFG_RANGE_MASK          ((0x1UL) << SCG_SIRCCFG_RANGE_SHIFT)
  81#define SCG_SIRCCFG_RANGE_4M            ((0x0UL) << SCG_SIRCCFG_RANGE_SHIFT)
  82#define SCG_SIRCCFG_RANGE_16M           ((0x1UL) << SCG_SIRCCFG_RANGE_SHIFT)
  83
  84/* SCG Slow IRC Divide Register */
  85#define SCG_SIRCDIV_DIV3_SHIFT          (16)
  86#define SCG_SIRCDIV_DIV3_MASK           ((0x7UL) << SCG_SIRCDIV_DIV3_SHIFT)
  87
  88#define SCG_SIRCDIV_DIV2_SHIFT          (8)
  89#define SCG_SIRCDIV_DIV2_MASK           ((0x7UL) << SCG_SIRCDIV_DIV2_SHIFT)
  90
  91#define SCG_SIRCDIV_DIV1_SHIFT          (0)
  92#define SCG_SIRCDIV_DIV1_MASK           ((0x7UL) << SCG_SIRCDIV_DIV1_SHIFT)
  93/*
  94 * FIRC/SIRC DIV1 ==> xIRC_PLAT_CLK
  95 * FIRC/SIRC DIV2 ==> xIRC_BUS_CLK
  96 * FIRC/SIRC DIV3 ==> xIRC_SLOW_CLK
  97 */
  98
  99/* SCG Fast IRC Control Status Register */
 100#define SCG_FIRC_CSR_FIRCVLD_SHIFT      (24)
 101#define SCG_FIRC_CSR_FIRCVLD_MASK       ((0x1UL) << SCG_FIRC_CSR_FIRCVLD_SHIFT)
 102
 103#define SCG_FIRC_CSR_FIRCEN_SHIFT       (0)
 104#define SCG_FIRC_CSR_FIRCEN_MASK        ((0x1UL) << SCG_FIRC_CSR_FIRCEN_SHIFT)
 105
 106/* SCG Fast IRC Divide Register */
 107#define SCG_FIRCDIV_DIV3_SHIFT          (16)
 108#define SCG_FIRCDIV_DIV3_MASK           ((0x7UL) << SCG_FIRCDIV_DIV3_SHIFT)
 109
 110#define SCG_FIRCDIV_DIV2_SHIFT          (8)
 111#define SCG_FIRCDIV_DIV2_MASK           ((0x7UL) << SCG_FIRCDIV_DIV2_SHIFT)
 112
 113#define SCG_FIRCDIV_DIV1_SHIFT          (0)
 114#define SCG_FIRCDIV_DIV1_MASK           ((0x7UL) << SCG_FIRCDIV_DIV1_SHIFT)
 115
 116#define SCG_FIRCCFG_RANGE_SHIFT         (0)
 117#define SCG_FIRCCFG_RANGE_MASK          ((0x3UL) << SCG_FIRCCFG_RANGE_SHIFT)
 118
 119#define SCG_FIRCCFG_RANGE_SHIFT         (0)
 120#define SCG_FIRCCFG_RANGE_48M           ((0x0UL) << SCG_FIRCCFG_RANGE_SHIFT)
 121
 122/* SCG System OSC Control Status Register */
 123#define SCG_SOSC_CSR_SOSCVLD_SHIFT      (24)
 124#define SCG_SOSC_CSR_SOSCVLD_MASK       ((0x1UL) << SCG_SOSC_CSR_SOSCVLD_SHIFT)
 125
 126/* SCG Fast IRC Divide Register */
 127#define SCG_SOSCDIV_DIV3_SHIFT          (16)
 128#define SCG_SOSCDIV_DIV3_MASK           ((0x7UL) << SCG_SOSCDIV_DIV3_SHIFT)
 129
 130#define SCG_SOSCDIV_DIV2_SHIFT          (8)
 131#define SCG_SOSCDIV_DIV2_MASK           ((0x7UL) << SCG_SOSCDIV_DIV2_SHIFT)
 132
 133#define SCG_SOSCDIV_DIV1_SHIFT          (0)
 134#define SCG_SOSCDIV_DIV1_MASK           ((0x7UL) << SCG_SOSCDIV_DIV1_SHIFT)
 135
 136/* SCG RTC OSC Control Status Register */
 137#define SCG_ROSC_CSR_ROSCVLD_SHIFT      (24)
 138#define SCG_ROSC_CSR_ROSCVLD_MASK       ((0x1UL) << SCG_ROSC_CSR_ROSCVLD_SHIFT)
 139
 140#define SCG_SPLL_CSR_SPLLVLD_SHIFT      (24)
 141#define SCG_SPLL_CSR_SPLLVLD_MASK       ((0x1UL) << SCG_SPLL_CSR_SPLLVLD_SHIFT)
 142#define SCG_SPLL_CSR_SPLLEN_SHIFT       (0)
 143#define SCG_SPLL_CSR_SPLLEN_MASK        ((0x1UL) << SCG_SPLL_CSR_SPLLEN_SHIFT)
 144#define SCG_APLL_CSR_APLLEN_SHIFT       (0)
 145#define SCG_APLL_CSR_APLLEN_MASK        (0x1UL)
 146#define SCG_APLL_CSR_APLLVLD_MASK       (0x01000000)
 147
 148#define SCG_UPLL_CSR_UPLLVLD_MASK       (0x01000000)
 149
 150
 151#define SCG_PLL_PFD3_GATE_MASK          (0x80000000)
 152#define SCG_PLL_PFD2_GATE_MASK          (0x00800000)
 153#define SCG_PLL_PFD1_GATE_MASK          (0x00008000)
 154#define SCG_PLL_PFD0_GATE_MASK          (0x00000080)
 155#define SCG_PLL_PFD3_VALID_MASK         (0x40000000)
 156#define SCG_PLL_PFD2_VALID_MASK         (0x00400000)
 157#define SCG_PLL_PFD1_VALID_MASK         (0x00004000)
 158#define SCG_PLL_PFD0_VALID_MASK         (0x00000040)
 159
 160#define SCG_PLL_PFD0_FRAC_SHIFT         (0)
 161#define SCG_PLL_PFD0_FRAC_MASK          ((0x3F) << SCG_PLL_PFD0_FRAC_SHIFT)
 162#define SCG_PLL_PFD1_FRAC_SHIFT         (8)
 163#define SCG_PLL_PFD1_FRAC_MASK          ((0x3F) << SCG_PLL_PFD1_FRAC_SHIFT)
 164#define SCG_PLL_PFD2_FRAC_SHIFT         (16)
 165#define SCG_PLL_PFD2_FRAC_MASK          ((0x3F) << SCG_PLL_PFD2_FRAC_SHIFT)
 166#define SCG_PLL_PFD3_FRAC_SHIFT         (24)
 167#define SCG_PLL_PFD3_FRAC_MASK          ((0x3F) << SCG_PLL_PFD3_FRAC_SHIFT)
 168
 169#define SCG_PLL_CFG_POSTDIV2_SHIFT      (28)
 170#define SCG_PLL_CFG_POSTDIV2_MASK       ((0xFUL) << SCG_PLL_CFG_POSTDIV2_SHIFT)
 171#define SCG_PLL_CFG_POSTDIV1_SHIFT      (24)
 172#define SCG_PLL_CFG_POSTDIV1_MASK       ((0xFUL) << SCG_PLL_CFG_POSTDIV1_SHIFT)
 173#define SCG_PLL_CFG_MULT_SHIFT          (16)
 174#define SCG1_SPLL_CFG_MULT_MASK         ((0x7FUL) << SCG_PLL_CFG_MULT_SHIFT)
 175#define SCG_APLL_CFG_MULT_MASK          ((0x7FUL) << SCG_PLL_CFG_MULT_SHIFT)
 176#define SCG_PLL_CFG_PFDSEL_SHIFT        (14)
 177#define SCG_PLL_CFG_PFDSEL_MASK         ((0x3UL) << SCG_PLL_CFG_PFDSEL_SHIFT)
 178#define SCG_PLL_CFG_PREDIV_SHIFT        (8)
 179#define SCG_PLL_CFG_PREDIV_MASK         ((0x7UL) << SCG_PLL_CFG_PREDIV_SHIFT)
 180#define SCG_PLL_CFG_BYPASS_SHIFT        (2)
 181/* 0: SPLL, 1: bypass */
 182#define SCG_PLL_CFG_BYPASS_MASK         ((0x1UL) << SCG_PLL_CFG_BYPASS_SHIFT)
 183#define SCG_PLL_CFG_PLLSEL_SHIFT        (1)
 184/* 0: pll, 1: pfd */
 185#define SCG_PLL_CFG_PLLSEL_MASK         ((0x1UL) << SCG_PLL_CFG_PLLSEL_SHIFT)
 186#define SCG_PLL_CFG_CLKSRC_SHIFT        (0)
 187/* 0: Sys-OSC, 1: FIRC */
 188#define SCG_PLL_CFG_CLKSRC_MASK         ((0x1UL) << SCG_PLL_CFG_CLKSRC_SHIFT)
 189#define SCG0_SPLL_CFG_MULT_SHIFT        (17)
 190/* 0: Multiplier = 20, 1: Multiplier = 22 */
 191#define SCG0_SPLL_CFG_MULT_MASK         ((0x1UL) << SCG0_SPLL_CFG_MULT_SHIFT)
 192
 193#define PLL_USB_EN_USB_CLKS_MASK        (0x01 << 6)
 194#define PLL_USB_PWR_MASK                (0x01 << 12)
 195#define PLL_USB_ENABLE_MASK             (0x01 << 13)
 196#define PLL_USB_BYPASS_MASK             (0x01 << 16)
 197#define PLL_USB_REG_ENABLE_MASK         (0x01 << 21)
 198#define PLL_USB_DIV_SEL_MASK            (0x07 << 22)
 199#define PLL_USB_LOCK_MASK               (0x01 << 31)
 200
 201enum scg_clk {
 202        SCG_SOSC_CLK,
 203        SCG_FIRC_CLK,
 204        SCG_SIRC_CLK,
 205        SCG_ROSC_CLK,
 206        SCG_SIRC_DIV1_CLK,
 207        SCG_SIRC_DIV2_CLK,
 208        SCG_SIRC_DIV3_CLK,
 209        SCG_FIRC_DIV1_CLK,
 210        SCG_FIRC_DIV2_CLK,
 211        SCG_FIRC_DIV3_CLK,
 212        SCG_SOSC_DIV1_CLK,
 213        SCG_SOSC_DIV2_CLK,
 214        SCG_SOSC_DIV3_CLK,
 215        SCG_CORE_CLK,
 216        SCG_BUS_CLK,
 217        SCG_SPLL_PFD0_CLK,
 218        SCG_SPLL_PFD1_CLK,
 219        SCG_SPLL_PFD2_CLK,
 220        SCG_SPLL_PFD3_CLK,
 221        SCG_DDR_CLK,
 222        SCG_NIC0_CLK,
 223        SCG_GPU_CLK,
 224        SCG_NIC1_CLK,
 225        SCG_NIC1_BUS_CLK,
 226        SCG_NIC1_EXT_CLK,
 227        SCG_APLL_PFD0_CLK,
 228        SCG_APLL_PFD1_CLK,
 229        SCG_APLL_PFD2_CLK,
 230        SCG_APLL_PFD3_CLK,
 231        USB_PLL_OUT,
 232        MIPI_PLL_OUT
 233};
 234
 235enum scg_sys_src {
 236        SCG_SCS_SYS_OSC = 1,
 237        SCG_SCS_SLOW_IRC,
 238        SCG_SCS_FAST_IRC,
 239        SCG_SCS_RTC_OSC,
 240        SCG_SCS_AUX_PLL,
 241        SCG_SCS_SYS_PLL,
 242        SCG_SCS_USBPHY_PLL,
 243};
 244
 245/* PLL supported by i.mx7ulp */
 246enum pll_clocks {
 247        PLL_M4_SPLL,    /* M4 SPLL */
 248        PLL_M4_APLL,    /* M4 APLL*/
 249        PLL_A7_SPLL,    /* A7 SPLL */
 250        PLL_A7_APLL,    /* A7 APLL */
 251        PLL_USB,        /* USB PLL*/
 252        PLL_MIPI,       /* MIPI PLL */
 253};
 254
 255typedef struct scg_regs {
 256        u32 verid;      /* VERSION_ID */
 257        u32 param;      /*  PARAMETER */
 258        u32 rsvd11[2];
 259
 260        u32 csr;        /*  Clock Status Register */
 261        u32 rccr;       /*  Run Clock Control Register */
 262        u32 vccr;       /*  VLPR Clock Control Register */
 263        u32 hccr;       /*  HSRUN Clock Control Register */
 264        u32 clkoutcnfg; /*  SCG CLKOUT Configuration Register */
 265        u32 rsvd12[3];
 266        u32 ddrccr;     /*  SCG DDR Clock Control Register */
 267        u32 rsvd13[3];
 268        u32 nicccr;     /*  NIC Clock Control Register */
 269        u32 niccsr;     /*  NIC Clock Status Register */
 270        u32 rsvd10[46];
 271
 272        u32 sosccsr;    /*  System OSC Control Status Register, offset 0x100 */
 273        u32 soscdiv;    /*  System OSC Divide Register */
 274        u32 sosccfg;    /*  System Oscillator Configuration Register */
 275        u32 sosctest;   /*  System Oscillator Test Register */
 276        u32 rsvd20[60];
 277
 278        u32 sirccsr;    /*  Slow IRC Control Status Register, offset 0x200 */
 279        u32 sircdiv;    /*  Slow IRC Divide Register */
 280        u32 sirccfg;    /*  Slow IRC Configuration Register */
 281        u32 sirctrim;   /*  Slow IRC Trim Register */
 282        u32 loptrim;    /*  Low Power Oscillator Trim Register */
 283        u32 sirctest;   /*  Slow IRC Test Register */
 284        u32 rsvd30[58];
 285
 286        u32 firccsr;    /*  Fast IRC Control Status Register, offset 0x300 */
 287        u32 fircdiv;
 288        u32 firccfg;
 289        u32 firctcfg;   /*  Fast IRC Trim Configuration Register */
 290        u32 firctriml;  /*  Fast IRC Trim Low Register */
 291        u32 firctrimh;
 292        u32 fircstat;   /*  Fast IRC Status Register */
 293        u32 firctest;   /*  Fast IRC Test Register */
 294        u32 rsvd40[56];
 295
 296        u32 rtccsr;     /*  RTC OSC Control Status Register, offset 0x400 */
 297        u32 rsvd50[63];
 298
 299        u32 apllcsr; /*  Auxiliary PLL Control Status Register, offset 0x500 */
 300        u32 aplldiv;    /*  Auxiliary PLL Divider Register */
 301        u32 apllcfg;    /*  Auxiliary PLL Configuration Register */
 302        u32 apllpfd;    /*  Auxiliary PLL PFD Register */
 303        u32 apllnum;    /*  Auxiliary PLL Numerator Register */
 304        u32 aplldenom;  /*  Auxiliary PLL Denominator Register */
 305        u32 apllss;     /*  Auxiliary PLL Spread Spectrum Register */
 306        u32 rsvd60[55];
 307        u32 apllock_cnfg; /*  Auxiliary PLL LOCK Configuration Register */
 308        u32 rsvd61[1];
 309
 310        u32 spllcsr;    /*  System PLL Control Status Register, offset 0x600 */
 311        u32 splldiv;    /*  System PLL Divide Register */
 312        u32 spllcfg;    /*  System PLL Configuration Register */
 313        u32 spllpfd;    /*  System PLL Test Register */
 314        u32 spllnum;    /*  System PLL Numerator Register */
 315        u32 splldenom;  /*  System PLL Denominator Register */
 316        u32 spllss;     /*  System PLL Spread Spectrum Register */
 317        u32 rsvd70[55];
 318        u32 spllock_cnfg;       /*  System PLL LOCK Configuration Register */
 319        u32 rsvd71[1];
 320
 321        u32 upllcsr;    /*  USB PLL Control Status Register, offset 0x700 */
 322        u32 uplldiv;    /*  USB PLL Divide Register */
 323        u32 upllcfg;    /*  USB PLL Configuration Register */
 324} scg_t, *scg_p;
 325
 326u32 scg_clk_get_rate(enum scg_clk clk);
 327int scg_enable_pll_pfd(enum scg_clk clk, u32 frac);
 328int scg_enable_usb_pll(bool usb_control);
 329u32 decode_pll(enum pll_clocks pll);
 330
 331void scg_a7_rccr_init(void);
 332void scg_a7_spll_init(void);
 333void scg_a7_ddrclk_init(void);
 334void scg_a7_apll_init(void);
 335void scg_a7_firc_init(void);
 336void scg_a7_nicclk_init(void);
 337void scg_a7_sys_clk_sel(enum scg_sys_src clk);
 338void scg_a7_info(void);
 339void scg_a7_soscdiv_init(void);
 340
 341#endif
 342