1/* SPDX-License-Identifier: GPL-2.0+ */ 2/* 3 * (C) Copyright 2016 Rockchip Electronics Co., Ltd 4 */ 5 6#ifndef __SOC_ROCKCHIP_RK3328_GRF_H__ 7#define __SOC_ROCKCHIP_RK3328_GRF_H__ 8 9struct rk3328_grf_regs { 10 u32 gpio0a_iomux; 11 u32 gpio0b_iomux; 12 u32 gpio0c_iomux; 13 u32 gpio0d_iomux; 14 u32 gpio1a_iomux; 15 u32 gpio1b_iomux; 16 u32 gpio1c_iomux; 17 u32 gpio1d_iomux; 18 u32 gpio2a_iomux; 19 u32 gpio2bl_iomux; 20 u32 gpio2bh_iomux; 21 u32 gpio2cl_iomux; 22 u32 gpio2ch_iomux; 23 u32 gpio2d_iomux; 24 u32 gpio3al_iomux; 25 u32 gpio3ah_iomux; 26 u32 gpio3bl_iomux; 27 u32 gpio3bh_iomux; 28 u32 gpio3c_iomux; 29 u32 gpio3d_iomux; 30 u32 com_iomux; 31 u32 reserved1[(0x100 - 0x54) / 4]; 32 33 u32 gpio0a_p; 34 u32 gpio0b_p; 35 u32 gpio0c_p; 36 u32 gpio0d_p; 37 u32 gpio1a_p; 38 u32 gpio1b_p; 39 u32 gpio1c_p; 40 u32 gpio1d_p; 41 u32 gpio2a_p; 42 u32 gpio2b_p; 43 u32 gpio2c_p; 44 u32 gpio2d_p; 45 u32 gpio3a_p; 46 u32 gpio3b_p; 47 u32 gpio3c_p; 48 u32 gpio3d_p; 49 u32 reserved2[(0x200 - 0x140) / 4]; 50 u32 gpio0a_e; 51 u32 gpio0b_e; 52 u32 gpio0c_e; 53 u32 gpio0d_e; 54 u32 gpio1a_e; 55 u32 gpio1b_e; 56 u32 gpio1c_e; 57 u32 gpio1d_e; 58 u32 gpio2a_e; 59 u32 gpio2b_e; 60 u32 gpio2c_e; 61 u32 gpio2d_e; 62 u32 gpio3a_e; 63 u32 gpio3b_e; 64 u32 gpio3c_e; 65 u32 gpio3d_e; 66 u32 reserved3[(0x300 - 0x240) / 4]; 67 u32 gpio0l_sr; 68 u32 gpio0h_sr; 69 u32 gpio1l_sr; 70 u32 gpio1h_sr; 71 u32 gpio2l_sr; 72 u32 gpio2h_sr; 73 u32 gpio3l_sr; 74 u32 gpio3h_sr; 75 u32 reserved4[(0x380 - 0x320) / 4]; 76 u32 gpio0l_smt; 77 u32 gpio0h_smt; 78 u32 gpio1l_smt; 79 u32 gpio1h_smt; 80 u32 gpio2l_smt; 81 u32 gpio2h_smt; 82 u32 gpio3l_smt; 83 u32 gpio3h_smt; 84 u32 reserved5[(0x400 - 0x3a0) / 4]; 85 u32 soc_con[11]; 86 u32 reserved6[(0x480 - 0x42c) / 4]; 87 u32 soc_status[5]; 88 u32 reserved7[(0x4c0 - 0x494) / 4]; 89 u32 otg3_con[2]; 90 u32 reserved8[(0x500 - 0x4c8) / 4]; 91 u32 cpu_con[2]; 92 u32 reserved9[(0x520 - 0x508) / 4]; 93 u32 cpu_status[2]; 94 u32 reserved10[(0x5c8 - 0x528) / 4]; 95 u32 os_reg[8]; 96 u32 reserved11[(0x680 - 0x5e8) / 4]; 97 u32 sig_detect_con; 98 u32 reserved12[3]; 99 u32 sig_detect_status; 100 u32 reserved13[3]; 101 u32 sig_detect_status_clr; 102 u32 reserved14[3]; 103 104 u32 sdmmc_det_counter; 105 u32 reserved15[(0x700 - 0x6b4) / 4]; 106 u32 host0_con[3]; 107 u32 reserved16[(0x880 - 0x70c) / 4]; 108 u32 otg_con0; 109 u32 reserved17[3]; 110 u32 host0_status; 111 u32 reserved18[(0x900 - 0x894) / 4]; 112 u32 mac_con[3]; 113 u32 reserved19[(0xb00 - 0x90c) / 4]; 114 u32 macphy_con[4]; 115 u32 macphy_status; 116}; 117check_member(rk3328_grf_regs, macphy_status, 0xb10); 118 119struct rk3328_sgrf_regs { 120 u32 soc_con[6]; 121 u32 reserved0[(0x100 - 0x18) / 4]; 122 u32 dmac_con[6]; 123 u32 reserved1[(0x180 - 0x118) / 4]; 124 u32 fast_boot_addr; 125 u32 reserved2[(0x200 - 0x184) / 4]; 126 u32 chip_fuse_con; 127 u32 reserved3[(0x280 - 0x204) / 4]; 128 u32 hdcp_key_reg[8]; 129 u32 hdcp_key_access_mask; 130}; 131check_member(rk3328_sgrf_regs, hdcp_key_access_mask, 0x2a0); 132 133#endif /* __SOC_ROCKCHIP_RK3328_GRF_H__ */ 134