LXR uboot/arch/arm/mach-omap2/omap5/hwinit.c

   1// SPDX-License-Identifier: GPL-2.0+
   2/*
   3 *
   4 * Functions for omap5 based boards.
   5 *
   6 * (C) Copyright 2011
   7 * Texas Instruments, <www.ti.com>
   8 *
   9 * Author :
  10 *      Aneesh V        <aneesh@ti.com>
  11 *      Steve Sakoman   <steve@sakoman.com>
  12 *      Sricharan       <r.sricharan@ti.com>
  13 */
  14#include <common.h>
  15#include <palmas.h>
  16#include <asm/armv7.h>
  17#include <asm/arch/cpu.h>
  18#include <asm/arch/sys_proto.h>
  19#include <asm/arch/clock.h>
  20#include <linux/sizes.h>
  21#include <asm/utils.h>
  22#include <asm/arch/gpio.h>
  23#include <asm/emif.h>
  24#include <asm/omap_common.h>
  25
  26u32 *const omap_si_rev = (u32 *)OMAP_SRAM_SCRATCH_OMAP_REV;
  27
  28#ifndef CONFIG_DM_GPIO
  29static struct gpio_bank gpio_bank_54xx[8] = {
  30        { (void *)OMAP54XX_GPIO1_BASE },
  31        { (void *)OMAP54XX_GPIO2_BASE },
  32        { (void *)OMAP54XX_GPIO3_BASE },
  33        { (void *)OMAP54XX_GPIO4_BASE },
  34        { (void *)OMAP54XX_GPIO5_BASE },
  35        { (void *)OMAP54XX_GPIO6_BASE },
  36        { (void *)OMAP54XX_GPIO7_BASE },
  37        { (void *)OMAP54XX_GPIO8_BASE },
  38};
  39
  40const struct gpio_bank *const omap_gpio_bank = gpio_bank_54xx;
  41#endif
  42
  43void do_set_mux32(u32 base, struct pad_conf_entry const *array, int size)
  44{
  45        int i;
  46        struct pad_conf_entry *pad = (struct pad_conf_entry *)array;
  47
  48        for (i = 0; i < size; i++, pad++)
  49                writel(pad->val, base + pad->offset);
  50}
  51
  52#ifdef CONFIG_SPL_BUILD
  53/* LPDDR2 specific IO settings */
  54static void io_settings_lpddr2(void)
  55{
  56        const struct ctrl_ioregs *ioregs;
  57
  58        get_ioregs(&ioregs);
  59        writel(ioregs->ctrl_ddrch, (*ctrl)->control_ddrch1_0);
  60        writel(ioregs->ctrl_ddrch, (*ctrl)->control_ddrch1_1);
  61        writel(ioregs->ctrl_ddrch, (*ctrl)->control_ddrch2_0);
  62        writel(ioregs->ctrl_ddrch, (*ctrl)->control_ddrch2_1);
  63        writel(ioregs->ctrl_lpddr2ch, (*ctrl)->control_lpddr2ch1_0);
  64        writel(ioregs->ctrl_lpddr2ch, (*ctrl)->control_lpddr2ch1_1);
  65        writel(ioregs->ctrl_ddrio_0, (*ctrl)->control_ddrio_0);
  66        writel(ioregs->ctrl_ddrio_1, (*ctrl)->control_ddrio_1);
  67        writel(ioregs->ctrl_ddrio_2, (*ctrl)->control_ddrio_2);
  68}
  69
  70/* DDR3 specific IO settings */
  71static void io_settings_ddr3(void)
  72{
  73        u32 io_settings = 0;
  74        const struct ctrl_ioregs *ioregs;
  75
  76        get_ioregs(&ioregs);
  77        writel(ioregs->ctrl_ddr3ch, (*ctrl)->control_ddr3ch1_0);
  78        writel(ioregs->ctrl_ddrch, (*ctrl)->control_ddrch1_0);
  79        writel(ioregs->ctrl_ddrch, (*ctrl)->control_ddrch1_1);
  80
  81        writel(ioregs->ctrl_ddr3ch, (*ctrl)->control_ddr3ch2_0);
  82        writel(ioregs->ctrl_ddrch, (*ctrl)->control_ddrch2_0);
  83        writel(ioregs->ctrl_ddrch, (*ctrl)->control_ddrch2_1);
  84
  85        writel(ioregs->ctrl_ddrio_0, (*ctrl)->control_ddrio_0);
  86        writel(ioregs->ctrl_ddrio_1, (*ctrl)->control_ddrio_1);
  87
  88        if (!is_dra7xx()) {
  89                writel(ioregs->ctrl_ddrio_2, (*ctrl)->control_ddrio_2);
  90                writel(ioregs->ctrl_lpddr2ch, (*ctrl)->control_lpddr2ch1_1);
  91        }
  92
  93        /* omap5432 does not use lpddr2 */
  94        writel(ioregs->ctrl_lpddr2ch, (*ctrl)->control_lpddr2ch1_0);
  95
  96        writel(ioregs->ctrl_emif_sdram_config_ext,
  97               (*ctrl)->control_emif1_sdram_config_ext);
  98        if (!is_dra72x())
  99                writel(ioregs->ctrl_emif_sdram_config_ext,
 100                       (*ctrl)->control_emif2_sdram_config_ext);
 101
 102        if (is_omap54xx()) {
 103                /* Disable DLL select */
 104                io_settings = (readl((*ctrl)->control_port_emif1_sdram_config)
 105                                                        & 0xFFEFFFFF);
 106                writel(io_settings,
 107                        (*ctrl)->control_port_emif1_sdram_config);
 108
 109                io_settings = (readl((*ctrl)->control_port_emif2_sdram_config)
 110                                                        & 0xFFEFFFFF);
 111                writel(io_settings,
 112                        (*ctrl)->control_port_emif2_sdram_config);
 113        } else {
 114                writel(ioregs->ctrl_ddr_ctrl_ext_0,
 115                                (*ctrl)->control_ddr_control_ext_0);
 116        }
 117}
 118
 119/*
 120 * Some tuning of IOs for optimal power and performance
 121 */
 122void do_io_settings(void)
 123{
 124        u32 io_settings = 0, mask = 0;
 125        struct emif_reg_struct *emif = (struct emif_reg_struct *)EMIF1_BASE;
 126
 127        /* Impedance settings EMMC, C2C 1,2, hsi2 */
 128        mask = (ds_mask << 2) | (ds_mask << 8) |
 129                (ds_mask << 16) | (ds_mask << 18);
 130        io_settings = readl((*ctrl)->control_smart1io_padconf_0) &
 131                                (~mask);
 132        io_settings |= (ds_60_ohm << 8) | (ds_45_ohm << 16) |
 133                        (ds_45_ohm << 18) | (ds_60_ohm << 2);
 134        writel(io_settings, (*ctrl)->control_smart1io_padconf_0);
 135
 136        /* Impedance settings Mcspi2 */
 137        mask = (ds_mask << 30);
 138        io_settings = readl((*ctrl)->control_smart1io_padconf_1) &
 139                        (~mask);
 140        io_settings |= (ds_60_ohm << 30);
 141        writel(io_settings, (*ctrl)->control_smart1io_padconf_1);
 142
 143        /* Impedance settings C2C 3,4 */
 144        mask = (ds_mask << 14) | (ds_mask << 16);
 145        io_settings = readl((*ctrl)->control_smart1io_padconf_2) &
 146                        (~mask);
 147        io_settings |= (ds_45_ohm << 14) | (ds_45_ohm << 16);
 148        writel(io_settings, (*ctrl)->control_smart1io_padconf_2);
 149
 150        /* Slew rate settings EMMC, C2C 1,2 */
 151        mask = (sc_mask << 8) | (sc_mask << 16) | (sc_mask << 18);
 152        io_settings = readl((*ctrl)->control_smart2io_padconf_0) &
 153                        (~mask);
 154        io_settings |= (sc_fast << 8) | (sc_na << 16) | (sc_na << 18);
 155        writel(io_settings, (*ctrl)->control_smart2io_padconf_0);
 156
 157        /* Slew rate settings hsi2, Mcspi2 */
 158        mask = (sc_mask << 24) | (sc_mask << 28);
 159        io_settings = readl((*ctrl)->control_smart2io_padconf_1) &
 160                        (~mask);
 161        io_settings |= (sc_fast << 28) | (sc_fast << 24);
 162        writel(io_settings, (*ctrl)->control_smart2io_padconf_1);
 163
 164        /* Slew rate settings C2C 3,4 */
 165        mask = (sc_mask << 16) | (sc_mask << 18);
 166        io_settings = readl((*ctrl)->control_smart2io_padconf_2) &
 167                        (~mask);
 168        io_settings |= (sc_na << 16) | (sc_na << 18);
 169        writel(io_settings, (*ctrl)->control_smart2io_padconf_2);
 170
 171        /* impedance and slew rate settings for usb */
 172        mask = (usb_i_mask << 29) | (usb_i_mask << 26) | (usb_i_mask << 23) |
 173                (usb_i_mask << 20) | (usb_i_mask << 17) | (usb_i_mask << 14);
 174        io_settings = readl((*ctrl)->control_smart3io_padconf_1) &
 175                        (~mask);
 176        io_settings |= (ds_60_ohm << 29) | (ds_60_ohm << 26) |
 177                       (ds_60_ohm << 23) | (sc_fast << 20) |
 178                       (sc_fast << 17) | (sc_fast << 14);
 179        writel(io_settings, (*ctrl)->control_smart3io_padconf_1);
 180
 181        if (emif_sdram_type(emif->emif_sdram_config) == EMIF_SDRAM_TYPE_LPDDR2)
 182                io_settings_lpddr2();
 183        else
 184                io_settings_ddr3();
 185}
 186
 187static const struct srcomp_params srcomp_parameters[NUM_SYS_CLKS] = {
 188        {0x45, 0x1},    /* 12 MHz   */
 189        {-1, -1},       /* 13 MHz   */
 190        {0x63, 0x2},    /* 16.8 MHz */
 191        {0x57, 0x2},    /* 19.2 MHz */
 192        {0x20, 0x1},    /* 26 MHz   */
 193        {-1, -1},       /* 27 MHz   */
 194        {0x41, 0x3}     /* 38.4 MHz */
 195};
 196
 197void srcomp_enable(void)
 198{
 199        u32 srcomp_value, mul_factor, div_factor, clk_val, i;
 200        u32 sysclk_ind  = get_sys_clk_index();
 201        u32 omap_rev    = omap_revision();
 202
 203        if (!is_omap54xx())
 204                return;
 205
 206        mul_factor = srcomp_parameters[sysclk_ind].multiply_factor;
 207        div_factor = srcomp_parameters[sysclk_ind].divide_factor;
 208
 209        for (i = 0; i < 4; i++) {
 210                srcomp_value = readl((*ctrl)->control_srcomp_north_side + i*4);
 211                srcomp_value &=
 212                        ~(MULTIPLY_FACTOR_XS_MASK | DIVIDE_FACTOR_XS_MASK);
 213                srcomp_value |= (mul_factor << MULTIPLY_FACTOR_XS_SHIFT) |
 214                        (div_factor << DIVIDE_FACTOR_XS_SHIFT);
 215                writel(srcomp_value, (*ctrl)->control_srcomp_north_side + i*4);
 216        }
 217
 218        if ((omap_rev == OMAP5430_ES1_0) || (omap_rev == OMAP5432_ES1_0)) {
 219                clk_val = readl((*prcm)->cm_coreaon_io_srcomp_clkctrl);
 220                clk_val |= OPTFCLKEN_SRCOMP_FCLK_MASK;
 221                writel(clk_val, (*prcm)->cm_coreaon_io_srcomp_clkctrl);
 222
 223                for (i = 0; i < 4; i++) {
 224                        srcomp_value =
 225                                readl((*ctrl)->control_srcomp_north_side + i*4);
 226                        srcomp_value &= ~PWRDWN_XS_MASK;
 227                        writel(srcomp_value,
 228                               (*ctrl)->control_srcomp_north_side + i*4);
 229
 230                        while (((readl((*ctrl)->control_srcomp_north_side + i*4)
 231                                & SRCODE_READ_XS_MASK) >>
 232                                SRCODE_READ_XS_SHIFT) == 0)
 233                                ;
 234
 235                        srcomp_value =
 236                                readl((*ctrl)->control_srcomp_north_side + i*4);
 237                        srcomp_value &= ~OVERRIDE_XS_MASK;
 238                        writel(srcomp_value,
 239                               (*ctrl)->control_srcomp_north_side + i*4);
 240                }
 241        } else {
 242                srcomp_value = readl((*ctrl)->control_srcomp_east_side_wkup);
 243                srcomp_value &= ~(MULTIPLY_FACTOR_XS_MASK |
 244                                  DIVIDE_FACTOR_XS_MASK);
 245                srcomp_value |= (mul_factor << MULTIPLY_FACTOR_XS_SHIFT) |
 246                                (div_factor << DIVIDE_FACTOR_XS_SHIFT);
 247                writel(srcomp_value, (*ctrl)->control_srcomp_east_side_wkup);
 248
 249                for (i = 0; i < 4; i++) {
 250                        srcomp_value =
 251                                readl((*ctrl)->control_srcomp_north_side + i*4);
 252                        srcomp_value |= SRCODE_OVERRIDE_SEL_XS_MASK;
 253                        writel(srcomp_value,
 254                               (*ctrl)->control_srcomp_north_side + i*4);
 255
 256                        srcomp_value =
 257                                readl((*ctrl)->control_srcomp_north_side + i*4);
 258                        srcomp_value &= ~OVERRIDE_XS_MASK;
 259                        writel(srcomp_value,
 260                               (*ctrl)->control_srcomp_north_side + i*4);
 261                }
 262
 263                srcomp_value =
 264                        readl((*ctrl)->control_srcomp_east_side_wkup);
 265                srcomp_value |= SRCODE_OVERRIDE_SEL_XS_MASK;
 266                writel(srcomp_value, (*ctrl)->control_srcomp_east_side_wkup);
 267
 268                srcomp_value =
 269                        readl((*ctrl)->control_srcomp_east_side_wkup);
 270                srcomp_value &= ~OVERRIDE_XS_MASK;
 271                writel(srcomp_value, (*ctrl)->control_srcomp_east_side_wkup);
 272
 273                clk_val = readl((*prcm)->cm_coreaon_io_srcomp_clkctrl);
 274                clk_val |= OPTFCLKEN_SRCOMP_FCLK_MASK;
 275                writel(clk_val, (*prcm)->cm_coreaon_io_srcomp_clkctrl);
 276
 277                clk_val = readl((*prcm)->cm_wkupaon_io_srcomp_clkctrl);
 278                clk_val |= OPTFCLKEN_SRCOMP_FCLK_MASK;
 279                writel(clk_val, (*prcm)->cm_wkupaon_io_srcomp_clkctrl);
 280
 281                for (i = 0; i < 4; i++) {
 282                        while (((readl((*ctrl)->control_srcomp_north_side + i*4)
 283                                & SRCODE_READ_XS_MASK) >>
 284                                SRCODE_READ_XS_SHIFT) == 0)
 285                                ;
 286
 287                        srcomp_value =
 288                                readl((*ctrl)->control_srcomp_north_side + i*4);
 289                        srcomp_value &= ~SRCODE_OVERRIDE_SEL_XS_MASK;
 290                        writel(srcomp_value,
 291                               (*ctrl)->control_srcomp_north_side + i*4);
 292                }
 293
 294                while (((readl((*ctrl)->control_srcomp_east_side_wkup) &
 295                        SRCODE_READ_XS_MASK) >> SRCODE_READ_XS_SHIFT) == 0)
 296                        ;
 297
 298                srcomp_value =
 299                        readl((*ctrl)->control_srcomp_east_side_wkup);
 300                srcomp_value &= ~SRCODE_OVERRIDE_SEL_XS_MASK;
 301                writel(srcomp_value, (*ctrl)->control_srcomp_east_side_wkup);
 302        }
 303}
 304#endif
 305
 306void config_data_eye_leveling_samples(u32 emif_base)
 307{
 308        const struct ctrl_ioregs *ioregs;
 309
 310        get_ioregs(&ioregs);
 311
 312        /*EMIF_SDRAM_CONFIG_EXT-Read data eye leveling no of samples =4*/
 313        if (emif_base == EMIF1_BASE)
 314                writel(ioregs->ctrl_emif_sdram_config_ext_final,
 315                       (*ctrl)->control_emif1_sdram_config_ext);
 316        else if (emif_base == EMIF2_BASE)
 317                writel(ioregs->ctrl_emif_sdram_config_ext_final,
 318                       (*ctrl)->control_emif2_sdram_config_ext);
 319}
 320
 321void init_cpu_configuration(void)
 322{
 323        u32 l2actlr;
 324
 325        asm volatile("mrc p15, 1, %0, c15, c0, 0" : "=r"(l2actlr));
 326        /*
 327         * L2ACTLR: Ensure to enable the following:
 328         * 3: Disable clean/evict push to external
 329         * 4: Disable WriteUnique and WriteLineUnique transactions from master
 330         * 8: Disable DVM/CMO message broadcast
 331         */
 332        l2actlr |= 0x118;
 333        omap_smc1(OMAP5_SERVICE_L2ACTLR_SET, l2actlr);
 334}
 335
 336void init_omap_revision(void)
 337{
 338        /*
 339         * For some of the ES2/ES1 boards ID_CODE is not reliable:
 340         * Also, ES1 and ES2 have different ARM revisions
 341         * So use ARM revision for identification
 342         */
 343        unsigned int rev = cortex_rev();
 344
 345        switch (readl(CONTROL_ID_CODE)) {
 346        case OMAP5430_CONTROL_ID_CODE_ES1_0:
 347                *omap_si_rev = OMAP5430_ES1_0;
 348                if (rev == MIDR_CORTEX_A15_R2P2)
 349                        *omap_si_rev = OMAP5430_ES2_0;
 350                break;
 351        case OMAP5432_CONTROL_ID_CODE_ES1_0:
 352                *omap_si_rev = OMAP5432_ES1_0;
 353                if (rev == MIDR_CORTEX_A15_R2P2)
 354                        *omap_si_rev = OMAP5432_ES2_0;
 355                break;
 356        case OMAP5430_CONTROL_ID_CODE_ES2_0:
 357                *omap_si_rev = OMAP5430_ES2_0;
 358                break;
 359        case OMAP5432_CONTROL_ID_CODE_ES2_0:
 360                *omap_si_rev = OMAP5432_ES2_0;
 361                break;
 362        case DRA762_CONTROL_ID_CODE_ES1_0:
 363                *omap_si_rev = DRA762_ES1_0;
 364                break;
 365        case DRA752_CONTROL_ID_CODE_ES1_0:
 366                *omap_si_rev = DRA752_ES1_0;
 367                break;
 368        case DRA752_CONTROL_ID_CODE_ES1_1:
 369                *omap_si_rev = DRA752_ES1_1;
 370                break;
 371        case DRA752_CONTROL_ID_CODE_ES2_0:
 372                *omap_si_rev = DRA752_ES2_0;
 373                break;
 374        case DRA722_CONTROL_ID_CODE_ES1_0:
 375                *omap_si_rev = DRA722_ES1_0;
 376                break;
 377        case DRA722_CONTROL_ID_CODE_ES2_0:
 378                *omap_si_rev = DRA722_ES2_0;
 379                break;
 380        case DRA722_CONTROL_ID_CODE_ES2_1:
 381                *omap_si_rev = DRA722_ES2_1;
 382                break;
 383        default:
 384                *omap_si_rev = OMAP5430_SILICON_ID_INVALID;
 385        }
 386        init_cpu_configuration();
 387}
 388
 389void init_package_revision(void)
 390{
 391        unsigned int die_id[4] = { 0 };
 392        u8 package;
 393
 394        omap_die_id(die_id);
 395        package = (die_id[2] >> 16) & 0x3;
 396
 397        if (is_dra76x()) {
 398                switch (package) {
 399                case DRA762_ABZ_PACKAGE:
 400                        *omap_si_rev = DRA762_ABZ_ES1_0;
 401                        break;
 402                case DRA762_ACD_PACKAGE:
 403                default:
 404                        *omap_si_rev = DRA762_ACD_ES1_0;
 405                        break;
 406                }
 407        }
 408}
 409
 410void omap_die_id(unsigned int *die_id)
 411{
 412        die_id[0] = readl((*ctrl)->control_std_fuse_die_id_0);
 413        die_id[1] = readl((*ctrl)->control_std_fuse_die_id_1);
 414        die_id[2] = readl((*ctrl)->control_std_fuse_die_id_2);
 415        die_id[3] = readl((*ctrl)->control_std_fuse_die_id_3);
 416}
 417
 418void reset_cpu(ulong ignored)
 419{
 420        u32 omap_rev = omap_revision();
 421
 422        /*
 423         * WARM reset is not functional in case of OMAP5430 ES1.0 soc.
 424         * So use cold reset in case instead.
 425         */
 426        if (omap_rev == OMAP5430_ES1_0)
 427                writel(PRM_RSTCTRL_RESET << 0x1, (*prcm)->prm_rstctrl);
 428        else
 429                writel(PRM_RSTCTRL_RESET, (*prcm)->prm_rstctrl);
 430}
 431
 432u32 warm_reset(void)
 433{
 434        return readl((*prcm)->prm_rstst) & PRM_RSTST_WARM_RESET_MASK;
 435}
 436
 437void setup_warmreset_time(void)
 438{
 439        u32 rst_time, rst_val;
 440
 441        /*
 442         * MAX value for PRM_RSTTIME[9:0]RSTTIME1 stored is 0x3ff.
 443         * 0x3ff is in the no of FUNC_32K_CLK cycles. Converting cycles
 444         * into microsec and passing the value.
 445         */
 446        rst_time = usec_to_32k(CONFIG_OMAP_PLATFORM_RESET_TIME_MAX_USEC)
 447                << RSTTIME1_SHIFT;
 448
 449        if (rst_time > RSTTIME1_MASK)
 450                rst_time = RSTTIME1_MASK;
 451
 452        rst_val = readl((*prcm)->prm_rsttime) & ~RSTTIME1_MASK;
 453        rst_val |= rst_time;
 454        writel(rst_val, (*prcm)->prm_rsttime);
 455}
 456
 457void v7_arch_cp15_set_l2aux_ctrl(u32 l2auxctrl, u32 cpu_midr,
 458                                 u32 cpu_rev_comb, u32 cpu_variant,
 459                                 u32 cpu_rev)
 460{
 461        omap_smc1(OMAP5_SERVICE_L2ACTLR_SET, l2auxctrl);
 462}
 463
 464void v7_arch_cp15_set_acr(u32 acr, u32 cpu_midr, u32 cpu_rev_comb,
 465                          u32 cpu_variant, u32 cpu_rev)
 466{
 467
 468#ifdef CONFIG_ARM_ERRATA_801819
 469        /*
 470         * DRA72x processors are uniprocessors and DONOT have
 471         * ACP (Accelerator Coherency Port) hooked to ACE (AXI Coherency
 472         * Extensions) Hence the erratum workaround is not applicable for
 473         * DRA72x processors.
 474         */
 475        if (is_dra72x())
 476                acr &= ~((0x3 << 23) | (0x3 << 25));
 477#endif
 478        omap_smc1(OMAP5_SERVICE_ACR_SET, acr);
 479}
 480
 481#if defined(CONFIG_PALMAS_POWER)
 482__weak void board_mmc_poweron_ldo(uint voltage)
 483{
 484        palmas_mmc1_poweron_ldo(LDO1_VOLTAGE, LDO1_CTRL, voltage);
 485}
 486
 487void vmmc_pbias_config(uint voltage)
 488{
 489        u32 value = 0;
 490
 491        value = readl((*ctrl)->control_pbias);
 492        value &= ~SDCARD_PWRDNZ;
 493        writel(value, (*ctrl)->control_pbias);
 494        udelay(10); /* wait 10 us */
 495        value &= ~SDCARD_BIAS_PWRDNZ;
 496        writel(value, (*ctrl)->control_pbias);
 497
 498        board_mmc_poweron_ldo(voltage);
 499
 500        value = readl((*ctrl)->control_pbias);
 501        value |= SDCARD_BIAS_PWRDNZ;
 502        writel(value, (*ctrl)->control_pbias);
 503        udelay(150); /* wait 150 us */
 504        value |= SDCARD_PWRDNZ;
 505        writel(value, (*ctrl)->control_pbias);
 506        udelay(150); /* wait 150 us */
 507}
 508#endif
 509