uboot/arch/arm/mach-socfpga/scan_manager.c
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   1// SPDX-License-Identifier: GPL-2.0+
   2/*
   3 *  Copyright (C) 2013 Altera Corporation <www.altera.com>
   4 */
   5
   6#include <common.h>
   7#include <errno.h>
   8#include <asm/io.h>
   9#include <asm/arch/freeze_controller.h>
  10#include <asm/arch/scan_manager.h>
  11#include <asm/arch/system_manager.h>
  12
  13/*
  14 * Maximum polling loop to wait for IO scan chain engine becomes idle
  15 * to prevent infinite loop. It is important that this is NOT changed
  16 * to delay using timer functions, since at the time this function is
  17 * called, timer might not yet be inited.
  18 */
  19#define SCANMGR_MAX_DELAY               100
  20
  21/*
  22 * Maximum length of TDI_TDO packet payload is 128 bits,
  23 * represented by (length - 1) in TDI_TDO header.
  24 */
  25#define TDI_TDO_MAX_PAYLOAD             127
  26
  27#define SCANMGR_STAT_ACTIVE             (1 << 31)
  28#define SCANMGR_STAT_WFIFOCNT_MASK      0x70000000
  29
  30static const struct socfpga_scan_manager *scan_manager_base =
  31                (void *)(SOCFPGA_SCANMGR_ADDRESS);
  32static const struct socfpga_freeze_controller *freeze_controller_base =
  33                (void *)(SOCFPGA_SYSMGR_ADDRESS + SYSMGR_FRZCTRL_ADDRESS);
  34static struct socfpga_system_manager *sys_mgr_base =
  35        (struct socfpga_system_manager *)SOCFPGA_SYSMGR_ADDRESS;
  36
  37/**
  38 * scan_chain_engine_is_idle() - Check if the JTAG scan chain is idle
  39 * @max_iter:   Maximum number of iterations to wait for idle
  40 *
  41 * Function to check IO scan chain engine status and wait if the engine is
  42 * is active. Poll the IO scan chain engine till maximum iteration reached.
  43 */
  44static u32 scan_chain_engine_is_idle(u32 max_iter)
  45{
  46        const u32 mask = SCANMGR_STAT_ACTIVE | SCANMGR_STAT_WFIFOCNT_MASK;
  47        u32 status;
  48
  49        /* Poll the engine until the scan engine is inactive. */
  50        do {
  51                status = readl(&scan_manager_base->stat);
  52                if (!(status & mask))
  53                        return 0;
  54        } while (max_iter--);
  55
  56        return -ETIMEDOUT;
  57}
  58
  59#define JTAG_BP_INSN            (1 << 0)
  60#define JTAG_BP_TMS             (1 << 1)
  61#define JTAG_BP_PAYLOAD         (1 << 2)
  62#define JTAG_BP_2BYTE           (1 << 3)
  63#define JTAG_BP_4BYTE           (1 << 4)
  64
  65/**
  66 * scan_mgr_jtag_io() - Access the JTAG chain
  67 * @flags:      Control flags, used to configure the action on the JTAG
  68 * @iarg:       Instruction argument
  69 * @parg:       Payload argument or data
  70 *
  71 * Perform I/O on the JTAG chain
  72 */
  73static void scan_mgr_jtag_io(const u32 flags, const u8 iarg, const u32 parg)
  74{
  75        u32 data = parg;
  76
  77        if (flags & JTAG_BP_INSN) {     /* JTAG instruction */
  78                /*
  79                 * The SCC JTAG register is LSB first, so make
  80                 * space for the instruction at the LSB.
  81                 */
  82                data <<= 8;
  83                if (flags & JTAG_BP_TMS) {
  84                        data |= (0 << 7);       /* TMS instruction. */
  85                        data |= iarg & 0x3f;    /* TMS arg is 6 bits. */
  86                        if (flags & JTAG_BP_PAYLOAD)
  87                                data |= (1 << 6);
  88                } else {
  89                        data |= (1 << 7);       /* TDI/TDO instruction. */
  90                        data |= iarg & 0xf;     /* TDI/TDO arg is 4 bits. */
  91                        if (flags & JTAG_BP_PAYLOAD)
  92                                data |= (1 << 4);
  93                }
  94        }
  95
  96        if (flags & JTAG_BP_4BYTE)
  97                writel(data, &scan_manager_base->fifo_quad_byte);
  98        else if (flags & JTAG_BP_2BYTE)
  99                writel(data & 0xffff, &scan_manager_base->fifo_double_byte);
 100        else
 101                writel(data & 0xff, &scan_manager_base->fifo_single_byte);
 102}
 103
 104/**
 105 * scan_mgr_jtag_insn_data() - Send JTAG instruction and data
 106 * @iarg:       Instruction argument
 107 * @data:       Associated data
 108 * @dlen:       Length of data in bits
 109 *
 110 * This function is used when programming the IO chains to submit the
 111 * instruction followed by variable length payload.
 112 */
 113static int
 114scan_mgr_jtag_insn_data(const u8 iarg, const unsigned long *data,
 115                        const unsigned int dlen)
 116{
 117        int i, j;
 118
 119        scan_mgr_jtag_io(JTAG_BP_INSN | JTAG_BP_2BYTE, iarg, dlen - 1);
 120
 121        /* 32 bits or more remain */
 122        for (i = 0; i < dlen / 32; i++)
 123                scan_mgr_jtag_io(JTAG_BP_4BYTE, 0x0, data[i]);
 124
 125        if ((dlen % 32) > 24) { /* 31...24 bits remain */
 126                scan_mgr_jtag_io(JTAG_BP_4BYTE, 0x0, data[i]);
 127        } else if (dlen % 32) { /* 24...1 bit remain */
 128                for (j = 0; j < dlen % 32; j += 8)
 129                        scan_mgr_jtag_io(0, 0x0, data[i] >> j);
 130        }
 131
 132        return scan_chain_engine_is_idle(SCANMGR_MAX_DELAY);
 133}
 134
 135/**
 136 * scan_mgr_io_scan_chain_prg() - Program HPS IO Scan Chain
 137 * @io_scan_chain_id:           IO scan chain ID
 138 */
 139static int scan_mgr_io_scan_chain_prg(const unsigned int io_scan_chain_id)
 140{
 141        u32 io_scan_chain_len_in_bits;
 142        const unsigned long *iocsr_scan_chain;
 143        unsigned int rem, idx = 0;
 144        int ret;
 145
 146        ret = iocsr_get_config_table(io_scan_chain_id, &iocsr_scan_chain,
 147                                     &io_scan_chain_len_in_bits);
 148        if (ret)
 149                return 1;
 150
 151        /*
 152         * De-assert reinit if the IO scan chain is intended for HIO. In
 153         * this, its the chain 3.
 154         */
 155        if (io_scan_chain_id == 3)
 156                clrbits_le32(&freeze_controller_base->hioctrl,
 157                             SYSMGR_FRZCTRL_HIOCTRL_DLLRST_MASK);
 158
 159        /*
 160         * Check if the scan chain engine is inactive and the
 161         * WFIFO is empty before enabling the IO scan chain
 162         */
 163        ret = scan_chain_engine_is_idle(SCANMGR_MAX_DELAY);
 164        if (ret)
 165                return ret;
 166
 167        /*
 168         * Enable IO Scan chain based on scan chain id
 169         * Note: only one chain can be enabled at a time
 170         */
 171        setbits_le32(&scan_manager_base->en, 1 << io_scan_chain_id);
 172
 173        /* Program IO scan chain. */
 174        while (io_scan_chain_len_in_bits) {
 175                if (io_scan_chain_len_in_bits > 128)
 176                        rem = 128;
 177                else
 178                        rem = io_scan_chain_len_in_bits;
 179
 180                ret = scan_mgr_jtag_insn_data(0x0, &iocsr_scan_chain[idx], rem);
 181                if (ret)
 182                        goto error;
 183                io_scan_chain_len_in_bits -= rem;
 184                idx += 4;
 185        }
 186
 187        /* Disable IO Scan chain when configuration done*/
 188        clrbits_le32(&scan_manager_base->en, 1 << io_scan_chain_id);
 189        return 0;
 190
 191error:
 192        /* Disable IO Scan chain when error detected */
 193        clrbits_le32(&scan_manager_base->en, 1 << io_scan_chain_id);
 194        return ret;
 195}
 196
 197int scan_mgr_configure_iocsr(void)
 198{
 199        int status = 0;
 200
 201        /* configure the IOCSR through scan chain */
 202        status |= scan_mgr_io_scan_chain_prg(0);
 203        status |= scan_mgr_io_scan_chain_prg(1);
 204        status |= scan_mgr_io_scan_chain_prg(2);
 205        status |= scan_mgr_io_scan_chain_prg(3);
 206        return status;
 207}
 208
 209/**
 210 * scan_mgr_get_fpga_id() - Obtain FPGA JTAG ID
 211 *
 212 * This function obtains JTAG ID from the FPGA TAP controller.
 213 */
 214u32 scan_mgr_get_fpga_id(void)
 215{
 216        const unsigned long data = 0;
 217        u32 id = 0xffffffff;
 218        int ret;
 219
 220        /* Enable HPS to talk to JTAG in the FPGA through the System Manager */
 221        writel(0x1, &sys_mgr_base->scanmgrgrp_ctrl);
 222
 223        /* Enable port 7 */
 224        writel(0x80, &scan_manager_base->en);
 225        /* write to CSW to make s2f_ntrst reset */
 226        writel(0x02, &scan_manager_base->stat);
 227
 228        /* Add a pause */
 229        mdelay(1);
 230
 231        /* write 0x00 to CSW to clear the s2f_ntrst */
 232        writel(0, &scan_manager_base->stat);
 233
 234        /*
 235         * Go to Test-Logic-Reset state.
 236         * This sets TAP controller into IDCODE mode.
 237         */
 238        scan_mgr_jtag_io(JTAG_BP_INSN | JTAG_BP_TMS, 0x1f | (1 << 5), 0x0);
 239
 240        /* Go to Run-Test/Idle -> DR-Scan -> Capture-DR -> Shift-DR state. */
 241        scan_mgr_jtag_io(JTAG_BP_INSN | JTAG_BP_TMS, 0x02 | (1 << 4), 0x0);
 242
 243        /*
 244         * Push 4 bytes of data through TDI->DR->TDO.
 245         *
 246         * Length of TDI data is 32bits (length - 1) and they are only
 247         * zeroes as we care only for TDO data.
 248         */
 249        ret = scan_mgr_jtag_insn_data(0x4, &data, 32);
 250        /* Read 32 bit from captured JTAG data. */
 251        if (!ret)
 252                id = readl(&scan_manager_base->fifo_quad_byte);
 253
 254        /* Disable all port */
 255        writel(0, &scan_manager_base->en);
 256        writel(0, &sys_mgr_base->scanmgrgrp_ctrl);
 257
 258        return id;
 259}
 260