LXR uboot/arch/arm/mach-sunxi/cpu

   1// SPDX-License-Identifier: GPL-2.0+
   2/*
   3 * (C) Copyright 2007-2011
   4 * Allwinner Technology Co., Ltd. <www.allwinnertech.com>
   5 * Tom Cubie <tangliang@allwinnertech.com>
   6 */
   7
   8#include <common.h>
   9#include <asm/io.h>
  10#include <asm/arch/cpu.h>
  11#include <asm/arch/clock.h>
  12#include <axp_pmic.h>
  13#include <errno.h>
  14
  15#ifdef CONFIG_MACH_SUN6I
  16int sunxi_get_ss_bonding_id(void)
  17{
  18        struct sunxi_ccm_reg * const ccm =
  19                (struct sunxi_ccm_reg *)SUNXI_CCM_BASE;
  20        static int bonding_id = -1;
  21
  22        if (bonding_id != -1)
  23                return bonding_id;
  24
  25        /* Enable Security System */
  26        setbits_le32(&ccm->ahb_reset0_cfg, 1 << AHB_RESET_OFFSET_SS);
  27        setbits_le32(&ccm->ahb_gate0, 1 << AHB_GATE_OFFSET_SS);
  28
  29        bonding_id = readl(SUNXI_SS_BASE);
  30        bonding_id = (bonding_id >> 16) & 0x7;
  31
  32        /* Disable Security System again */
  33        clrbits_le32(&ccm->ahb_gate0, 1 << AHB_GATE_OFFSET_SS);
  34        clrbits_le32(&ccm->ahb_reset0_cfg, 1 << AHB_RESET_OFFSET_SS);
  35
  36        return bonding_id;
  37}
  38#endif
  39
  40#ifdef CONFIG_MACH_SUN8I
  41uint sunxi_get_sram_id(void)
  42{
  43        uint id;
  44
  45        /* Unlock sram info reg, read it, relock */
  46        setbits_le32(SUNXI_SRAMC_BASE + 0x24, (1 << 15));
  47        id = readl(SUNXI_SRAMC_BASE + 0x24) >> 16;
  48        clrbits_le32(SUNXI_SRAMC_BASE + 0x24, (1 << 15));
  49
  50        return id;
  51}
  52#endif
  53
  54#ifdef CONFIG_DISPLAY_CPUINFO
  55int print_cpuinfo(void)
  56{
  57#ifdef CONFIG_MACH_SUN4I
  58        puts("CPU:   Allwinner A10 (SUN4I)\n");
  59#elif defined CONFIG_MACH_SUN5I
  60        u32 val = readl(SUNXI_SID_BASE + 0x08);
  61        switch ((val >> 12) & 0xf) {
  62        case 0: puts("CPU:   Allwinner A12 (SUN5I)\n"); break;
  63        case 3: puts("CPU:   Allwinner A13 (SUN5I)\n"); break;
  64        case 7: puts("CPU:   Allwinner A10s (SUN5I)\n"); break;
  65        default: puts("CPU:   Allwinner A1X (SUN5I)\n");
  66        }
  67#elif defined CONFIG_MACH_SUN6I
  68        switch (sunxi_get_ss_bonding_id()) {
  69        case SUNXI_SS_BOND_ID_A31:
  70                puts("CPU:   Allwinner A31 (SUN6I)\n");
  71                break;
  72        case SUNXI_SS_BOND_ID_A31S:
  73                puts("CPU:   Allwinner A31s (SUN6I)\n");
  74                break;
  75        default:
  76                printf("CPU:   Allwinner A31? (SUN6I, id: %d)\n",
  77                       sunxi_get_ss_bonding_id());
  78        }
  79#elif defined CONFIG_MACH_SUN7I
  80        puts("CPU:   Allwinner A20 (SUN7I)\n");
  81#elif defined CONFIG_MACH_SUN8I_A23
  82        printf("CPU:   Allwinner A23 (SUN8I %04x)\n", sunxi_get_sram_id());
  83#elif defined CONFIG_MACH_SUN8I_A33
  84        printf("CPU:   Allwinner A33 (SUN8I %04x)\n", sunxi_get_sram_id());
  85#elif defined CONFIG_MACH_SUN8I_A83T
  86        printf("CPU:   Allwinner A83T (SUN8I %04x)\n", sunxi_get_sram_id());
  87#elif defined CONFIG_MACH_SUN8I_H3
  88        printf("CPU:   Allwinner H3 (SUN8I %04x)\n", sunxi_get_sram_id());
  89#elif defined CONFIG_MACH_SUN8I_R40
  90        printf("CPU:   Allwinner R40 (SUN8I %04x)\n", sunxi_get_sram_id());
  91#elif defined CONFIG_MACH_SUN8I_V3S
  92        printf("CPU:   Allwinner V3s (SUN8I %04x)\n", sunxi_get_sram_id());
  93#elif defined CONFIG_MACH_SUN9I
  94        puts("CPU:   Allwinner A80 (SUN9I)\n");
  95#elif defined CONFIG_MACH_SUN50I
  96        puts("CPU:   Allwinner A64 (SUN50I)\n");
  97#elif defined CONFIG_MACH_SUN50I_H5
  98        puts("CPU:   Allwinner H5 (SUN50I)\n");
  99#elif defined CONFIG_MACH_SUN50I_H6
 100        puts("CPU:   Allwinner H6 (SUN50I)\n");
 101#else
 102#warning Please update cpu_info.c with correct CPU information
 103        puts("CPU:   SUNXI Family\n");
 104#endif
 105        return 0;
 106}
 107#endif
 108
 109#ifdef CONFIG_MACH_SUN8I_H3
 110
 111#define SIDC_PRCTL 0x40
 112#define SIDC_RDKEY 0x60
 113
 114#define SIDC_OP_LOCK 0xAC
 115
 116uint32_t sun8i_efuse_read(uint32_t offset)
 117{
 118        uint32_t reg_val;
 119
 120        reg_val = readl(SUNXI_SIDC_BASE + SIDC_PRCTL);
 121        reg_val &= ~(((0x1ff) << 16) | 0x3);
 122        reg_val |= (offset << 16);
 123        writel(reg_val, SUNXI_SIDC_BASE + SIDC_PRCTL);
 124
 125        reg_val &= ~(((0xff) << 8) | 0x3);
 126        reg_val |= (SIDC_OP_LOCK << 8) | 0x2;
 127        writel(reg_val, SUNXI_SIDC_BASE + SIDC_PRCTL);
 128
 129        while (readl(SUNXI_SIDC_BASE + SIDC_PRCTL) & 0x2);
 130
 131        reg_val &= ~(((0x1ff) << 16) | ((0xff) << 8) | 0x3);
 132        writel(reg_val, SUNXI_SIDC_BASE + SIDC_PRCTL);
 133
 134        reg_val = readl(SUNXI_SIDC_BASE + SIDC_RDKEY);
 135        return reg_val;
 136}
 137#endif
 138
 139int sunxi_get_sid(unsigned int *sid)
 140{
 141#ifdef CONFIG_AXP221_POWER
 142        return axp_get_sid(sid);
 143#elif defined CONFIG_MACH_SUN8I_H3
 144        /*
 145         * H3 SID controller has a bug, which makes the initial value of
 146         * SUNXI_SID_BASE at boot wrong.
 147         * Read the value directly from SID controller, in order to get
 148         * the correct value, and also refresh the wrong value at
 149         * SUNXI_SID_BASE.
 150         */
 151        int i;
 152
 153        for (i = 0; i< 4; i++)
 154                sid[i] = sun8i_efuse_read(i * 4);
 155
 156        return 0;
 157#elif defined SUNXI_SID_BASE
 158        int i;
 159
 160        for (i = 0; i< 4; i++)
 161                sid[i] = readl((ulong)SUNXI_SID_BASE + 4 * i);
 162
 163        return 0;
 164#else
 165        return -ENODEV;
 166#endif
 167}
 168