1/* SPDX-License-Identifier: GPL-2.0 */ 2/* 3 * From Coreboot file of same name 4 * 5 * Copyright (C) 2007-2009 coresystems GmbH 6 * 2012 secunet Security Networks AG 7 */ 8 9#ifndef _ASM_SPEEDSTEP_H 10#define _ASM_SPEEDSTEP_H 11 12/* Magic value used to locate speedstep configuration in the device tree */ 13#define SPEEDSTEP_APIC_MAGIC 0xACAC 14 15/* MWAIT coordination I/O base address. This must match 16 * the \_PR_.CPU0 PM base address. 17 */ 18#define PMB0_BASE 0x510 19 20/* PMB1: I/O port that triggers SMI once cores are in the same state. 21 * See CSM Trigger, at PMG_CST_CONFIG_CONTROL[6:4] 22 */ 23#define PMB1_BASE 0x800 24 25struct sst_state { 26 uint8_t dynfsb:1; /* whether this is SLFM */ 27 uint8_t nonint:1; /* add .5 to ratio */ 28 uint8_t ratio:6; 29 uint8_t vid; 30 uint8_t is_turbo; 31 uint8_t is_slfm; 32 uint32_t power; 33}; 34#define SPEEDSTEP_RATIO_SHIFT 8 35#define SPEEDSTEP_RATIO_DYNFSB_SHIFT (7 + SPEEDSTEP_RATIO_SHIFT) 36#define SPEEDSTEP_RATIO_DYNFSB (1 << SPEEDSTEP_RATIO_DYNFSB_SHIFT) 37#define SPEEDSTEP_RATIO_NONINT_SHIFT (6 + SPEEDSTEP_RATIO_SHIFT) 38#define SPEEDSTEP_RATIO_NONINT (1 << SPEEDSTEP_RATIO_NONINT_SHIFT) 39#define SPEEDSTEP_RATIO_VALUE_MASK (0x1f << SPEEDSTEP_RATIO_SHIFT) 40#define SPEEDSTEP_VID_MASK 0x3f 41#define SPEEDSTEP_STATE_FROM_MSR(val, mask) ((struct sst_state){ \ 42 0, /* dynfsb won't be read. */ \ 43 ((val & mask) & SPEEDSTEP_RATIO_NONINT) ? 1 : 0, \ 44 (((val & mask) & SPEEDSTEP_RATIO_VALUE_MASK) \ 45 >> SPEEDSTEP_RATIO_SHIFT), \ 46 (val & mask) & SPEEDSTEP_VID_MASK, \ 47 0, /* not turbo by default */ \ 48 0, /* not slfm by default */ \ 49 0 /* power is hardcoded in software. */ \ 50 }) 51#define SPEEDSTEP_ENCODE_STATE(state) ( \ 52 ((uint16_t)(state).dynfsb << SPEEDSTEP_RATIO_DYNFSB_SHIFT) | \ 53 ((uint16_t)(state).nonint << SPEEDSTEP_RATIO_NONINT_SHIFT) | \ 54 ((uint16_t)(state).ratio << SPEEDSTEP_RATIO_SHIFT) | \ 55 ((uint16_t)(state).vid & SPEEDSTEP_VID_MASK)) 56#define SPEEDSTEP_DOUBLE_RATIO(state) ( \ 57 ((uint8_t)(state).ratio * 2) + (state).nonint) 58 59struct sst_params { 60 struct sst_state slfm; 61 struct sst_state min; 62 struct sst_state max; 63 struct sst_state turbo; 64}; 65 66/* Looking at core2's spec, the highest normal bus ratio for an eist enabled 67 processor is 14, the lowest is always 6. This makes 5 states with the 68 minimal step width of 2. With turbo mode and super LFM we have at most 7. */ 69#define SPEEDSTEP_MAX_NORMAL_STATES 5 70#define SPEEDSTEP_MAX_STATES (SPEEDSTEP_MAX_NORMAL_STATES + 2) 71struct sst_table { 72 /* Table of p-states for EMTTM and ACPI by decreasing performance. */ 73 struct sst_state states[SPEEDSTEP_MAX_STATES]; 74 int num_states; 75}; 76 77void speedstep_gen_pstates(struct sst_table *); 78 79#define SPEEDSTEP_MAX_POWER_YONAH 31000 80#define SPEEDSTEP_MIN_POWER_YONAH 13100 81#define SPEEDSTEP_MAX_POWER_MEROM 35000 82#define SPEEDSTEP_MIN_POWER_MEROM 25000 83#define SPEEDSTEP_SLFM_POWER_MEROM 12000 84#define SPEEDSTEP_MAX_POWER_PENRYN 35000 85#define SPEEDSTEP_MIN_POWER_PENRYN 15000 86#define SPEEDSTEP_SLFM_POWER_PENRYN 12000 87 88#endif 89