1
2
3
4
5
6#include <common.h>
7#include <asm/processor.h>
8#include <asm/mmu.h>
9#include <asm/cache.h>
10#include <asm/immap_85xx.h>
11#include <asm/io.h>
12#include <miiphy.h>
13#include <linux/libfdt.h>
14#include <fdt_support.h>
15#include <fsl_mdio.h>
16#include <tsec.h>
17#include <jffs2/load_kernel.h>
18#include <mtd_node.h>
19#include <flash.h>
20#include <netdev.h>
21
22
23DECLARE_GLOBAL_DATA_PTR;
24
25int board_early_init_f(void)
26{
27 ccsr_gur_t *gur = (void *)CONFIG_SYS_MPC85xx_GUTS_ADDR;
28
29 clrbits_be32(&gur->pmuxcr2, MPC85xx_PMUXCR2_UART_CTS_B0_GPIO42);
30 setbits_be32(&gur->pmuxcr2, MPC85xx_PMUXCR2_UART_CTS_B0_DSP_TMS);
31
32 clrbits_be32(&gur->pmuxcr2, MPC85xx_PMUXCR2_UART_RTS_B0_GPIO43);
33 setbits_be32(&gur->pmuxcr2, MPC85xx_PMUXCR2_UART_RTS_B0_DSP_TCK |
34 MPC85xx_PMUXCR2_UART_CTS_B1_SIM_PD);
35 setbits_be32(&gur->halt_req_mask, HALTED_TO_HALT_REQ_MASK_0);
36 clrsetbits_be32(&gur->pmuxcr, MPC85xx_PMUXCR_IFC_AD_GPIO_MASK |
37 MPC85xx_PMUXCR_IFC_AD17_GPO_MASK,
38 MPC85xx_PMUXCR_IFC_AD_GPIO |
39 MPC85xx_PMUXCR_IFC_AD17_GPO | MPC85xx_PMUXCR_SDHC_USIM);
40
41 return 0;
42}
43
44int checkboard(void)
45{
46 struct cpu_type *cpu;
47
48 cpu = gd->arch.cpu;
49 printf("Board: %sRDB\n", cpu->name);
50
51 return 0;
52}
53
54#if defined(CONFIG_OF_BOARD_SETUP)
55#ifdef CONFIG_FDT_FIXUP_PARTITIONS
56static const struct node_info nodes[] = {
57 { "fsl,ifc-nand", MTD_DEV_TYPE_NAND, },
58};
59#endif
60int ft_board_setup(void *blob, bd_t *bd)
61{
62 phys_addr_t base;
63 phys_size_t size;
64
65 ft_cpu_setup(blob, bd);
66
67 base = env_get_bootm_low();
68 size = env_get_bootm_size();
69
70 fdt_fixup_memory(blob, (u64)base, (u64)size);
71#ifdef CONFIG_FDT_FIXUP_PARTITIONS
72 fdt_fixup_mtdparts(blob, nodes, ARRAY_SIZE(nodes));
73#endif
74
75 fsl_fdt_fixup_dr_usb(blob, bd);
76
77 return 0;
78}
79#endif
80