LXR uboot/board/freescale/ls1088a/ls1088a.c

   1// SPDX-License-Identifier: GPL-2.0+
   2/*
   3 * Copyright 2017-2018 NXP
   4 */
   5#include <common.h>
   6#include <i2c.h>
   7#include <malloc.h>
   8#include <errno.h>
   9#include <netdev.h>
  10#include <fsl_ifc.h>
  11#include <fsl_ddr.h>
  12#include <fsl_sec.h>
  13#include <asm/io.h>
  14#include <fdt_support.h>
  15#include <linux/libfdt.h>
  16#include <fsl-mc/fsl_mc.h>
  17#include <environment.h>
  18#include <asm/arch-fsl-layerscape/soc.h>
  19#include <asm/arch/ppa.h>
  20#include <hwconfig.h>
  21#include <asm/arch/fsl_serdes.h>
  22#include <asm/arch/soc.h>
  23
  24#include "../common/qixis.h"
  25#include "ls1088a_qixis.h"
  26#include "../common/vid.h"
  27#include <fsl_immap.h>
  28
  29DECLARE_GLOBAL_DATA_PTR;
  30
  31int board_early_init_f(void)
  32{
  33#if defined(CONFIG_SYS_I2C_EARLY_INIT) && defined(CONFIG_TARGET_LS1088AQDS)
  34        i2c_early_init_f();
  35#endif
  36        fsl_lsch3_early_init_f();
  37        return 0;
  38}
  39
  40#ifdef CONFIG_FSL_QIXIS
  41unsigned long long get_qixis_addr(void)
  42{
  43        unsigned long long addr;
  44
  45        if (gd->flags & GD_FLG_RELOC)
  46                addr = QIXIS_BASE_PHYS;
  47        else
  48                addr = QIXIS_BASE_PHYS_EARLY;
  49
  50        /*
  51         * IFC address under 256MB is mapped to 0x30000000, any address above
  52         * is mapped to 0x5_10000000 up to 4GB.
  53         */
  54        addr = addr  > 0x10000000 ? addr + 0x500000000ULL : addr + 0x30000000;
  55
  56        return addr;
  57}
  58#endif
  59
  60#if defined(CONFIG_VID)
  61int init_func_vid(void)
  62{
  63        if (adjust_vdd(0) < 0)
  64                printf("core voltage not adjusted\n");
  65
  66        return 0;
  67}
  68#endif
  69
  70int is_pb_board(void)
  71{
  72        u8 board_id;
  73
  74        board_id = QIXIS_READ(id);
  75        if (board_id == LS1088ARDB_PB_BOARD)
  76                return 1;
  77        else
  78                return 0;
  79}
  80
  81int fixup_ls1088ardb_pb_banner(void *fdt)
  82{
  83        fdt_setprop_string(fdt, 0, "model", "LS1088ARDB-PB Board");
  84
  85        return 0;
  86}
  87
  88#if !defined(CONFIG_SPL_BUILD)
  89int checkboard(void)
  90{
  91        char buf[64];
  92        u8 sw;
  93        static const char *const freq[] = {"100", "125", "156.25",
  94                                            "100 separate SSCG"};
  95        int clock;
  96
  97#ifdef CONFIG_TARGET_LS1088AQDS
  98        printf("Board: LS1088A-QDS, ");
  99#else
 100        if (is_pb_board())
 101                printf("Board: LS1088ARDB-PB, ");
 102        else
 103                printf("Board: LS1088A-RDB, ");
 104#endif
 105
 106        sw = QIXIS_READ(arch);
 107        printf("Board Arch: V%d, ", sw >> 4);
 108
 109#ifdef CONFIG_TARGET_LS1088AQDS
 110        printf("Board version: %c, boot from ", (sw & 0xf) + 'A' - 1);
 111#else
 112        printf("Board version: %c, boot from ", (sw & 0xf) + 'A');
 113#endif
 114
 115        memset((u8 *)buf, 0x00, ARRAY_SIZE(buf));
 116
 117        sw = QIXIS_READ(brdcfg[0]);
 118        sw = (sw & QIXIS_LBMAP_MASK) >> QIXIS_LBMAP_SHIFT;
 119
 120#ifdef CONFIG_SD_BOOT
 121        puts("SD card\n");
 122#endif
 123        switch (sw) {
 124#ifdef CONFIG_TARGET_LS1088AQDS
 125        case 0:
 126        case 1:
 127        case 2:
 128        case 3:
 129        case 4:
 130        case 5:
 131        case 6:
 132        case 7:
 133                printf("vBank: %d\n", sw);
 134                break;
 135        case 8:
 136                puts("PromJet\n");
 137                break;
 138        case 15:
 139                puts("IFCCard\n");
 140                break;
 141        case 14:
 142#else
 143        case 0:
 144#endif
 145                puts("QSPI:");
 146                sw = QIXIS_READ(brdcfg[0]);
 147                sw = (sw & QIXIS_QMAP_MASK) >> QIXIS_QMAP_SHIFT;
 148                if (sw == 0 || sw == 4)
 149                        puts("0\n");
 150                else if (sw == 1)
 151                        puts("1\n");
 152                else
 153                        puts("EMU\n");
 154                break;
 155
 156        default:
 157                printf("invalid setting of SW%u\n", QIXIS_LBMAP_SWITCH);
 158                break;
 159        }
 160
 161#ifdef CONFIG_TARGET_LS1088AQDS
 162        printf("FPGA: v%d (%s), build %d",
 163               (int)QIXIS_READ(scver), qixis_read_tag(buf),
 164               (int)qixis_read_minor());
 165        /* the timestamp string contains "\n" at the end */
 166        printf(" on %s", qixis_read_time(buf));
 167#else
 168        printf("CPLD: v%d.%d\n", QIXIS_READ(scver), QIXIS_READ(tagdata));
 169#endif
 170
 171        /*
 172         * Display the actual SERDES reference clocks as configured by the
 173         * dip switches on the board.  Note that the SWx registers could
 174         * technically be set to force the reference clocks to match the
 175         * values that the SERDES expects (or vice versa).  For now, however,
 176         * we just display both values and hope the user notices when they
 177         * don't match.
 178         */
 179        puts("SERDES1 Reference : ");
 180        sw = QIXIS_READ(brdcfg[2]);
 181        clock = (sw >> 6) & 3;
 182        printf("Clock1 = %sMHz ", freq[clock]);
 183        clock = (sw >> 4) & 3;
 184        printf("Clock2 = %sMHz", freq[clock]);
 185
 186        puts("\nSERDES2 Reference : ");
 187        clock = (sw >> 2) & 3;
 188        printf("Clock1 = %sMHz ", freq[clock]);
 189        clock = (sw >> 0) & 3;
 190        printf("Clock2 = %sMHz\n", freq[clock]);
 191
 192        return 0;
 193}
 194#endif
 195
 196bool if_board_diff_clk(void)
 197{
 198#ifdef CONFIG_TARGET_LS1088AQDS
 199        u8 diff_conf = QIXIS_READ(brdcfg[11]);
 200        return diff_conf & 0x40;
 201#else
 202        u8 diff_conf = QIXIS_READ(dutcfg[11]);
 203        return diff_conf & 0x80;
 204#endif
 205}
 206
 207unsigned long get_board_sys_clk(void)
 208{
 209        u8 sysclk_conf = QIXIS_READ(brdcfg[1]);
 210
 211        switch (sysclk_conf & 0x0f) {
 212        case QIXIS_SYSCLK_83:
 213                return 83333333;
 214        case QIXIS_SYSCLK_100:
 215                return 100000000;
 216        case QIXIS_SYSCLK_125:
 217                return 125000000;
 218        case QIXIS_SYSCLK_133:
 219                return 133333333;
 220        case QIXIS_SYSCLK_150:
 221                return 150000000;
 222        case QIXIS_SYSCLK_160:
 223                return 160000000;
 224        case QIXIS_SYSCLK_166:
 225                return 166666666;
 226        }
 227
 228        return 66666666;
 229}
 230
 231unsigned long get_board_ddr_clk(void)
 232{
 233        u8 ddrclk_conf = QIXIS_READ(brdcfg[1]);
 234
 235        if (if_board_diff_clk())
 236                return get_board_sys_clk();
 237        switch ((ddrclk_conf & 0x30) >> 4) {
 238        case QIXIS_DDRCLK_100:
 239                return 100000000;
 240        case QIXIS_DDRCLK_125:
 241                return 125000000;
 242        case QIXIS_DDRCLK_133:
 243                return 133333333;
 244        }
 245
 246        return 66666666;
 247}
 248
 249int select_i2c_ch_pca9547(u8 ch)
 250{
 251        int ret;
 252
 253        ret = i2c_write(I2C_MUX_PCA_ADDR_PRI, 0, 1, &ch, 1);
 254        if (ret) {
 255                puts("PCA: failed to select proper channel\n");
 256                return ret;
 257        }
 258
 259        return 0;
 260}
 261
 262#if !defined(CONFIG_SPL_BUILD)
 263void board_retimer_init(void)
 264{
 265        u8 reg;
 266
 267        /* Retimer is connected to I2C1_CH5 */
 268        select_i2c_ch_pca9547(I2C_MUX_CH5);
 269
 270        /* Access to Control/Shared register */
 271        reg = 0x0;
 272        i2c_write(I2C_RETIMER_ADDR, 0xff, 1, &reg, 1);
 273
 274        /* Read device revision and ID */
 275        i2c_read(I2C_RETIMER_ADDR, 1, 1, &reg, 1);
 276        debug("Retimer version id = 0x%x\n", reg);
 277
 278        /* Enable Broadcast. All writes target all channel register sets */
 279        reg = 0x0c;
 280        i2c_write(I2C_RETIMER_ADDR, 0xff, 1, &reg, 1);
 281
 282        /* Reset Channel Registers */
 283        i2c_read(I2C_RETIMER_ADDR, 0, 1, &reg, 1);
 284        reg |= 0x4;
 285        i2c_write(I2C_RETIMER_ADDR, 0, 1, &reg, 1);
 286
 287        /* Set data rate as 10.3125 Gbps */
 288        reg = 0x90;
 289        i2c_write(I2C_RETIMER_ADDR, 0x60, 1, &reg, 1);
 290        reg = 0xb3;
 291        i2c_write(I2C_RETIMER_ADDR, 0x61, 1, &reg, 1);
 292        reg = 0x90;
 293        i2c_write(I2C_RETIMER_ADDR, 0x62, 1, &reg, 1);
 294        reg = 0xb3;
 295        i2c_write(I2C_RETIMER_ADDR, 0x63, 1, &reg, 1);
 296        reg = 0xcd;
 297        i2c_write(I2C_RETIMER_ADDR, 0x64, 1, &reg, 1);
 298
 299        /* Select VCO Divider to full rate (000) */
 300        i2c_read(I2C_RETIMER_ADDR, 0x2F, 1, &reg, 1);
 301        reg &= 0x0f;
 302        reg |= 0x70;
 303        i2c_write(I2C_RETIMER_ADDR, 0x2F, 1, &reg, 1);
 304
 305#ifdef  CONFIG_TARGET_LS1088AQDS
 306        /* Retimer is connected to I2C1_CH5 */
 307        select_i2c_ch_pca9547(I2C_MUX_CH5);
 308
 309        /* Access to Control/Shared register */
 310        reg = 0x0;
 311        i2c_write(I2C_RETIMER_ADDR2, 0xff, 1, &reg, 1);
 312
 313        /* Read device revision and ID */
 314        i2c_read(I2C_RETIMER_ADDR2, 1, 1, &reg, 1);
 315        debug("Retimer version id = 0x%x\n", reg);
 316
 317        /* Enable Broadcast. All writes target all channel register sets */
 318        reg = 0x0c;
 319        i2c_write(I2C_RETIMER_ADDR2, 0xff, 1, &reg, 1);
 320
 321        /* Reset Channel Registers */
 322        i2c_read(I2C_RETIMER_ADDR2, 0, 1, &reg, 1);
 323        reg |= 0x4;
 324        i2c_write(I2C_RETIMER_ADDR2, 0, 1, &reg, 1);
 325
 326        /* Set data rate as 10.3125 Gbps */
 327        reg = 0x90;
 328        i2c_write(I2C_RETIMER_ADDR2, 0x60, 1, &reg, 1);
 329        reg = 0xb3;
 330        i2c_write(I2C_RETIMER_ADDR2, 0x61, 1, &reg, 1);
 331        reg = 0x90;
 332        i2c_write(I2C_RETIMER_ADDR2, 0x62, 1, &reg, 1);
 333        reg = 0xb3;
 334        i2c_write(I2C_RETIMER_ADDR2, 0x63, 1, &reg, 1);
 335        reg = 0xcd;
 336        i2c_write(I2C_RETIMER_ADDR2, 0x64, 1, &reg, 1);
 337
 338        /* Select VCO Divider to full rate (000) */
 339        i2c_read(I2C_RETIMER_ADDR2, 0x2F, 1, &reg, 1);
 340        reg &= 0x0f;
 341        reg |= 0x70;
 342        i2c_write(I2C_RETIMER_ADDR2, 0x2F, 1, &reg, 1);
 343#endif
 344        /*return the default channel*/
 345        select_i2c_ch_pca9547(I2C_MUX_CH_DEFAULT);
 346}
 347
 348#ifdef CONFIG_MISC_INIT_R
 349int misc_init_r(void)
 350{
 351#ifdef CONFIG_TARGET_LS1088ARDB
 352        u8 brdcfg5;
 353
 354        if (hwconfig("esdhc-force-sd")) {
 355                brdcfg5 = QIXIS_READ(brdcfg[5]);
 356                brdcfg5 &= ~BRDCFG5_SPISDHC_MASK;
 357                brdcfg5 |= BRDCFG5_FORCE_SD;
 358                QIXIS_WRITE(brdcfg[5], brdcfg5);
 359        }
 360#endif
 361        return 0;
 362}
 363#endif
 364#endif
 365
 366int i2c_multiplexer_select_vid_channel(u8 channel)
 367{
 368        return select_i2c_ch_pca9547(channel);
 369}
 370
 371#ifdef CONFIG_TARGET_LS1088AQDS
 372/* read the current value(SVDD) of the LTM Regulator Voltage */
 373int get_serdes_volt(void)
 374{
 375        int  ret, vcode = 0;
 376        u8 chan = PWM_CHANNEL0;
 377
 378        /* Select the PAGE 0 using PMBus commands PAGE for VDD */
 379        ret = i2c_write(I2C_SVDD_MONITOR_ADDR,
 380                        PMBUS_CMD_PAGE, 1, &chan, 1);
 381        if (ret) {
 382                printf("VID: failed to select VDD Page 0\n");
 383                return ret;
 384        }
 385
 386        /* Read the output voltage using PMBus command READ_VOUT */
 387        ret = i2c_read(I2C_SVDD_MONITOR_ADDR,
 388                       PMBUS_CMD_READ_VOUT, 1, (void *)&vcode, 2);
 389        if (ret) {
 390                printf("VID: failed to read the volatge\n");
 391                return ret;
 392        }
 393
 394        return vcode;
 395}
 396
 397int set_serdes_volt(int svdd)
 398{
 399        int ret, vdd_last;
 400        u8 buff[5] = {0x04, PWM_CHANNEL0, PMBUS_CMD_VOUT_COMMAND,
 401                        svdd & 0xFF, (svdd & 0xFF00) >> 8};
 402
 403        /* Write the desired voltage code to the SVDD regulator */
 404        ret = i2c_write(I2C_SVDD_MONITOR_ADDR,
 405                        PMBUS_CMD_PAGE_PLUS_WRITE, 1, (void *)&buff, 5);
 406        if (ret) {
 407                printf("VID: I2C failed to write to the volatge regulator\n");
 408                return -1;
 409        }
 410
 411        /* Wait for the volatge to get to the desired value */
 412        do {
 413                vdd_last = get_serdes_volt();
 414                if (vdd_last < 0) {
 415                        printf("VID: Couldn't read sensor abort VID adjust\n");
 416                        return -1;
 417                }
 418        } while (vdd_last != svdd);
 419
 420        return 1;
 421}
 422#else
 423int get_serdes_volt(void)
 424{
 425        return 0;
 426}
 427
 428int set_serdes_volt(int svdd)
 429{
 430        int ret;
 431        u8 brdcfg4;
 432
 433        printf("SVDD changing of RDB\n");
 434
 435        /* Read the BRDCFG54 via CLPD */
 436        ret = i2c_read(CONFIG_SYS_I2C_FPGA_ADDR,
 437                       QIXIS_BRDCFG4_OFFSET, 1, (void *)&brdcfg4, 1);
 438        if (ret) {
 439                printf("VID: I2C failed to read the CPLD BRDCFG4\n");
 440                return -1;
 441        }
 442
 443        brdcfg4 = brdcfg4 | 0x08;
 444
 445        /* Write to the BRDCFG4 */
 446        ret = i2c_write(CONFIG_SYS_I2C_FPGA_ADDR,
 447                        QIXIS_BRDCFG4_OFFSET, 1, (void *)&brdcfg4, 1);
 448        if (ret) {
 449                debug("VID: I2C failed to set the SVDD CPLD BRDCFG4\n");
 450                return -1;
 451        }
 452
 453        /* Wait for the volatge to get to the desired value */
 454        udelay(10000);
 455
 456        return 1;
 457}
 458#endif
 459
 460/* this function disables the SERDES, changes the SVDD Voltage and enables it*/
 461int board_adjust_vdd(int vdd)
 462{
 463        int ret = 0;
 464
 465        debug("%s: vdd = %d\n", __func__, vdd);
 466
 467        /* Special settings to be performed when voltage is 900mV */
 468        if (vdd == 900) {
 469                ret = setup_serdes_volt(vdd);
 470                if (ret < 0) {
 471                        ret = -1;
 472                        goto exit;
 473                }
 474        }
 475exit:
 476        return ret;
 477}
 478
 479#if !defined(CONFIG_SPL_BUILD)
 480int board_init(void)
 481{
 482        init_final_memctl_regs();
 483#if defined(CONFIG_TARGET_LS1088ARDB) && defined(CONFIG_FSL_MC_ENET)
 484        u32 __iomem *irq_ccsr = (u32 __iomem *)ISC_BASE;
 485#endif
 486
 487        select_i2c_ch_pca9547(I2C_MUX_CH_DEFAULT);
 488        board_retimer_init();
 489
 490#ifdef CONFIG_ENV_IS_NOWHERE
 491        gd->env_addr = (ulong)&default_environment[0];
 492#endif
 493
 494#if defined(CONFIG_TARGET_LS1088ARDB) && defined(CONFIG_FSL_MC_ENET)
 495        /* invert AQR105 IRQ pins polarity */
 496        out_le32(irq_ccsr + IRQCR_OFFSET / 4, AQR105_IRQ_MASK);
 497#endif
 498
 499#ifdef CONFIG_FSL_CAAM
 500        sec_init();
 501#endif
 502#ifdef CONFIG_FSL_LS_PPA
 503        ppa_init();
 504#endif
 505        return 0;
 506}
 507
 508void detail_board_ddr_info(void)
 509{
 510        puts("\nDDR    ");
 511        print_size(gd->bd->bi_dram[0].size + gd->bd->bi_dram[1].size, "");
 512        print_ddr_info(0);
 513}
 514
 515#if defined(CONFIG_ARCH_MISC_INIT)
 516int arch_misc_init(void)
 517{
 518        return 0;
 519}
 520#endif
 521
 522#ifdef CONFIG_FSL_MC_ENET
 523void fdt_fixup_board_enet(void *fdt)
 524{
 525        int offset;
 526
 527        offset = fdt_path_offset(fdt, "/fsl-mc");
 528
 529        if (offset < 0)
 530                offset = fdt_path_offset(fdt, "/fsl,dprc@0");
 531
 532        if (offset < 0) {
 533                printf("%s: ERROR: fsl-mc node not found in device tree (error %d)\n",
 534                       __func__, offset);
 535                return;
 536        }
 537
 538        if ((get_mc_boot_status() == 0) && (get_dpl_apply_status() == 0))
 539                fdt_status_okay(fdt, offset);
 540        else
 541                fdt_status_fail(fdt, offset);
 542}
 543#endif
 544
 545#ifdef CONFIG_OF_BOARD_SETUP
 546void fsl_fdt_fixup_flash(void *fdt)
 547{
 548        int offset;
 549
 550/*
 551 * IFC-NOR and QSPI are muxed on SoC.
 552 * So disable IFC node in dts if QSPI is enabled or
 553 * disable QSPI node in dts in case QSPI is not enabled.
 554 */
 555
 556#ifdef CONFIG_FSL_QSPI
 557        offset = fdt_path_offset(fdt, "/soc/ifc/nor");
 558
 559        if (offset < 0)
 560                offset = fdt_path_offset(fdt, "/ifc/nor");
 561#else
 562        offset = fdt_path_offset(fdt, "/soc/quadspi");
 563
 564        if (offset < 0)
 565                offset = fdt_path_offset(fdt, "/quadspi");
 566#endif
 567        if (offset < 0)
 568                return;
 569
 570        fdt_status_disabled(fdt, offset);
 571}
 572
 573int ft_board_setup(void *blob, bd_t *bd)
 574{
 575        int err, i;
 576        u64 base[CONFIG_NR_DRAM_BANKS];
 577        u64 size[CONFIG_NR_DRAM_BANKS];
 578
 579        ft_cpu_setup(blob, bd);
 580
 581        /* fixup DT for the two GPP DDR banks */
 582        for (i = 0; i < CONFIG_NR_DRAM_BANKS; i++) {
 583                base[i] = gd->bd->bi_dram[i].start;
 584                size[i] = gd->bd->bi_dram[i].size;
 585        }
 586
 587#ifdef CONFIG_RESV_RAM
 588        /* reduce size if reserved memory is within this bank */
 589        if (gd->arch.resv_ram >= base[0] &&
 590            gd->arch.resv_ram < base[0] + size[0])
 591                size[0] = gd->arch.resv_ram - base[0];
 592        else if (gd->arch.resv_ram >= base[1] &&
 593                 gd->arch.resv_ram < base[1] + size[1])
 594                size[1] = gd->arch.resv_ram - base[1];
 595#endif
 596
 597        fdt_fixup_memory_banks(blob, base, size, CONFIG_NR_DRAM_BANKS);
 598
 599        fdt_fsl_mc_fixup_iommu_map_entry(blob);
 600
 601        fsl_fdt_fixup_flash(blob);
 602
 603#ifdef CONFIG_FSL_MC_ENET
 604        fdt_fixup_board_enet(blob);
 605        err = fsl_mc_ldpaa_exit(bd);
 606        if (err)
 607                return err;
 608#endif
 609        if (is_pb_board())
 610                fixup_ls1088ardb_pb_banner(blob);
 611
 612        return 0;
 613}
 614#endif
 615#endif /* defined(CONFIG_SPL_BUILD) */
 616