LXR uboot/board/hisilicon/poplar/poplar.c

   1// SPDX-License-Identifier: GPL-2.0+
   2/*
   3 * (C) Copyright 2017 Linaro
   4 * Jorge Ramirez-Ortiz <jorge.ramirez-ortiz@linaro.org>
   5 */
   6
   7#include <dm.h>
   8#include <common.h>
   9#include <asm/io.h>
  10#include <dm/platform_data/serial_pl01x.h>
  11#include <asm/arch/hi3798cv200.h>
  12#include <asm/arch/dwmmc.h>
  13#include <asm/armv8/mmu.h>
  14
  15DECLARE_GLOBAL_DATA_PTR;
  16
  17static struct mm_region poplar_mem_map[] = {
  18        {
  19                .virt = 0x0UL,
  20                .phys = 0x0UL,
  21                .size = 0x80000000UL,
  22                .attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL) |
  23                         PTE_BLOCK_INNER_SHARE
  24        }, {
  25                .virt = 0x80000000UL,
  26                .phys = 0x80000000UL,
  27                .size = 0x80000000UL,
  28                .attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
  29                         PTE_BLOCK_NON_SHARE |
  30                         PTE_BLOCK_PXN | PTE_BLOCK_UXN
  31        }, {
  32                0,
  33        }
  34};
  35
  36struct mm_region *mem_map = poplar_mem_map;
  37
  38#if !CONFIG_IS_ENABLED(OF_CONTROL)
  39static const struct pl01x_serial_platdata serial_platdata = {
  40        .base = REG_BASE_UART0,
  41        .type = TYPE_PL010,
  42        .clock = 75000000,
  43};
  44
  45U_BOOT_DEVICE(poplar_serial) = {
  46        .name = "serial_pl01x",
  47        .platdata = &serial_platdata,
  48};
  49#endif
  50
  51int checkboard(void)
  52{
  53        puts("BOARD: Hisilicon HI3798cv200 Poplar\n");
  54
  55        return 0;
  56}
  57
  58void reset_cpu(ulong addr)
  59{
  60        psci_system_reset();
  61}
  62
  63int dram_init(void)
  64{
  65        gd->ram_size = get_ram_size(NULL, 0x80000000);
  66
  67        return 0;
  68}
  69
  70/*
  71 * Some linux kernel versions don't use memory before its load address, so to
  72 * be generic we just pretend it isn't there.  In previous uboot versions we
  73 * carved the space used by BL31 (runs in DDR on this platfomr) so the PSCI code
  74 * could persist in memory and be left alone by the kernel.
  75 *
  76 * That led to a problem when mapping memory in older kernels.  That PSCI code
  77 * now lies in memory below the kernel load offset; it therefore won't be
  78 * touched by the kernel, and by not specially reserving it we avoid the mapping
  79 * problem as well.
  80 *
  81 */
  82#define KERNEL_TEXT_OFFSET      0x00080000
  83
  84int dram_init_banksize(void)
  85{
  86        gd->bd->bi_dram[0].start = KERNEL_TEXT_OFFSET;
  87        gd->bd->bi_dram[0].size = gd->ram_size - gd->bd->bi_dram[0].start;
  88
  89        return 0;
  90}
  91
  92static void usb2_phy_config(void)
  93{
  94        const u32 config[] = {
  95                /* close EOP pre-emphasis. open data pre-emphasis */
  96                0xa1001c,
  97                /* Rcomp = 150mW, increase DC level */
  98                0xa00607,
  99                /* keep Rcomp working */
 100                0xa10700,
 101                /* Icomp = 212mW, increase current drive */
 102                0xa00aab,
 103                /* EMI fix: rx_active not stay 1 when error packets received */
 104                0xa11140,
 105                /* Comp mode select */
 106                0xa11041,
 107                /* adjust eye diagram */
 108                0xa0098c,
 109                /* adjust eye diagram */
 110                0xa10a0a,
 111        };
 112        int i;
 113
 114        for (i = 0; i < ARRAY_SIZE(config); i++) {
 115                writel(config[i], PERI_CTRL_USB0);
 116                clrsetbits_le32(PERI_CTRL_USB0, BIT(21), BIT(20) | BIT(22));
 117                udelay(20);
 118        }
 119}
 120
 121static void usb2_phy_init(void)
 122{
 123        /* reset usb2 controller bus/utmi/roothub */
 124        setbits_le32(PERI_CRG46, USB2_BUS_SRST_REQ | USB2_UTMI0_SRST_REQ |
 125                        USB2_HST_PHY_SYST_REQ | USB2_OTG_PHY_SYST_REQ);
 126        udelay(200);
 127
 128        /* reset usb2 phy por/utmi */
 129        setbits_le32(PERI_CRG47, USB2_PHY01_SRST_REQ | USB2_PHY01_SRST_TREQ1);
 130        udelay(200);
 131
 132        /* open usb2 ref clk */
 133        setbits_le32(PERI_CRG47, USB2_PHY01_REF_CKEN);
 134        udelay(300);
 135
 136        /* cancel usb2 power on reset */
 137        clrbits_le32(PERI_CRG47, USB2_PHY01_SRST_REQ);
 138        udelay(500);
 139
 140        usb2_phy_config();
 141
 142        /* cancel usb2 port reset, wait comp circuit stable */
 143        clrbits_le32(PERI_CRG47, USB2_PHY01_SRST_TREQ1);
 144        mdelay(10);
 145
 146        /* open usb2 controller clk */
 147        setbits_le32(PERI_CRG46, USB2_BUS_CKEN | USB2_OHCI48M_CKEN |
 148                        USB2_OHCI12M_CKEN | USB2_OTG_UTMI_CKEN |
 149                        USB2_HST_PHY_CKEN | USB2_UTMI0_CKEN);
 150        udelay(200);
 151
 152        /* cancel usb2 control reset */
 153        clrbits_le32(PERI_CRG46, USB2_BUS_SRST_REQ | USB2_UTMI0_SRST_REQ |
 154                        USB2_HST_PHY_SYST_REQ | USB2_OTG_PHY_SYST_REQ);
 155        udelay(200);
 156}
 157
 158int board_mmc_init(bd_t *bis)
 159{
 160        int ret;
 161
 162        ret = hi6220_dwmci_add_port(0, REG_BASE_MCI, 8);
 163        if (ret)
 164                printf("mmc init error (%d)\n", ret);
 165
 166        return ret;
 167}
 168
 169int board_init(void)
 170{
 171        usb2_phy_init();
 172
 173        return 0;
 174}
 175
 176