LXR uboot/board/k+p/kp_imx6q_tpc/kp_imx6q

   1// SPDX-License-Identifier: GPL-2.0+
   2/*
   3 * K+P iMX6Q KP_IMX6Q_TPC board configuration
   4 *
   5 * Copyright (C) 2018 Lukasz Majewski <lukma@denx.de>
   6 */
   7
   8#include <common.h>
   9#include <asm/arch/clock.h>
  10#include <asm/arch/crm_regs.h>
  11#include <asm/arch/imx-regs.h>
  12#include <asm/arch/iomux.h>
  13#include <asm/arch/mx6-pins.h>
  14#include <asm/arch/sys_proto.h>
  15#include <asm/gpio.h>
  16#include <asm/io.h>
  17#include <asm/mach-imx/boot_mode.h>
  18#include <asm/mach-imx/iomux-v3.h>
  19#include <asm/mach-imx/mxc_i2c.h>
  20#include <errno.h>
  21#include <fsl_esdhc.h>
  22#include <fuse.h>
  23#include <i2c.h>
  24#include <miiphy.h>
  25#include <mmc.h>
  26#include <net.h>
  27#include <netdev.h>
  28#include <usb.h>
  29#include <usb/ehci-ci.h>
  30
  31DECLARE_GLOBAL_DATA_PTR;
  32
  33#define ENET_PAD_CTRL                                                   \
  34        (PAD_CTL_PUS_100K_UP | PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm |  \
  35         PAD_CTL_HYS)
  36
  37#define I2C_PAD_CTRL                                                    \
  38        (PAD_CTL_PUS_100K_UP | PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm |  \
  39        PAD_CTL_HYS | PAD_CTL_ODE | PAD_CTL_SRE_FAST)
  40
  41#define PC                      MUX_PAD_CTRL(I2C_PAD_CTRL)
  42
  43static struct i2c_pads_info kp_imx6q_tpc_i2c_pad_info0 = {
  44        .scl = {
  45                .i2c_mode  = MX6Q_PAD_CSI0_DAT9__I2C1_SCL | PC,
  46                .gpio_mode = MX6Q_PAD_CSI0_DAT9__GPIO5_IO27 | PC,
  47                .gp = IMX_GPIO_NR(5, 27)
  48        },
  49        .sda = {
  50                 .i2c_mode = MX6Q_PAD_CSI0_DAT8__I2C1_SDA | PC,
  51                 .gpio_mode = MX6Q_PAD_CSI0_DAT8__GPIO5_IO26 | PC,
  52                 .gp = IMX_GPIO_NR(5, 26)
  53        }
  54};
  55
  56static struct i2c_pads_info kp_imx6q_tpc_i2c_pad_info1 = {
  57        .scl = {
  58                .i2c_mode  = MX6Q_PAD_KEY_COL3__I2C2_SCL | PC,
  59                .gpio_mode = MX6Q_PAD_KEY_COL3__GPIO4_IO12 | PC,
  60                .gp = IMX_GPIO_NR(4, 12)
  61        },
  62        .sda = {
  63                 .i2c_mode = MX6Q_PAD_KEY_ROW3__I2C2_SDA | PC,
  64                 .gpio_mode = MX6Q_PAD_KEY_ROW3__GPIO4_IO13 | PC,
  65                 .gp = IMX_GPIO_NR(4, 13)
  66        }
  67};
  68
  69int dram_init(void)
  70{
  71        gd->ram_size = imx_ddr_size();
  72        return 0;
  73}
  74
  75/*
  76 * Do not overwrite the console
  77 * Use always serial for U-Boot console
  78 */
  79int overwrite_console(void)
  80{
  81        return 1;
  82}
  83
  84#ifdef CONFIG_FEC_MXC
  85static iomux_v3_cfg_t const enet_pads[] = {
  86        IOMUX_PADS(PAD_ENET_MDIO__ENET_MDIO     | MUX_PAD_CTRL(ENET_PAD_CTRL)),
  87        IOMUX_PADS(PAD_ENET_MDC__ENET_MDC       | MUX_PAD_CTRL(ENET_PAD_CTRL)),
  88        IOMUX_PADS(PAD_RGMII_TXC__RGMII_TXC     | MUX_PAD_CTRL(ENET_PAD_CTRL)),
  89        IOMUX_PADS(PAD_RGMII_TD0__RGMII_TD0     | MUX_PAD_CTRL(ENET_PAD_CTRL)),
  90        IOMUX_PADS(PAD_RGMII_TD1__RGMII_TD1     | MUX_PAD_CTRL(ENET_PAD_CTRL)),
  91        IOMUX_PADS(PAD_RGMII_TD2__RGMII_TD2     | MUX_PAD_CTRL(ENET_PAD_CTRL)),
  92        IOMUX_PADS(PAD_RGMII_TD3__RGMII_TD3     | MUX_PAD_CTRL(ENET_PAD_CTRL)),
  93        IOMUX_PADS(PAD_RGMII_TX_CTL__RGMII_TX_CTL |
  94                   MUX_PAD_CTRL(ENET_PAD_CTRL)),
  95        IOMUX_PADS(PAD_ENET_REF_CLK__ENET_TX_CLK | MUX_PAD_CTRL(ENET_PAD_CTRL)),
  96        IOMUX_PADS(PAD_RGMII_RXC__RGMII_RXC     | MUX_PAD_CTRL(ENET_PAD_CTRL)),
  97        IOMUX_PADS(PAD_RGMII_RD0__RGMII_RD0     | MUX_PAD_CTRL(ENET_PAD_CTRL)),
  98        IOMUX_PADS(PAD_RGMII_RD1__RGMII_RD1     | MUX_PAD_CTRL(ENET_PAD_CTRL)),
  99        IOMUX_PADS(PAD_RGMII_RD2__RGMII_RD2     | MUX_PAD_CTRL(ENET_PAD_CTRL)),
 100        IOMUX_PADS(PAD_RGMII_RD3__RGMII_RD3     | MUX_PAD_CTRL(ENET_PAD_CTRL)),
 101        IOMUX_PADS(PAD_RGMII_RX_CTL__RGMII_RX_CTL |
 102                   MUX_PAD_CTRL(ENET_PAD_CTRL)),
 103        /* AR8031 PHY Reset */
 104        IOMUX_PADS(PAD_ENET_CRS_DV__GPIO1_IO25  | MUX_PAD_CTRL(NO_PAD_CTRL)),
 105};
 106
 107static void eth_phy_reset(void)
 108{
 109        /* Reset AR8031 PHY */
 110        gpio_direction_output(IMX_GPIO_NR(1, 25), 0);
 111        mdelay(10);
 112        gpio_set_value(IMX_GPIO_NR(1, 25), 1);
 113        udelay(100);
 114}
 115
 116static int setup_fec_clock(void)
 117{
 118        struct iomuxc *iomuxc_regs = (struct iomuxc *)IOMUXC_BASE_ADDR;
 119
 120        /* set gpr1[21] to select anatop clock */
 121        clrsetbits_le32(&iomuxc_regs->gpr[1], 0x1 << 21, 0x1 << 21);
 122
 123        return enable_fec_anatop_clock(0, ENET_50MHZ);
 124}
 125
 126int board_eth_init(bd_t *bis)
 127{
 128        SETUP_IOMUX_PADS(enet_pads);
 129        setup_fec_clock();
 130        eth_phy_reset();
 131
 132        return cpu_eth_init(bis);
 133}
 134
 135static int ar8031_phy_fixup(struct phy_device *phydev)
 136{
 137        unsigned short val;
 138
 139        /* To enable AR8031 output a 125MHz clk from CLK_25M */
 140        phy_write(phydev, MDIO_DEVAD_NONE, 0xd, 0x7);
 141        phy_write(phydev, MDIO_DEVAD_NONE, 0xe, 0x8016);
 142        phy_write(phydev, MDIO_DEVAD_NONE, 0xd, 0x4007);
 143
 144        val = phy_read(phydev, MDIO_DEVAD_NONE, 0xe);
 145        val &= 0xffe3;
 146        val |= 0x18;
 147        phy_write(phydev, MDIO_DEVAD_NONE, 0xe, val);
 148
 149        /* introduce tx clock delay */
 150        phy_write(phydev, MDIO_DEVAD_NONE, 0x1d, 0x5);
 151        val = phy_read(phydev, MDIO_DEVAD_NONE, 0x1e);
 152        val |= 0x0100;
 153        phy_write(phydev, MDIO_DEVAD_NONE, 0x1e, val);
 154
 155        return 0;
 156}
 157
 158int board_phy_config(struct phy_device *phydev)
 159{
 160        ar8031_phy_fixup(phydev);
 161
 162        if (phydev->drv->config)
 163                phydev->drv->config(phydev);
 164
 165        return 0;
 166}
 167#endif
 168
 169#ifdef CONFIG_FSL_ESDHC
 170
 171#define USDHC2_CD_GPIO  IMX_GPIO_NR(1, 4)
 172static struct fsl_esdhc_cfg usdhc_cfg[] = {
 173        { USDHC2_BASE_ADDR },
 174        { USDHC4_BASE_ADDR },
 175};
 176
 177int board_mmc_getcd(struct mmc *mmc)
 178{
 179        struct fsl_esdhc_cfg *cfg = (struct fsl_esdhc_cfg *)mmc->priv;
 180
 181        switch (cfg->esdhc_base) {
 182        case USDHC2_BASE_ADDR:
 183                return !gpio_get_value(USDHC2_CD_GPIO);
 184        case USDHC4_BASE_ADDR:
 185                return 1; /* eMMC/uSDHC4 is always present */
 186        }
 187
 188        return 0;
 189}
 190
 191int board_mmc_init(bd_t *bis)
 192{
 193        int i, ret;
 194
 195        /*
 196         * According to the board_mmc_init() the following map is done:
 197         * (U-Boot device node)    (Physical Port)
 198         * mmc0                    micro SD
 199         * mmc2                    eMMC
 200         */
 201        gpio_direction_input(USDHC2_CD_GPIO);
 202
 203        usdhc_cfg[0].sdhc_clk = mxc_get_clock(MXC_ESDHC2_CLK);
 204        usdhc_cfg[1].sdhc_clk = mxc_get_clock(MXC_ESDHC4_CLK);
 205
 206        for (i = 0; i < CONFIG_SYS_FSL_USDHC_NUM; i++) {
 207                ret = fsl_esdhc_initialize(bis, &usdhc_cfg[i]);
 208                if (ret)
 209                        return ret;
 210        }
 211
 212        return 0;
 213}
 214#endif
 215
 216#ifdef CONFIG_USB_EHCI_MX6
 217static void setup_usb(void)
 218{
 219        /*
 220         * Set daisy chain for otg_pin_id on MX6Q.
 221         * For MX6DL, this bit is reserved.
 222         */
 223        imx_iomux_set_gpr_register(1, 13, 1, 0);
 224}
 225
 226int board_usb_phy_mode(int port)
 227{
 228        if (port == 1)
 229                return USB_INIT_HOST;
 230        else
 231                return USB_INIT_DEVICE;
 232}
 233
 234int board_ehci_power(int port, int on)
 235{
 236        switch (port) {
 237        case 0:
 238                break;
 239        case 1:
 240                gpio_direction_output(IMX_GPIO_NR(3, 31), !!on);
 241                break;
 242        default:
 243                printf("MXC USB port %d not yet supported\n", port);
 244                return -EINVAL;
 245        }
 246
 247        return 0;
 248}
 249#endif
 250
 251int board_early_init_f(void)
 252{
 253#ifdef CONFIG_USB_EHCI_MX6
 254        setup_usb();
 255#endif
 256
 257        return 0;
 258}
 259
 260int board_init(void)
 261{
 262        struct mxc_ccm_reg *mxc_ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR;
 263
 264        /* address of boot parameters */
 265        gd->bd->bi_boot_params = PHYS_SDRAM + 0x100;
 266
 267        /* Enable eim_slow clocks */
 268        setbits_le32(&mxc_ccm->CCGR6, 0x1 << MXC_CCM_CCGR6_EMI_SLOW_OFFSET);
 269
 270        setup_i2c(0, CONFIG_SYS_I2C_SPEED, 0x7f, &kp_imx6q_tpc_i2c_pad_info0);
 271        setup_i2c(1, CONFIG_SYS_I2C_SPEED, 0x7f, &kp_imx6q_tpc_i2c_pad_info1);
 272
 273        return 0;
 274}
 275
 276#ifdef CONFIG_CMD_BMODE
 277static const struct boot_mode board_boot_modes[] = {
 278        /* 4 bit bus width */
 279        {"sd2",  MAKE_CFGVAL(0x40, 0x28, 0x00, 0x00)},
 280        /* 8 bit bus width */
 281        {"emmc", MAKE_CFGVAL(0x60, 0x58, 0x00, 0x00)},
 282        {NULL,   0},
 283};
 284#endif
 285
 286int board_late_init(void)
 287{
 288#ifdef CONFIG_CMD_BMODE
 289        add_board_boot_modes(board_boot_modes);
 290#endif
 291
 292        env_set("boardname", "kp-tpc");
 293        env_set("boardsoc", "imx6q");
 294        return 0;
 295}
 296
 297int checkboard(void)
 298{
 299        puts("Board: K+P KP_IMX6Q_TPC i.MX6Q\n");
 300        return 0;
 301}
 302