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9#include <common.h>
10#include <asm/arch/ddr3.h>
11#include <asm/arch/hardware.h>
12#include <asm/ti-common/keystone_net.h>
13
14unsigned int get_external_clk(u32 clk)
15{
16 unsigned int clk_freq;
17
18 switch (clk) {
19 case sys_clk:
20 clk_freq = 122880000;
21 break;
22 case alt_core_clk:
23 clk_freq = 100000000;
24 break;
25 case pa_clk:
26 clk_freq = 122880000;
27 break;
28 case tetris_clk:
29 clk_freq = 122880000;
30 break;
31 case ddr3a_clk:
32 clk_freq = 100000000;
33 break;
34 default:
35 clk_freq = 0;
36 break;
37 }
38
39 return clk_freq;
40}
41
42static struct pll_init_data core_pll_config[NUM_SPDS] = {
43 [SPD800] = CORE_PLL_799,
44 [SPD1000] = CORE_PLL_1000,
45 [SPD1200] = CORE_PLL_1198,
46};
47
48s16 divn_val[16] = {
49 0, 0, 1, 4, 23, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1
50};
51
52static struct pll_init_data tetris_pll_config[] = {
53 [SPD800] = TETRIS_PLL_799,
54 [SPD1000] = TETRIS_PLL_1000,
55 [SPD1200] = TETRIS_PLL_1198,
56 [SPD1350] = TETRIS_PLL_1352,
57 [SPD1400] = TETRIS_PLL_1401,
58};
59
60static struct pll_init_data pa_pll_config =
61 PASS_PLL_983;
62
63struct pll_init_data *get_pll_init_data(int pll)
64{
65 int speed;
66 struct pll_init_data *data;
67
68 switch (pll) {
69 case MAIN_PLL:
70 speed = get_max_dev_speed(speeds);
71 data = &core_pll_config[speed];
72 break;
73 case TETRIS_PLL:
74 speed = get_max_arm_speed(speeds);
75 data = &tetris_pll_config[speed];
76 break;
77 case PASS_PLL:
78 data = &pa_pll_config;
79 break;
80 default:
81 data = NULL;
82 }
83
84 return data;
85}
86
87#ifdef CONFIG_BOARD_EARLY_INIT_F
88int board_early_init_f(void)
89{
90 init_plls();
91
92 return 0;
93}
94#endif
95
96#if defined(CONFIG_MULTI_DTB_FIT)
97int board_fit_config_name_match(const char *name)
98{
99 if (!strcmp(name, "keystone-k2l-evm"))
100 return 0;
101
102 return -1;
103}
104#endif
105
106#ifdef CONFIG_SPL_BUILD
107void spl_init_keystone_plls(void)
108{
109 init_plls();
110}
111#endif
112