LXR uboot/drivers/mtd/spi/sf

   1/* SPDX-License-Identifier: GPL-2.0+ */
   2/*
   3 * SPI flash internal definitions
   4 *
   5 * Copyright (C) 2008 Atmel Corporation
   6 * Copyright (C) 2013 Jagannadha Sutradharudu Teki, Xilinx Inc.
   7 */
   8
   9#ifndef _SF_INTERNAL_H_
  10#define _SF_INTERNAL_H_
  11
  12#include <linux/types.h>
  13#include <linux/compiler.h>
  14
  15/* Dual SPI flash memories - see SPI_COMM_DUAL_... */
  16enum spi_dual_flash {
  17        SF_SINGLE_FLASH = 0,
  18        SF_DUAL_STACKED_FLASH   = BIT(0),
  19        SF_DUAL_PARALLEL_FLASH  = BIT(1),
  20};
  21
  22enum spi_nor_option_flags {
  23        SNOR_F_SST_WR           = BIT(0),
  24        SNOR_F_USE_FSR          = BIT(1),
  25        SNOR_F_USE_UPAGE        = BIT(3),
  26};
  27
  28#define SPI_FLASH_3B_ADDR_LEN           3
  29#define SPI_FLASH_CMD_LEN               (1 + SPI_FLASH_3B_ADDR_LEN)
  30#define SPI_FLASH_16MB_BOUN             0x1000000
  31
  32/* CFI Manufacture ID's */
  33#define SPI_FLASH_CFI_MFR_SPANSION      0x01
  34#define SPI_FLASH_CFI_MFR_STMICRO       0x20
  35#define SPI_FLASH_CFI_MFR_MICRON        0x2C
  36#define SPI_FLASH_CFI_MFR_MACRONIX      0xc2
  37#define SPI_FLASH_CFI_MFR_SST           0xbf
  38#define SPI_FLASH_CFI_MFR_WINBOND       0xef
  39#define SPI_FLASH_CFI_MFR_ATMEL         0x1f
  40
  41/* Erase commands */
  42#define CMD_ERASE_4K                    0x20
  43#define CMD_ERASE_CHIP                  0xc7
  44#define CMD_ERASE_64K                   0xd8
  45
  46/* Write commands */
  47#define CMD_WRITE_STATUS                0x01
  48#define CMD_PAGE_PROGRAM                0x02
  49#define CMD_WRITE_DISABLE               0x04
  50#define CMD_WRITE_ENABLE                0x06
  51#define CMD_QUAD_PAGE_PROGRAM           0x32
  52
  53/* Read commands */
  54#define CMD_READ_ARRAY_SLOW             0x03
  55#define CMD_READ_ARRAY_FAST             0x0b
  56#define CMD_READ_DUAL_OUTPUT_FAST       0x3b
  57#define CMD_READ_DUAL_IO_FAST           0xbb
  58#define CMD_READ_QUAD_OUTPUT_FAST       0x6b
  59#define CMD_READ_QUAD_IO_FAST           0xeb
  60#define CMD_READ_ID                     0x9f
  61#define CMD_READ_STATUS                 0x05
  62#define CMD_READ_STATUS1                0x35
  63#define CMD_READ_CONFIG                 0x35
  64#define CMD_FLAG_STATUS                 0x70
  65
  66/* Bank addr access commands */
  67#ifdef CONFIG_SPI_FLASH_BAR
  68# define CMD_BANKADDR_BRWR              0x17
  69# define CMD_BANKADDR_BRRD              0x16
  70# define CMD_EXTNADDR_WREAR             0xC5
  71# define CMD_EXTNADDR_RDEAR             0xC8
  72#endif
  73
  74/* Common status */
  75#define STATUS_WIP                      BIT(0)
  76#define STATUS_QEB_WINSPAN              BIT(1)
  77#define STATUS_QEB_MXIC                 BIT(6)
  78#define STATUS_PEC                      BIT(7)
  79#define SR_BP0                          BIT(2)  /* Block protect 0 */
  80#define SR_BP1                          BIT(3)  /* Block protect 1 */
  81#define SR_BP2                          BIT(4)  /* Block protect 2 */
  82
  83/* Flash timeout values */
  84#define SPI_FLASH_PROG_TIMEOUT          (2 * CONFIG_SYS_HZ)
  85#define SPI_FLASH_PAGE_ERASE_TIMEOUT    (5 * CONFIG_SYS_HZ)
  86#define SPI_FLASH_SECTOR_ERASE_TIMEOUT  (10 * CONFIG_SYS_HZ)
  87
  88/* SST specific */
  89#ifdef CONFIG_SPI_FLASH_SST
  90#define SST26_CMD_READ_BPR              0x72
  91#define SST26_CMD_WRITE_BPR             0x42
  92
  93#define SST26_BPR_8K_NUM                4
  94#define SST26_MAX_BPR_REG_LEN           (18 + 1)
  95#define SST26_BOUND_REG_SIZE            ((32 + SST26_BPR_8K_NUM * 8) * SZ_1K)
  96
  97enum lock_ctl {
  98        SST26_CTL_LOCK,
  99        SST26_CTL_UNLOCK,
 100        SST26_CTL_CHECK
 101};
 102
 103# define CMD_SST_BP             0x02    /* Byte Program */
 104# define CMD_SST_AAI_WP         0xAD    /* Auto Address Incr Word Program */
 105
 106int sst_write_wp(struct spi_flash *flash, u32 offset, size_t len,
 107                const void *buf);
 108int sst_write_bp(struct spi_flash *flash, u32 offset, size_t len,
 109                const void *buf);
 110#endif
 111
 112#define JEDEC_MFR(info)         ((info)->id[0])
 113#define JEDEC_ID(info)          (((info)->id[1]) << 8 | ((info)->id[2]))
 114#define JEDEC_EXT(info)         (((info)->id[3]) << 8 | ((info)->id[4]))
 115#define SPI_FLASH_MAX_ID_LEN    6
 116
 117struct spi_flash_info {
 118        /* Device name ([MANUFLETTER][DEVTYPE][DENSITY][EXTRAINFO]) */
 119        const char      *name;
 120
 121        /*
 122         * This array stores the ID bytes.
 123         * The first three bytes are the JEDIC ID.
 124         * JEDEC ID zero means "no ID" (mostly older chips).
 125         */
 126        u8              id[SPI_FLASH_MAX_ID_LEN];
 127        u8              id_len;
 128
 129        /*
 130         * The size listed here is what works with SPINOR_OP_SE, which isn't
 131         * necessarily called a "sector" by the vendor.
 132         */
 133        u32             sector_size;
 134        u32             n_sectors;
 135
 136        u16             page_size;
 137
 138        u16             flags;
 139#define SECT_4K                 BIT(0)  /* CMD_ERASE_4K works uniformly */
 140#define E_FSR                   BIT(1)  /* use flag status register for */
 141#define SST_WR                  BIT(2)  /* use SST byte/word programming */
 142#define WR_QPP                  BIT(3)  /* use Quad Page Program */
 143#define RD_QUAD                 BIT(4)  /* use Quad Read */
 144#define RD_DUAL                 BIT(5)  /* use Dual Read */
 145#define RD_QUADIO               BIT(6)  /* use Quad IO Read */
 146#define RD_DUALIO               BIT(7)  /* use Dual IO Read */
 147#define RD_FULL                 (RD_QUAD | RD_DUAL | RD_QUADIO | RD_DUALIO)
 148};
 149
 150extern const struct spi_flash_info spi_flash_ids[];
 151
 152/* Send a single-byte command to the device and read the response */
 153int spi_flash_cmd(struct spi_slave *spi, u8 cmd, void *response, size_t len);
 154
 155/*
 156 * Send a multi-byte command to the device and read the response. Used
 157 * for flash array reads, etc.
 158 */
 159int spi_flash_cmd_read(struct spi_slave *spi, const u8 *cmd,
 160                size_t cmd_len, void *data, size_t data_len);
 161
 162/*
 163 * Send a multi-byte command to the device followed by (optional)
 164 * data. Used for programming the flash array, etc.
 165 */
 166int spi_flash_cmd_write(struct spi_slave *spi, const u8 *cmd, size_t cmd_len,
 167                const void *data, size_t data_len);
 168
 169
 170/* Flash erase(sectors) operation, support all possible erase commands */
 171int spi_flash_cmd_erase_ops(struct spi_flash *flash, u32 offset, size_t len);
 172
 173/* Get software write-protect value (BP bits) */
 174int spi_flash_cmd_get_sw_write_prot(struct spi_flash *flash);
 175
 176/* Lock stmicro spi flash region */
 177int stm_lock(struct spi_flash *flash, u32 ofs, size_t len);
 178
 179/* Unlock stmicro spi flash region */
 180int stm_unlock(struct spi_flash *flash, u32 ofs, size_t len);
 181
 182/* Check if a stmicro spi flash region is completely locked */
 183int stm_is_locked(struct spi_flash *flash, u32 ofs, size_t len);
 184
 185/* Enable writing on the SPI flash */
 186static inline int spi_flash_cmd_write_enable(struct spi_flash *flash)
 187{
 188        return spi_flash_cmd(flash->spi, CMD_WRITE_ENABLE, NULL, 0);
 189}
 190
 191/* Disable writing on the SPI flash */
 192static inline int spi_flash_cmd_write_disable(struct spi_flash *flash)
 193{
 194        return spi_flash_cmd(flash->spi, CMD_WRITE_DISABLE, NULL, 0);
 195}
 196
 197/*
 198 * Used for spi_flash write operation
 199 * - SPI claim
 200 * - spi_flash_cmd_write_enable
 201 * - spi_flash_cmd_write
 202 * - spi_flash_wait_till_ready
 203 * - SPI release
 204 */
 205int spi_flash_write_common(struct spi_flash *flash, const u8 *cmd,
 206                size_t cmd_len, const void *buf, size_t buf_len);
 207
 208/*
 209 * Flash write operation, support all possible write commands.
 210 * Write the requested data out breaking it up into multiple write
 211 * commands as needed per the write size.
 212 */
 213int spi_flash_cmd_write_ops(struct spi_flash *flash, u32 offset,
 214                size_t len, const void *buf);
 215
 216/*
 217 * Same as spi_flash_cmd_read() except it also claims/releases the SPI
 218 * bus. Used as common part of the ->read() operation.
 219 */
 220int spi_flash_read_common(struct spi_flash *flash, const u8 *cmd,
 221                size_t cmd_len, void *data, size_t data_len);
 222
 223/* Flash read operation, support all possible read commands */
 224int spi_flash_cmd_read_ops(struct spi_flash *flash, u32 offset,
 225                size_t len, void *data);
 226
 227#ifdef CONFIG_SPI_FLASH_MTD
 228int spi_flash_mtd_register(struct spi_flash *flash);
 229void spi_flash_mtd_unregister(void);
 230#endif
 231
 232/**
 233 * spi_flash_scan - scan the SPI FLASH
 234 * @flash:      the spi flash structure
 235 *
 236 * The drivers can use this fuction to scan the SPI FLASH.
 237 * In the scanning, it will try to get all the necessary information to
 238 * fill the spi_flash{}.
 239 *
 240 * Return: 0 for success, others for failure.
 241 */
 242int spi_flash_scan(struct spi_flash *flash);
 243
 244#endif /* _SF_INTERNAL_H_ */
 245