uboot/drivers/usb/eth/asix88179.c
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   1// SPDX-License-Identifier: GPL-2.0+
   2/*
   3 * Copyright (c) 2014 Rene Griessl <rgriessl@cit-ec.uni-bielefeld.de>
   4 * based on the U-Boot Asix driver as well as information
   5 * from the Linux AX88179_178a driver
   6 */
   7
   8#include <common.h>
   9#include <dm.h>
  10#include <usb.h>
  11#include <net.h>
  12#include <linux/mii.h>
  13#include "usb_ether.h"
  14#include <malloc.h>
  15#include <memalign.h>
  16#include <errno.h>
  17
  18/* ASIX AX88179 based USB 3.0 Ethernet Devices */
  19#define AX88179_PHY_ID                          0x03
  20#define AX_EEPROM_LEN                           0x100
  21#define AX88179_EEPROM_MAGIC                    0x17900b95
  22#define AX_MCAST_FLTSIZE                        8
  23#define AX_MAX_MCAST                            64
  24#define AX_INT_PPLS_LINK                        (1 << 16)
  25#define AX_RXHDR_L4_TYPE_MASK                   0x1c
  26#define AX_RXHDR_L4_TYPE_UDP                    4
  27#define AX_RXHDR_L4_TYPE_TCP                    16
  28#define AX_RXHDR_L3CSUM_ERR                     2
  29#define AX_RXHDR_L4CSUM_ERR                     1
  30#define AX_RXHDR_CRC_ERR                        (1 << 29)
  31#define AX_RXHDR_DROP_ERR                       (1 << 31)
  32#define AX_ENDPOINT_INT                         0x01
  33#define AX_ENDPOINT_IN                          0x02
  34#define AX_ENDPOINT_OUT                         0x03
  35#define AX_ACCESS_MAC                           0x01
  36#define AX_ACCESS_PHY                           0x02
  37#define AX_ACCESS_EEPROM                        0x04
  38#define AX_ACCESS_EFUS                          0x05
  39#define AX_PAUSE_WATERLVL_HIGH                  0x54
  40#define AX_PAUSE_WATERLVL_LOW                   0x55
  41
  42#define PHYSICAL_LINK_STATUS                    0x02
  43        #define AX_USB_SS               (1 << 2)
  44        #define AX_USB_HS               (1 << 1)
  45
  46#define GENERAL_STATUS                          0x03
  47        #define AX_SECLD                (1 << 2)
  48
  49#define AX_SROM_ADDR                            0x07
  50#define AX_SROM_CMD                             0x0a
  51        #define EEP_RD                  (1 << 2)
  52        #define EEP_BUSY                (1 << 4)
  53
  54#define AX_SROM_DATA_LOW                        0x08
  55#define AX_SROM_DATA_HIGH                       0x09
  56
  57#define AX_RX_CTL                               0x0b
  58        #define AX_RX_CTL_DROPCRCERR    (1 << 8)
  59        #define AX_RX_CTL_IPE           (1 << 9)
  60        #define AX_RX_CTL_START         (1 << 7)
  61        #define AX_RX_CTL_AP            (1 << 5)
  62        #define AX_RX_CTL_AM            (1 << 4)
  63        #define AX_RX_CTL_AB            (1 << 3)
  64        #define AX_RX_CTL_AMALL         (1 << 1)
  65        #define AX_RX_CTL_PRO           (1 << 0)
  66        #define AX_RX_CTL_STOP          0
  67
  68#define AX_NODE_ID                              0x10
  69#define AX_MULFLTARY                            0x16
  70
  71#define AX_MEDIUM_STATUS_MODE                   0x22
  72        #define AX_MEDIUM_GIGAMODE      (1 << 0)
  73        #define AX_MEDIUM_FULL_DUPLEX   (1 << 1)
  74        #define AX_MEDIUM_EN_125MHZ     (1 << 3)
  75        #define AX_MEDIUM_RXFLOW_CTRLEN (1 << 4)
  76        #define AX_MEDIUM_TXFLOW_CTRLEN (1 << 5)
  77        #define AX_MEDIUM_RECEIVE_EN    (1 << 8)
  78        #define AX_MEDIUM_PS            (1 << 9)
  79        #define AX_MEDIUM_JUMBO_EN      0x8040
  80
  81#define AX_MONITOR_MOD                          0x24
  82        #define AX_MONITOR_MODE_RWLC    (1 << 1)
  83        #define AX_MONITOR_MODE_RWMP    (1 << 2)
  84        #define AX_MONITOR_MODE_PMEPOL  (1 << 5)
  85        #define AX_MONITOR_MODE_PMETYPE (1 << 6)
  86
  87#define AX_GPIO_CTRL                            0x25
  88        #define AX_GPIO_CTRL_GPIO3EN    (1 << 7)
  89        #define AX_GPIO_CTRL_GPIO2EN    (1 << 6)
  90        #define AX_GPIO_CTRL_GPIO1EN    (1 << 5)
  91
  92#define AX_PHYPWR_RSTCTL                        0x26
  93        #define AX_PHYPWR_RSTCTL_BZ     (1 << 4)
  94        #define AX_PHYPWR_RSTCTL_IPRL   (1 << 5)
  95        #define AX_PHYPWR_RSTCTL_AT     (1 << 12)
  96
  97#define AX_RX_BULKIN_QCTRL                      0x2e
  98#define AX_CLK_SELECT                           0x33
  99        #define AX_CLK_SELECT_BCS       (1 << 0)
 100        #define AX_CLK_SELECT_ACS       (1 << 1)
 101        #define AX_CLK_SELECT_ULR       (1 << 3)
 102
 103#define AX_RXCOE_CTL                            0x34
 104        #define AX_RXCOE_IP             (1 << 0)
 105        #define AX_RXCOE_TCP            (1 << 1)
 106        #define AX_RXCOE_UDP            (1 << 2)
 107        #define AX_RXCOE_TCPV6          (1 << 5)
 108        #define AX_RXCOE_UDPV6          (1 << 6)
 109
 110#define AX_TXCOE_CTL                            0x35
 111        #define AX_TXCOE_IP             (1 << 0)
 112        #define AX_TXCOE_TCP            (1 << 1)
 113        #define AX_TXCOE_UDP            (1 << 2)
 114        #define AX_TXCOE_TCPV6          (1 << 5)
 115        #define AX_TXCOE_UDPV6          (1 << 6)
 116
 117#define AX_LEDCTRL                              0x73
 118
 119#define GMII_PHY_PHYSR                          0x11
 120        #define GMII_PHY_PHYSR_SMASK    0xc000
 121        #define GMII_PHY_PHYSR_GIGA     (1 << 15)
 122        #define GMII_PHY_PHYSR_100      (1 << 14)
 123        #define GMII_PHY_PHYSR_FULL     (1 << 13)
 124        #define GMII_PHY_PHYSR_LINK     (1 << 10)
 125
 126#define GMII_LED_ACT                            0x1a
 127        #define GMII_LED_ACTIVE_MASK    0xff8f
 128        #define GMII_LED0_ACTIVE        (1 << 4)
 129        #define GMII_LED1_ACTIVE        (1 << 5)
 130        #define GMII_LED2_ACTIVE        (1 << 6)
 131
 132#define GMII_LED_LINK                           0x1c
 133        #define GMII_LED_LINK_MASK      0xf888
 134        #define GMII_LED0_LINK_10       (1 << 0)
 135        #define GMII_LED0_LINK_100      (1 << 1)
 136        #define GMII_LED0_LINK_1000     (1 << 2)
 137        #define GMII_LED1_LINK_10       (1 << 4)
 138        #define GMII_LED1_LINK_100      (1 << 5)
 139        #define GMII_LED1_LINK_1000     (1 << 6)
 140        #define GMII_LED2_LINK_10       (1 << 8)
 141        #define GMII_LED2_LINK_100      (1 << 9)
 142        #define GMII_LED2_LINK_1000     (1 << 10)
 143        #define LED0_ACTIVE             (1 << 0)
 144        #define LED0_LINK_10            (1 << 1)
 145        #define LED0_LINK_100           (1 << 2)
 146        #define LED0_LINK_1000          (1 << 3)
 147        #define LED0_FD                 (1 << 4)
 148        #define LED0_USB3_MASK          0x001f
 149        #define LED1_ACTIVE             (1 << 5)
 150        #define LED1_LINK_10            (1 << 6)
 151        #define LED1_LINK_100           (1 << 7)
 152        #define LED1_LINK_1000          (1 << 8)
 153        #define LED1_FD                 (1 << 9)
 154        #define LED1_USB3_MASK          0x03e0
 155        #define LED2_ACTIVE             (1 << 10)
 156        #define LED2_LINK_1000          (1 << 13)
 157        #define LED2_LINK_100           (1 << 12)
 158        #define LED2_LINK_10            (1 << 11)
 159        #define LED2_FD                 (1 << 14)
 160        #define LED_VALID               (1 << 15)
 161        #define LED2_USB3_MASK          0x7c00
 162
 163#define GMII_PHYPAGE                            0x1e
 164#define GMII_PHY_PAGE_SELECT                    0x1f
 165        #define GMII_PHY_PGSEL_EXT      0x0007
 166        #define GMII_PHY_PGSEL_PAGE0    0x0000
 167
 168/* local defines */
 169#define ASIX_BASE_NAME "axg"
 170#define USB_CTRL_SET_TIMEOUT 5000
 171#define USB_CTRL_GET_TIMEOUT 5000
 172#define USB_BULK_SEND_TIMEOUT 5000
 173#define USB_BULK_RECV_TIMEOUT 5000
 174
 175#define AX_RX_URB_SIZE 1024 * 0x12
 176#define BLK_FRAME_SIZE 0x200
 177#define PHY_CONNECT_TIMEOUT 5000
 178
 179#define TIMEOUT_RESOLUTION 50   /* ms */
 180
 181#define FLAG_NONE                       0
 182#define FLAG_TYPE_AX88179       (1U << 0)
 183#define FLAG_TYPE_AX88178a      (1U << 1)
 184#define FLAG_TYPE_DLINK_DUB1312 (1U << 2)
 185#define FLAG_TYPE_SITECOM       (1U << 3)
 186#define FLAG_TYPE_SAMSUNG       (1U << 4)
 187#define FLAG_TYPE_LENOVO        (1U << 5)
 188#define FLAG_TYPE_GX3           (1U << 6)
 189
 190/* local vars */
 191static const struct {
 192        unsigned char ctrl, timer_l, timer_h, size, ifg;
 193} AX88179_BULKIN_SIZE[] =       {
 194        {7, 0x4f, 0,    0x02, 0xff},
 195        {7, 0x20, 3,    0x03, 0xff},
 196        {7, 0xae, 7,    0x04, 0xff},
 197        {7, 0xcc, 0x4c, 0x04, 8},
 198};
 199
 200#ifndef CONFIG_DM_ETH
 201static int curr_eth_dev; /* index for name of next device detected */
 202#endif
 203
 204/* driver private */
 205struct asix_private {
 206#ifdef CONFIG_DM_ETH
 207        struct ueth_data ueth;
 208        unsigned pkt_cnt;
 209        uint8_t *pkt_data;
 210        uint32_t *pkt_hdr;
 211#endif
 212        int flags;
 213        int rx_urb_size;
 214        int maxpacketsize;
 215};
 216
 217/*
 218 * Asix infrastructure commands
 219 */
 220static int asix_write_cmd(struct ueth_data *dev, u8 cmd, u16 value, u16 index,
 221                             u16 size, void *data)
 222{
 223        int len;
 224        ALLOC_CACHE_ALIGN_BUFFER(unsigned char, buf, size);
 225
 226        debug("asix_write_cmd() cmd=0x%02x value=0x%04x index=0x%04x size=%d\n",
 227              cmd, value, index, size);
 228
 229        memcpy(buf, data, size);
 230
 231        len = usb_control_msg(
 232                dev->pusb_dev,
 233                usb_sndctrlpipe(dev->pusb_dev, 0),
 234                cmd,
 235                USB_DIR_OUT | USB_TYPE_VENDOR | USB_RECIP_DEVICE,
 236                value,
 237                index,
 238                buf,
 239                size,
 240                USB_CTRL_SET_TIMEOUT);
 241
 242        return len == size ? 0 : ECOMM;
 243}
 244
 245static int asix_read_cmd(struct ueth_data *dev, u8 cmd, u16 value, u16 index,
 246                            u16 size, void *data)
 247{
 248        int len;
 249        ALLOC_CACHE_ALIGN_BUFFER(unsigned char, buf, size);
 250
 251        debug("asix_read_cmd() cmd=0x%02x value=0x%04x index=0x%04x size=%d\n",
 252              cmd, value, index, size);
 253
 254        len = usb_control_msg(
 255                dev->pusb_dev,
 256                usb_rcvctrlpipe(dev->pusb_dev, 0),
 257                cmd,
 258                USB_DIR_IN | USB_TYPE_VENDOR | USB_RECIP_DEVICE,
 259                value,
 260                index,
 261                buf,
 262                size,
 263                USB_CTRL_GET_TIMEOUT);
 264
 265        memcpy(data, buf, size);
 266
 267        return len == size ? 0 : ECOMM;
 268}
 269
 270static int asix_read_mac(struct ueth_data *dev, uint8_t *enetaddr)
 271{
 272        int ret;
 273
 274        ret = asix_read_cmd(dev, AX_ACCESS_MAC, AX_NODE_ID, 6, 6, enetaddr);
 275        if (ret < 0)
 276                debug("Failed to read MAC address: %02x\n", ret);
 277
 278        return ret;
 279}
 280
 281static int asix_write_mac(struct ueth_data *dev, uint8_t *enetaddr)
 282{
 283        int ret;
 284
 285        ret = asix_write_cmd(dev, AX_ACCESS_MAC, AX_NODE_ID, ETH_ALEN,
 286                                 ETH_ALEN, enetaddr);
 287        if (ret < 0)
 288                debug("Failed to set MAC address: %02x\n", ret);
 289
 290        return ret;
 291}
 292
 293static int asix_basic_reset(struct ueth_data *dev,
 294                        struct asix_private *dev_priv)
 295{
 296        u8 buf[5];
 297        u16 *tmp16;
 298        u8 *tmp;
 299
 300        tmp16 = (u16 *)buf;
 301        tmp = (u8 *)buf;
 302
 303        /* Power up ethernet PHY */
 304        *tmp16 = 0;
 305        asix_write_cmd(dev, AX_ACCESS_MAC, AX_PHYPWR_RSTCTL, 2, 2, tmp16);
 306
 307        *tmp16 = AX_PHYPWR_RSTCTL_IPRL;
 308        asix_write_cmd(dev, AX_ACCESS_MAC, AX_PHYPWR_RSTCTL, 2, 2, tmp16);
 309        mdelay(200);
 310
 311        *tmp = AX_CLK_SELECT_ACS | AX_CLK_SELECT_BCS;
 312        asix_write_cmd(dev, AX_ACCESS_MAC, AX_CLK_SELECT, 1, 1, tmp);
 313        mdelay(200);
 314
 315        /* RX bulk configuration */
 316        memcpy(tmp, &AX88179_BULKIN_SIZE[0], 5);
 317        asix_write_cmd(dev, AX_ACCESS_MAC, AX_RX_BULKIN_QCTRL, 5, 5, tmp);
 318
 319        dev_priv->rx_urb_size = 128 * 20;
 320
 321        /* Water Level configuration */
 322        *tmp = 0x34;
 323        asix_write_cmd(dev, AX_ACCESS_MAC, AX_PAUSE_WATERLVL_LOW, 1, 1, tmp);
 324
 325        *tmp = 0x52;
 326        asix_write_cmd(dev, AX_ACCESS_MAC, AX_PAUSE_WATERLVL_HIGH, 1, 1, tmp);
 327
 328        /* Enable checksum offload */
 329        *tmp = AX_RXCOE_IP | AX_RXCOE_TCP | AX_RXCOE_UDP |
 330               AX_RXCOE_TCPV6 | AX_RXCOE_UDPV6;
 331        asix_write_cmd(dev, AX_ACCESS_MAC, AX_RXCOE_CTL, 1, 1, tmp);
 332
 333        *tmp = AX_TXCOE_IP | AX_TXCOE_TCP | AX_TXCOE_UDP |
 334               AX_TXCOE_TCPV6 | AX_TXCOE_UDPV6;
 335        asix_write_cmd(dev, AX_ACCESS_MAC, AX_TXCOE_CTL, 1, 1, tmp);
 336
 337        /* Configure RX control register => start operation */
 338        *tmp16 = AX_RX_CTL_DROPCRCERR | AX_RX_CTL_IPE | AX_RX_CTL_START |
 339                 AX_RX_CTL_AP | AX_RX_CTL_AMALL | AX_RX_CTL_AB;
 340        asix_write_cmd(dev, AX_ACCESS_MAC, AX_RX_CTL, 2, 2, tmp16);
 341
 342        *tmp = AX_MONITOR_MODE_PMETYPE | AX_MONITOR_MODE_PMEPOL |
 343               AX_MONITOR_MODE_RWMP;
 344        asix_write_cmd(dev, AX_ACCESS_MAC, AX_MONITOR_MOD, 1, 1, tmp);
 345
 346        /* Configure default medium type => giga */
 347        *tmp16 = AX_MEDIUM_RECEIVE_EN | AX_MEDIUM_TXFLOW_CTRLEN |
 348                 AX_MEDIUM_RXFLOW_CTRLEN | AX_MEDIUM_FULL_DUPLEX |
 349                 AX_MEDIUM_GIGAMODE | AX_MEDIUM_JUMBO_EN;
 350        asix_write_cmd(dev, AX_ACCESS_MAC, AX_MEDIUM_STATUS_MODE, 2, 2, tmp16);
 351
 352        u16 adv = 0;
 353        adv = ADVERTISE_ALL | ADVERTISE_CSMA | ADVERTISE_LPACK |
 354              ADVERTISE_NPAGE | ADVERTISE_PAUSE_ASYM | ADVERTISE_PAUSE_CAP;
 355        asix_write_cmd(dev, AX_ACCESS_PHY, 0x03, MII_ADVERTISE, 2, &adv);
 356
 357        adv = ADVERTISE_1000FULL;
 358        asix_write_cmd(dev, AX_ACCESS_PHY, 0x03, MII_CTRL1000, 2, &adv);
 359
 360        return 0;
 361}
 362
 363static int asix_wait_link(struct ueth_data *dev)
 364{
 365        int timeout = 0;
 366        int link_detected;
 367        u8 buf[2];
 368        u16 *tmp16;
 369
 370        tmp16 = (u16 *)buf;
 371
 372        do {
 373                asix_read_cmd(dev, AX_ACCESS_PHY, AX88179_PHY_ID,
 374                              MII_BMSR, 2, buf);
 375                link_detected = *tmp16 & BMSR_LSTATUS;
 376                if (!link_detected) {
 377                        if (timeout == 0)
 378                                printf("Waiting for Ethernet connection... ");
 379                        mdelay(TIMEOUT_RESOLUTION);
 380                        timeout += TIMEOUT_RESOLUTION;
 381                }
 382        } while (!link_detected && timeout < PHY_CONNECT_TIMEOUT);
 383
 384        if (link_detected) {
 385                if (timeout > 0)
 386                        printf("done.\n");
 387                return 0;
 388        } else {
 389                printf("unable to connect.\n");
 390                return -ENETUNREACH;
 391        }
 392}
 393
 394static int asix_init_common(struct ueth_data *dev,
 395                        struct asix_private *dev_priv)
 396{
 397        u8 buf[2], tmp[5], link_sts;
 398        u16 *tmp16, mode;
 399
 400
 401        tmp16 = (u16 *)buf;
 402
 403        debug("** %s()\n", __func__);
 404
 405        /* Configure RX control register => start operation */
 406        *tmp16 = AX_RX_CTL_DROPCRCERR | AX_RX_CTL_IPE | AX_RX_CTL_START |
 407                 AX_RX_CTL_AP | AX_RX_CTL_AMALL | AX_RX_CTL_AB;
 408        if (asix_write_cmd(dev, AX_ACCESS_MAC, AX_RX_CTL, 2, 2, tmp16) != 0)
 409                goto out_err;
 410
 411        if (asix_wait_link(dev) != 0) {
 412                /*reset device and try again*/
 413                printf("Reset Ethernet Device\n");
 414                asix_basic_reset(dev, dev_priv);
 415                if (asix_wait_link(dev) != 0)
 416                        goto out_err;
 417        }
 418
 419        /* Configure link */
 420        mode = AX_MEDIUM_RECEIVE_EN | AX_MEDIUM_TXFLOW_CTRLEN |
 421               AX_MEDIUM_RXFLOW_CTRLEN;
 422
 423        asix_read_cmd(dev, AX_ACCESS_MAC, PHYSICAL_LINK_STATUS,
 424                      1, 1, &link_sts);
 425
 426        asix_read_cmd(dev, AX_ACCESS_PHY, AX88179_PHY_ID,
 427                      GMII_PHY_PHYSR, 2, tmp16);
 428
 429        if (!(*tmp16 & GMII_PHY_PHYSR_LINK)) {
 430                return 0;
 431        } else if (GMII_PHY_PHYSR_GIGA == (*tmp16 & GMII_PHY_PHYSR_SMASK)) {
 432                mode |= AX_MEDIUM_GIGAMODE | AX_MEDIUM_EN_125MHZ |
 433                        AX_MEDIUM_JUMBO_EN;
 434
 435                if (link_sts & AX_USB_SS)
 436                        memcpy(tmp, &AX88179_BULKIN_SIZE[0], 5);
 437                else if (link_sts & AX_USB_HS)
 438                        memcpy(tmp, &AX88179_BULKIN_SIZE[1], 5);
 439                else
 440                        memcpy(tmp, &AX88179_BULKIN_SIZE[3], 5);
 441        } else if (GMII_PHY_PHYSR_100 == (*tmp16 & GMII_PHY_PHYSR_SMASK)) {
 442                mode |= AX_MEDIUM_PS;
 443
 444                if (link_sts & (AX_USB_SS | AX_USB_HS))
 445                        memcpy(tmp, &AX88179_BULKIN_SIZE[2], 5);
 446                else
 447                        memcpy(tmp, &AX88179_BULKIN_SIZE[3], 5);
 448        } else {
 449                memcpy(tmp, &AX88179_BULKIN_SIZE[3], 5);
 450        }
 451
 452        /* RX bulk configuration */
 453        asix_write_cmd(dev, AX_ACCESS_MAC, AX_RX_BULKIN_QCTRL, 5, 5, tmp);
 454
 455        dev_priv->rx_urb_size = (1024 * (tmp[3] + 2));
 456        if (*tmp16 & GMII_PHY_PHYSR_FULL)
 457                mode |= AX_MEDIUM_FULL_DUPLEX;
 458        asix_write_cmd(dev, AX_ACCESS_MAC, AX_MEDIUM_STATUS_MODE,
 459                       2, 2, &mode);
 460
 461        return 0;
 462out_err:
 463        return -1;
 464}
 465
 466static int asix_send_common(struct ueth_data *dev,
 467                        struct asix_private *dev_priv,
 468                        void *packet, int length)
 469{
 470        int err;
 471        u32 packet_len, tx_hdr2;
 472        int actual_len, framesize;
 473        ALLOC_CACHE_ALIGN_BUFFER(unsigned char, msg,
 474                                 PKTSIZE + (2 * sizeof(packet_len)));
 475
 476        debug("** %s(), len %d\n", __func__, length);
 477
 478        packet_len = length;
 479        cpu_to_le32s(&packet_len);
 480
 481        memcpy(msg, &packet_len, sizeof(packet_len));
 482        framesize = dev_priv->maxpacketsize;
 483        tx_hdr2 = 0;
 484        if (((length + 8) % framesize) == 0)
 485                tx_hdr2 |= 0x80008000;  /* Enable padding */
 486
 487        cpu_to_le32s(&tx_hdr2);
 488
 489        memcpy(msg + sizeof(packet_len), &tx_hdr2, sizeof(tx_hdr2));
 490
 491        memcpy(msg + sizeof(packet_len) + sizeof(tx_hdr2),
 492               (void *)packet, length);
 493
 494        err = usb_bulk_msg(dev->pusb_dev,
 495                                usb_sndbulkpipe(dev->pusb_dev, dev->ep_out),
 496                                (void *)msg,
 497                                length + sizeof(packet_len) + sizeof(tx_hdr2),
 498                                &actual_len,
 499                                USB_BULK_SEND_TIMEOUT);
 500        debug("Tx: len = %zu, actual = %u, err = %d\n",
 501              length + sizeof(packet_len), actual_len, err);
 502
 503        return err;
 504}
 505
 506#ifndef CONFIG_DM_ETH
 507/*
 508 * Asix callbacks
 509 */
 510static int asix_init(struct eth_device *eth, bd_t *bd)
 511{
 512        struct ueth_data *dev = (struct ueth_data *)eth->priv;
 513        struct asix_private *dev_priv = (struct asix_private *)dev->dev_priv;
 514
 515        return asix_init_common(dev, dev_priv);
 516}
 517
 518static int asix_write_hwaddr(struct eth_device *eth)
 519{
 520        struct ueth_data *dev = (struct ueth_data *)eth->priv;
 521
 522        return asix_write_mac(dev, eth->enetaddr);
 523}
 524
 525static int asix_send(struct eth_device *eth, void *packet, int length)
 526{
 527        struct ueth_data *dev = (struct ueth_data *)eth->priv;
 528        struct asix_private *dev_priv = (struct asix_private *)dev->dev_priv;
 529
 530        return asix_send_common(dev, dev_priv, packet, length);
 531}
 532
 533static int asix_recv(struct eth_device *eth)
 534{
 535        struct ueth_data *dev = (struct ueth_data *)eth->priv;
 536        struct asix_private *dev_priv = (struct asix_private *)dev->dev_priv;
 537
 538        u16 frame_pos;
 539        int err;
 540        int actual_len;
 541
 542        int pkt_cnt;
 543        u32 rx_hdr;
 544        u16 hdr_off;
 545        u32 *pkt_hdr;
 546        ALLOC_CACHE_ALIGN_BUFFER(u8, recv_buf, dev_priv->rx_urb_size);
 547
 548        actual_len = -1;
 549
 550        debug("** %s()\n", __func__);
 551
 552        err = usb_bulk_msg(dev->pusb_dev,
 553                                usb_rcvbulkpipe(dev->pusb_dev, dev->ep_in),
 554                                (void *)recv_buf,
 555                                dev_priv->rx_urb_size,
 556                                &actual_len,
 557                                USB_BULK_RECV_TIMEOUT);
 558        debug("Rx: len = %u, actual = %u, err = %d\n", dev_priv->rx_urb_size,
 559              actual_len, err);
 560
 561        if (err != 0) {
 562                debug("Rx: failed to receive\n");
 563                return -ECOMM;
 564        }
 565        if (actual_len > dev_priv->rx_urb_size) {
 566                debug("Rx: received too many bytes %d\n", actual_len);
 567                return -EMSGSIZE;
 568        }
 569
 570
 571        rx_hdr = *(u32 *)(recv_buf + actual_len - 4);
 572        le32_to_cpus(&rx_hdr);
 573
 574        pkt_cnt = (u16)rx_hdr;
 575        hdr_off = (u16)(rx_hdr >> 16);
 576        pkt_hdr = (u32 *)(recv_buf + hdr_off);
 577
 578
 579        frame_pos = 0;
 580
 581        while (pkt_cnt--) {
 582                u16 pkt_len;
 583
 584                le32_to_cpus(pkt_hdr);
 585                pkt_len = (*pkt_hdr >> 16) & 0x1fff;
 586
 587                frame_pos += 2;
 588
 589                net_process_received_packet(recv_buf + frame_pos, pkt_len);
 590
 591                pkt_hdr++;
 592                frame_pos += ((pkt_len + 7) & 0xFFF8)-2;
 593
 594                if (pkt_cnt == 0)
 595                        return 0;
 596        }
 597        return err;
 598}
 599
 600static void asix_halt(struct eth_device *eth)
 601{
 602        debug("** %s()\n", __func__);
 603}
 604
 605/*
 606 * Asix probing functions
 607 */
 608void ax88179_eth_before_probe(void)
 609{
 610        curr_eth_dev = 0;
 611}
 612
 613struct asix_dongle {
 614        unsigned short vendor;
 615        unsigned short product;
 616        int flags;
 617};
 618
 619static const struct asix_dongle asix_dongles[] = {
 620        { 0x0b95, 0x1790, FLAG_TYPE_AX88179 },
 621        { 0x0b95, 0x178a, FLAG_TYPE_AX88178a },
 622        { 0x2001, 0x4a00, FLAG_TYPE_DLINK_DUB1312 },
 623        { 0x0df6, 0x0072, FLAG_TYPE_SITECOM },
 624        { 0x04e8, 0xa100, FLAG_TYPE_SAMSUNG },
 625        { 0x17ef, 0x304b, FLAG_TYPE_LENOVO },
 626        { 0x04b4, 0x3610, FLAG_TYPE_GX3 },
 627        { 0x0000, 0x0000, FLAG_NONE }   /* END - Do not remove */
 628};
 629
 630/* Probe to see if a new device is actually an asix device */
 631int ax88179_eth_probe(struct usb_device *dev, unsigned int ifnum,
 632                      struct ueth_data *ss)
 633{
 634        struct usb_interface *iface;
 635        struct usb_interface_descriptor *iface_desc;
 636        struct asix_private *dev_priv;
 637        int ep_in_found = 0, ep_out_found = 0;
 638        int i;
 639
 640        /* let's examine the device now */
 641        iface = &dev->config.if_desc[ifnum];
 642        iface_desc = &dev->config.if_desc[ifnum].desc;
 643
 644        for (i = 0; asix_dongles[i].vendor != 0; i++) {
 645                if (dev->descriptor.idVendor == asix_dongles[i].vendor &&
 646                    dev->descriptor.idProduct == asix_dongles[i].product)
 647                        /* Found a supported dongle */
 648                        break;
 649        }
 650
 651        if (asix_dongles[i].vendor == 0)
 652                return 0;
 653
 654        memset(ss, 0, sizeof(struct ueth_data));
 655
 656        /* At this point, we know we've got a live one */
 657        debug("\n\nUSB Ethernet device detected: %#04x:%#04x\n",
 658              dev->descriptor.idVendor, dev->descriptor.idProduct);
 659
 660        /* Initialize the ueth_data structure with some useful info */
 661        ss->ifnum = ifnum;
 662        ss->pusb_dev = dev;
 663        ss->subclass = iface_desc->bInterfaceSubClass;
 664        ss->protocol = iface_desc->bInterfaceProtocol;
 665
 666        /* alloc driver private */
 667        ss->dev_priv = calloc(1, sizeof(struct asix_private));
 668        if (!ss->dev_priv)
 669                return 0;
 670        dev_priv = ss->dev_priv;
 671        dev_priv->flags = asix_dongles[i].flags;
 672
 673        /*
 674         * We are expecting a minimum of 3 endpoints - in, out (bulk), and
 675         * int. We will ignore any others.
 676         */
 677        for (i = 0; i < iface_desc->bNumEndpoints; i++) {
 678                /* is it an interrupt endpoint? */
 679                if ((iface->ep_desc[i].bmAttributes &
 680                    USB_ENDPOINT_XFERTYPE_MASK) == USB_ENDPOINT_XFER_INT) {
 681                        ss->ep_int = iface->ep_desc[i].bEndpointAddress &
 682                                USB_ENDPOINT_NUMBER_MASK;
 683                        ss->irqinterval = iface->ep_desc[i].bInterval;
 684                        continue;
 685                }
 686
 687                /* is it an BULK endpoint? */
 688                if (!((iface->ep_desc[i].bmAttributes &
 689                     USB_ENDPOINT_XFERTYPE_MASK) == USB_ENDPOINT_XFER_BULK))
 690                        continue;
 691
 692                u8 ep_addr = iface->ep_desc[i].bEndpointAddress;
 693                if ((ep_addr & USB_DIR_IN) && !ep_in_found) {
 694                        ss->ep_in = ep_addr &
 695                                USB_ENDPOINT_NUMBER_MASK;
 696                        ep_in_found = 1;
 697                }
 698                if (!(ep_addr & USB_DIR_IN) && !ep_out_found) {
 699                        ss->ep_out = ep_addr &
 700                                USB_ENDPOINT_NUMBER_MASK;
 701                        dev_priv->maxpacketsize =
 702                                dev->epmaxpacketout[AX_ENDPOINT_OUT];
 703                        ep_out_found = 1;
 704                }
 705        }
 706        debug("Endpoints In %d Out %d Int %d\n",
 707              ss->ep_in, ss->ep_out, ss->ep_int);
 708
 709        /* Do some basic sanity checks, and bail if we find a problem */
 710        if (usb_set_interface(dev, iface_desc->bInterfaceNumber, 0) ||
 711            !ss->ep_in || !ss->ep_out || !ss->ep_int) {
 712                debug("Problems with device\n");
 713                return 0;
 714        }
 715        dev->privptr = (void *)ss;
 716        return 1;
 717}
 718
 719int ax88179_eth_get_info(struct usb_device *dev, struct ueth_data *ss,
 720                                struct eth_device *eth)
 721{
 722        struct asix_private *dev_priv = (struct asix_private *)ss->dev_priv;
 723
 724        if (!eth) {
 725                debug("%s: missing parameter.\n", __func__);
 726                return 0;
 727        }
 728        sprintf(eth->name, "%s%d", ASIX_BASE_NAME, curr_eth_dev++);
 729        eth->init = asix_init;
 730        eth->send = asix_send;
 731        eth->recv = asix_recv;
 732        eth->halt = asix_halt;
 733        eth->write_hwaddr = asix_write_hwaddr;
 734        eth->priv = ss;
 735
 736        if (asix_basic_reset(ss, dev_priv))
 737                return 0;
 738
 739        /* Get the MAC address */
 740        if (asix_read_mac(ss, eth->enetaddr))
 741                return 0;
 742        debug("MAC %pM\n", eth->enetaddr);
 743
 744        return 1;
 745}
 746
 747#else /* !CONFIG_DM_ETH */
 748
 749static int ax88179_eth_start(struct udevice *dev)
 750{
 751        struct asix_private *priv = dev_get_priv(dev);
 752
 753        return asix_init_common(&priv->ueth, priv);
 754}
 755
 756void ax88179_eth_stop(struct udevice *dev)
 757{
 758        struct asix_private *priv = dev_get_priv(dev);
 759        struct ueth_data *ueth = &priv->ueth;
 760
 761        debug("** %s()\n", __func__);
 762
 763        usb_ether_advance_rxbuf(ueth, -1);
 764        priv->pkt_cnt = 0;
 765        priv->pkt_data = NULL;
 766        priv->pkt_hdr = NULL;
 767}
 768
 769int ax88179_eth_send(struct udevice *dev, void *packet, int length)
 770{
 771        struct asix_private *priv = dev_get_priv(dev);
 772
 773        return asix_send_common(&priv->ueth, priv, packet, length);
 774}
 775
 776int ax88179_eth_recv(struct udevice *dev, int flags, uchar **packetp)
 777{
 778        struct asix_private *priv = dev_get_priv(dev);
 779        struct ueth_data *ueth = &priv->ueth;
 780        int ret, len;
 781        u16 pkt_len;
 782
 783        /* No packet left, get a new one */
 784        if (priv->pkt_cnt == 0) {
 785                uint8_t *ptr;
 786                u16 pkt_cnt;
 787                u16 hdr_off;
 788                u32 rx_hdr;
 789
 790                len = usb_ether_get_rx_bytes(ueth, &ptr);
 791                debug("%s: first try, len=%d\n", __func__, len);
 792                if (!len) {
 793                        if (!(flags & ETH_RECV_CHECK_DEVICE))
 794                                return -EAGAIN;
 795
 796                        ret = usb_ether_receive(ueth, priv->rx_urb_size);
 797                        if (ret < 0)
 798                                return ret;
 799
 800                        len = usb_ether_get_rx_bytes(ueth, &ptr);
 801                        debug("%s: second try, len=%d\n", __func__, len);
 802                }
 803
 804                if (len < 4) {
 805                        usb_ether_advance_rxbuf(ueth, -1);
 806                        return -EMSGSIZE;
 807                }
 808
 809                rx_hdr = *(u32 *)(ptr + len - 4);
 810                le32_to_cpus(&rx_hdr);
 811
 812                pkt_cnt = (u16)rx_hdr;
 813                if (pkt_cnt == 0) {
 814                        usb_ether_advance_rxbuf(ueth, -1);
 815                        return 0;
 816                }
 817
 818                hdr_off = (u16)(rx_hdr >> 16);
 819                if (hdr_off > len - 4) {
 820                        usb_ether_advance_rxbuf(ueth, -1);
 821                        return -EIO;
 822                }
 823
 824                priv->pkt_cnt = pkt_cnt;
 825                priv->pkt_data = ptr;
 826                priv->pkt_hdr = (u32 *)(ptr + hdr_off);
 827                debug("%s: %d packets received, pkt header at %d\n",
 828                      __func__, (int)priv->pkt_cnt, (int)hdr_off);
 829        }
 830
 831        le32_to_cpus(priv->pkt_hdr);
 832        pkt_len = (*priv->pkt_hdr >> 16) & 0x1fff;
 833
 834        *packetp = priv->pkt_data + 2;
 835
 836        priv->pkt_data += (pkt_len + 7) & 0xFFF8;
 837        priv->pkt_cnt--;
 838        priv->pkt_hdr++;
 839
 840        debug("%s: return packet of %d bytes (%d packets left)\n",
 841              __func__, (int)pkt_len, priv->pkt_cnt);
 842        return pkt_len;
 843}
 844
 845static int ax88179_free_pkt(struct udevice *dev, uchar *packet, int packet_len)
 846{
 847        struct asix_private *priv = dev_get_priv(dev);
 848        struct ueth_data *ueth = &priv->ueth;
 849
 850        if (priv->pkt_cnt == 0)
 851                usb_ether_advance_rxbuf(ueth, -1);
 852
 853        return 0;
 854}
 855
 856int ax88179_write_hwaddr(struct udevice *dev)
 857{
 858        struct eth_pdata *pdata = dev_get_platdata(dev);
 859        struct asix_private *priv = dev_get_priv(dev);
 860        struct ueth_data *ueth = &priv->ueth;
 861
 862        return asix_write_mac(ueth, pdata->enetaddr);
 863}
 864
 865static int ax88179_eth_probe(struct udevice *dev)
 866{
 867        struct eth_pdata *pdata = dev_get_platdata(dev);
 868        struct asix_private *priv = dev_get_priv(dev);
 869        struct usb_device *usb_dev;
 870        int ret;
 871
 872        priv->flags = dev->driver_data;
 873        ret = usb_ether_register(dev, &priv->ueth, AX_RX_URB_SIZE);
 874        if (ret)
 875                return ret;
 876
 877        usb_dev = priv->ueth.pusb_dev;
 878        priv->maxpacketsize = usb_dev->epmaxpacketout[AX_ENDPOINT_OUT];
 879
 880        /* Get the MAC address */
 881        ret = asix_read_mac(&priv->ueth, pdata->enetaddr);
 882        if (ret)
 883                return ret;
 884        debug("MAC %pM\n", pdata->enetaddr);
 885
 886        return 0;
 887}
 888
 889static const struct eth_ops ax88179_eth_ops = {
 890        .start = ax88179_eth_start,
 891        .send = ax88179_eth_send,
 892        .recv = ax88179_eth_recv,
 893        .free_pkt = ax88179_free_pkt,
 894        .stop = ax88179_eth_stop,
 895        .write_hwaddr = ax88179_write_hwaddr,
 896};
 897
 898U_BOOT_DRIVER(ax88179_eth) = {
 899        .name = "ax88179_eth",
 900        .id = UCLASS_ETH,
 901        .probe = ax88179_eth_probe,
 902        .ops = &ax88179_eth_ops,
 903        .priv_auto_alloc_size = sizeof(struct asix_private),
 904        .platdata_auto_alloc_size = sizeof(struct eth_pdata),
 905};
 906
 907static const struct usb_device_id ax88179_eth_id_table[] = {
 908        { USB_DEVICE(0x0b95, 0x1790), .driver_info = FLAG_TYPE_AX88179 },
 909        { USB_DEVICE(0x0b95, 0x178a), .driver_info = FLAG_TYPE_AX88178a },
 910        { USB_DEVICE(0x2001, 0x4a00), .driver_info = FLAG_TYPE_DLINK_DUB1312 },
 911        { USB_DEVICE(0x0df6, 0x0072), .driver_info = FLAG_TYPE_SITECOM },
 912        { USB_DEVICE(0x04e8, 0xa100), .driver_info = FLAG_TYPE_SAMSUNG },
 913        { USB_DEVICE(0x17ef, 0x304b), .driver_info = FLAG_TYPE_LENOVO },
 914        { USB_DEVICE(0x04b4, 0x3610), .driver_info = FLAG_TYPE_GX3 },
 915        { }             /* Terminating entry */
 916};
 917
 918U_BOOT_USB_DEVICE(ax88179_eth, ax88179_eth_id_table);
 919#endif /* !CONFIG_DM_ETH */
 920